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Drill bit eliminates delamination when drilling laminated material. It cuts or shaves the material as it progresses through it. The bit acts to hold down the material during drilling to prevent tearing or ripping and produces a clean, smooth and defect-free hole. It prevents chipping in stretched plastic windows for high-altitude, high-performance aircraft.
PCM telemetry bit synchronizer/signal conditioner, discussing bit acquisition, error and slippage rates
Self-synchronizing digital data communication systems usually use active or phase-locked loop (PLL) bit synchronizers. The three main elements of PLL synchronizers are the phase detector, loop filter, and the voltage controlled oscillator. Of these three elements, phase detector synthesis is the main source of difficulty, particularly when the received signals are demodulated square-wave signals. A phase detector synthesis technique is reviewed that provides a physically realizable design for bit synchronizer phase detectors. The development is based upon nonlinear recursive estimation methods. The phase detector portion of the algorithm is isolated and analyzed.
A prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. 8K-bit CCD shift register memories were used to construct a feasibility model 128K-bit buffer memory system. Peak power dissipation during a data transfer is less than 7 W., while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. Descriptions are provided of both the buffer memory system and a custom tester that was used to exercise the memory. The testing procedures and testing results are discussed. Suggestions are provided for further development with regards to the utilization of advanced versions of CCD memory devices to both simplified and expanded memory system applications.
A discrete phase state bit-synchronization loop is proposed for synchronization and detection of a binary nonreturn-to-zero (NRZ) process. The general loop model is developed for 11 and 17 phase states with optional sequential loop filter. Loop performance is considered in terms of the phase error density function, rms phase error, and mean time to bit slippage. It is shown that satisfactory loop performance can be achieved at -3 dB SNR through use of sequential loop filters.
Error rate of RF digital communication link is measured at low signal-to-noise ratios using this technique. In this method, identical pseudo-random sequences of pulses are generated at transmitter and receiver of link. However, comparison of two sequences at receiver involves integration that makes bit-tracking threshold depend on length of pseudo-random sequence, rather than on actual rate of transmission of individual bits.
Digital fiber-optic data-link terminal modules are being developed in a number of laboratories, and often the modules take the form of black boxes without convenient access to internal signals. This paper discusses types of measurements which can be made using only the digital terminals of the link. Bit-error-rate (BER) vs signal-power data can, of course, provide a means for proving overall link performance, but it can also be used to determine certain internal parameters of the receiver. The theoretical dependence of the BER-vs-light-signal-power curve shape on receiver input-noise equivalent power and comparator slicing level is discussed. BER-vs-light-signal-power measurements obtained with an experimental link are presented and interpreted with the aid of the theoretical curves. The effects of other problems, such as hum or oscillation, on the BER data are mentioned. Sensitivity of the system BER to bit rate is also discussed, with application to determining system operating limits. Since BER measurements are simple to make and can easily be automated, they may prove to be a useful means for either laboratory evaluation or production-line acceptance testing of sealed terminal modules.
Two bit synchronizer-signal conditioners (BSSC) developed for NASA high data rate applications such as earth resources monitoring are described. One BSSC is centered at 120 MB/s and the other at 240 Mb/s. These subsystems are featured out of the total hardware developed because the BSSC is such a key subsystem in determining overall system statistical performance. These units represent an evolution of high data rate BSSC's available at low data rates. Numerous inputs/outputs, control functions, indicators, plus the ability to minimize the effects of various signal perturbations are provided. Examples of allowed perturbations are input level variations, bit rate variance static and dynamic, baseline, transition density, bandlimiting, etc., as well as noise. Emphasis in the past has been primarily concerned only with noise.
A modular concept with three separate modules roughly separating bubble domain technology, control logic technology, and power supply technology was employed. These modules were respectively the standard memory module (SMM), the data control unit (DCU), and power supply module (PSM). The storage medium was provided by bubble domain chips organized into memory cells. These cells and the circuitry for parallel data access to the cells make up the SMM. The DCU provides a flexible serial data interface to the SMM. The PSM provides adequate power to enable one DCU and one SMM to operate simultaneously at the maximum data rate. The SSM was designed to handle asynchronous data rates from dc to 1.024 Mbs with a bit error rate less than 1 error in 10 to the eight power bits. Two versions of the SSM, a serial data memory and a dual parallel data memory were specified using the standard modules. The SSM specification includes requirements for radiation hardness, temperature and mechanical environments, dc magnetic field emission and susceptibility, electromagnetic compatibility, and reliability.
A multiple speed bit synchronizer was designed for installation in an inertial navigation system data decoder to extract non-return-to-zero level data and clock signal from biphase level data. The circuit automatically senses one of four pre-determined biphase data rates and synchronizes the proper clock rate to the data. Through a simple expansion of the basic design, synchronization of more than four binarily related data rates can be accomplished. The design provides an easily adaptable, low cost, low power alternative to external bit synchronizers with additional savings in size and weight.
Pulse distortion and intersymbol interference due to insufficient filtering in PCM and PSK channels cause performance degradation in terms of both bit error probabilities and timing errors. This paper reports the results of a study analyzing these effects on bit timing subsystems. Consideration is given to both the filter-rectifier and transition tracking type of timing subsystem. Although both these systems perform similarly in high SNR and ideal pulse models, pulse distortion and intersymbol affects each differently. The primary effects in both systems is to cause the presence of an irreducible mean squared timing error due to the intersymbol which limits the ultimate performance. Design procedures to minimize the anomalies of both systems are presented, and indicate modifications of the standard timing subsystems. It is found that specific design directions depend on whether the intersymbol or the receiver noise tends to dominate.
A computer simulation program that is used to study the effects of digitization in spaceborne synthetic aperture radar systems is described. An analytical study of the distortion noise introduced by the digitization process at various gain settings, sampling rates and bit error rates is presented and the results agree well with those obtained from the simulation program. The simulation program is also used to study the spatial frequency response of hard-limiting (quantizing to 1-bit) synthetic aperture radar systems. The implications of these results on synthetic aperture radar system design are discussed.
The design to achieve the required bit transition density for the Space Shuttle high rate multiplexes (HRM) data stream of the Space Laboratory Vehicle is reviewed. It contained a recommended circuit approach, specified the pseudo random (PN) sequence to be used and detailed the properties of the sequence. Calculations showing the probability of failing to meet the required transition density were included. A computer simulation of the data stream and PN cover sequence was provided. All worst case situations were simulated and the bit transition density exceeded that required. The Preliminary Design Review and the critical Design Review are documented. The Cover Sequence Generator (CSG) Encoder/Decoder design was constructed and demonstrated. The demonstrations were successful. All HRM and HRDM units incorporate the CSG encoder or CSG decoder as appropriate.
Instead of using the criterion of maximum free distance, (df) or the maximum (df) with minimizing a few first distance profiles, short constraint length rate 1/N convolution codes were searched using a criterion of minimizing required bit energy-to-noise density ratio, E(b)/N(o), for a given value of desired bit error rate (BER), for the goodness of a code. The considered channel was binary antipodal signaling over additive white Gaussian noise and no quantization at the channel output. For the BER calculations, the transfer function bounding technique was used. Partial searches were performed using some known facts and a very useful idea that "good codes generate good codes.'' That is, for a given constraint length K, good rate 1/(N + 1) codes can be found by extending the code generator matrices of good rate 1/N codes. The code search results are tabulated for 3 or = K or = 7 and 2 or = N or = 8. For many pairs of K and N, the new codes are shown to save 0.1 to 0.4 dB in the required E(b)/N(o) compared to previously reported codes. Additionally, the benefits of coding bandwidth expansion are confirmed with the new codes.
For rate 1/N convolutional codes, a recursive algorithm for finding the transfer function bound on bit error rate (BER) at the output of a Viterbi decoder is described. This technique is very fast and requires very little storage since all the unnecessary operations are eliminated. Using this technique, we find and plot bounds on the BER performance of known codes of rate 1/2 with K 18, rate 1/3 with K 14. When more than one reported code with the same parameter is known, we select the code that minimizes the required signal to noise ratio for a desired bit error rate of 0.000001. This criterion of determining goodness of a code had previously been found to be more useful than the maximum free distance criterion and was used in the code search procedures of very short constraint length codes. This very efficient technique can also be used for searches of longer constraint length codes.
The bit error rate (BER) for the coherent detection of M-ary PSK signals with Gray code bit mapping is considered. A closed-form expression for the exact BER of M-ary PSK is presented. Tight upper and lower bounds on BER are also obtained for M-ary PSK with larger M.
It is shown that single-event-upsets (SEUs) due to cosmic rays are a significant source of single bit error in spacecraft computers. The physical mechanism of SEU, electron hole generation by means of Linear Energy Transfer (LET), it discussed with reference made to the results of a study of the environmental effects on computer systems of the Galileo spacecraft. Techniques for making software more tolerant of cosmic ray effects are considered, including: reducing the number of registers used by the software; continuity testing of variables; redundant execution of major procedures for error detection; and encoding state variables to detect single-bit changes. Attention is also given to design modifications which may reduce the cosmic ray exposure of on-board hardware. These modifications include: shielding components operating in LEO; removing low-power Schottky parts; and the use of CMOS diodes. The SEU parameters of different electronic components are listed in a table.
A Very Large Scale Integration (VLSI) architecture and layout for an 8-bit finite field multiplier is described. The algorithm used in this design was developed by Massey and Omura. A normal basis representation of finite field elements is used to reduce the multiplication complexity. It is shown that a drastic improvement was achieved in this design. This multiplier will be used intensively in the implementation of an 8-bit Reed-Solomon decoder and in many other related projects.