Engineering PapersSearch

SEARCH · Engineering Papers

Results for “avionics interfaces”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 73 records · Page 4

Space Generic Open Avionics Architecture (SGOAA) reference model technical guide

This report presents a full description of the Space Generic Open Avionics Architecture (SGOAA). The SGOAA consists of a generic system architecture for the entities in spacecraft avionics, a generic processing architecture, and a six class model of interfaces in a hardware/software system. The purpose of the SGOAA is to provide an umbrella set of requirements for applying the generic architecture interface model to the design of specific avionics hardware/software systems. The SGOAA defines a generic set of system interface points to facilitate identification of critical interfaces and establishes the requirements for applying appropriate low level detailed implementation standards to those interface points. The generic core avionics system and processing architecture models provided herein are robustly tailorable to specific system applications and provide a platform upon which the interface model is to be applied.

Wray, Richard B.

Investigation of an advanced fault tolerant integrated avionics system

Presented is an advanced, fault-tolerant multiprocessor avionics architecture as could be employed in an advanced rotorcraft such as LHX. The processor structure is designed to interface with existing digital avionics systems and concepts including the Army Digital Avionics System (ADAS) cockpit/display system, navaid and communications suites, integrated sensing suite, and the Advanced Digital Optical Control System (ADOCS). The report defines mission, maintenance and safety-of-flight reliability goals as might be expected for an operational LHX aircraft. Based on use of a modular, compact (16-bit) microprocessor card family, results of a preliminary study examining simplex, dual and standby-sparing architectures is presented. Given the stated constraints, it is shown that the dual architecture is best suited to meet reliability goals with minimum hardware and software overhead. The report presents hardware and software design considerations for realizing the architecture including redundancy management requirements and techniques as well as verification and validation needs and methods.

Dunn, W. R.

Orbiter CIU/IUS communications hardware evaluation

The DOD and NASA inertial upper stage communication system design, hardware specifications and interfaces were analyzed to determine their compatibility with the Orbiter payload communications equipment (Payload Interrogator, Payload Signal Processors, Communications Interface Unit, and the Orbiter operational communications equipment (the S-Band and Ku-band systems). Topics covered include (1) IUS/shuttle Orbiter communications interface definition; (2) Orbiter avionics equipment serving the IUS; (3) IUS communication equipment; (4) IUS/shuttle Orbiter RF links; (5) STDN/TDRS S-band related activities; and (6) communication interface unit/Orbiter interface issues. A test requirement plan overview is included.

Huth, G. K.

General Purpose Computer (GPC) to GPC systems interface description

The General Purpose Computer (GPC) 'subsystem' of the Orbiter Data Processing System was described. Two interface areas are discussed. One is the area of GPC intraconnections and intracommunications involving the hardware/software interface between the Central Processing Unit (CPU) and the Input/Output Processor (IOP). The other is the area of GPC interconnections and intercommunications and involves the hardware/software interface between the five Orbiter GPC's. Based on the detailed GPC interface given, it is felt that the basic CPU to IOP interface and the GPC to GPC interface have the potential for trouble free operation. However, due to the complexity of the interface and the criticality of GPC synchronization to overall avionics performance, the GPC to GPC interface should be carefully evaluated when attempting to resolve test anomalies that may involve GPC timing and synchronization errors.

Breyer, B. C.

Thermal Interface Comparisons Under Flight Like Conditions

Thermal interface materials are used in bolted interfaces to promote good thermal conduction between the two. The mounting surface can include panels, heat pipes, electronics boxes, etc.. . On Lunar Reconnaissance Orbiter (LRO) project the results are directly applicable: a) Several high power avionics boxes b) Several interfaces from RWA to radiator through heat pipe network

Rodriquez-Ruiz, Juan

Launch site payload test configurations for Space Shuttle scientific payloads

This paper provides an overview of the test configurations which are utilized in prelaunch testing at the John F. Kennedy Space Center (KSC) for those scientific payloads which are flown in the National Space Transportation System (NSTS) Space Shuttle. A generalized view of the payload prelaunch processing is provided and the major types of payload configurations are described. The majority of the prelaunch test activity involves the verification of experiment functions, compatibility of experiment-to-carrier interfaces and payload-to-orbiter interfaces. The Shuttle's avionics system is presented as it relates to payloads. The testing of Spacelab experiments and the experiment-to-Spacelab compatibility verification is described as is the test activity for partial payloads and their experiments. Test operations which involve simulated orbiter interface verification and actual payload-to-orbiter testing are discussed. An overview of the Space Station payload processing concept is presented.

Schuiling, Roelof L.

Space Generic Open Avionics Architecture (SGOAA) standard specification

The purpose of this standard is to provide an umbrella set of requirements for applying the generic architecture interface model to the design of a specific avionics hardware/software system. This standard defines a generic set of system interface points to facilitate identification of critical interfaces and establishes the requirements for applying appropriate low level detailed implementation standards to those interface points. The generic core avionics system and processing architecture models provided herein are robustly tailorable to specific system applications and provide a platform upon which the interface model is to be applied.

Wray, Richard B.

A Definition of STS Accommodations for Attached Payloads

An input to a study conducted to define a set of carrier avionics for supporting large structures experiments attached to the Space Shuttle Orbiter is reported. The "baseline" Orbier interface used in developing the avionics concept for the Space Technology Experiments Platform, STEP, which Langley Research Center has proposed for supporting experiments of this sort is defined. Primarily, flight operations capabilities and considerations and the avionics systems capabilities that are available to a payload as a "mixed cargo" user of the Space Transportation System are addressed. Ground operations for payload integration at Kennedy Space Center, and ground operations for payload support during the mission are also discussed.

Echols, F. L.

Tug avionics system overview

The recently defined Tug avionics system takes maximum advantage of projected technology advances to attain: low system weight; power system capacity essentially independent of mission duration; sensors for rendezvous, docking, and navigation update; all attitude communications; onboard checkout and redundancy management; and modular fault tolerant computer control. The requirements, selection trades, and configurations are discussed for the major subsystems: data management, guidance navigation and control, communications, rendezvous and docking, and electrical power. The integrated avionics system and the interfaces with the payload, Shuttle and ground are described.

Raaberg, M. T.

Shuttle orbiter S-band communications equipment design evaluation

An assessment of S-band communication equipment includes: (1) the review and analysis of the ability of the various subsystem avionic equipment designs to interface with, and operate on signals from/to adjoining equipment; (2) the performance peculiarities of the hardware against the overall specified system requirements; and (3) the evaluation of EMC EMI test results of the various equipment with respect to the possibility of mutual interferences.

Springett, J. C.

A thermal control approach for a solar electric propulsion thrust subsystem

A thrust subsystem thermal control design is defined for a Solar Electric Propulsion System (SEPS) proposed for the comet Halley Flyby/comet Tempel 2 rendezvous mission. A 114 node analytic model, developed and coded on the systems improved numerical differencing analyzer program, was employed. A description of the resulting thrust subsystem thermal design is presented as well as a description of the analytic model and comparisons of the predicted temperature profiles for various SEPS thermal configurations that were generated using this model. It was concluded that: (1) a BIMOD engine system thermal design can be autonomous; (2) an independent thrust subsystem thermal design is feasible; (3) the interface module electronics temperatures can be controlled by a passive radiator and supplementary heaters; (4) maintaining heat pipes above the freezing point would require an additional 322 watts of supplementary heating power for the situation where no thrusters are operating; (5) insulation is required around the power processors, and between the interface module and the avionics module, as well as in those areas which may be subjected to solar heating; and (6) insulation behind the heat pipe radiators is not necessary.

Maloy, J. E.

Thermal energy management process experiment

The thermal energy management processes experiment (TEMP) will demonstrate that through the use of two-phase flow technology, thermal systems can be significantly enhanced by increasing heat transport capabilities at reduced power consumption while operating within narrow temperature limits. It has been noted that such phenomena as excess fluid puddling, priming, stratification, and surface tension effects all tend to mask the performance of two-phase flow systems in a 1-g field. The flight experiment approach would be to attack the experiment to an appropriate mounting surface with a 15 to 20 meter effective length and provide a heat input and output station in the form of heaters and a radiator. Using environmental data, the size, location, and orientation of the experiment can be optimized. The approach would be to provide a self-contained panel and mount it to the STEP through a frame. A small electronics package would be developed to interface with the STEP avionics for command and data handling. During the flight, heaters on the evaporator will be exercised to determine performance. Flight data will be evaluated against the ground tests to determine any anomalous behavior.

Ollendorf, S.

Software Model Checking of ARINC-653 Flight Code with MCP

The ARINC-653 standard defines a common interface for Integrated Modular Avionics (IMA) code. In particular, ARINC-653 Part 1 specifies a process- and partition-management API that is analogous to POSIX threads, but with certain extensions and restrictions intended to support the implementation of high reliability flight code. MCP is a software model checker, developed at NASA Ames, that provides capabilities for model checking C and C++ source code. In this paper, we present recent work aimed at implementing extensions to MCP that support ARINC-653, and we discuss the challenges and opportunities that consequentially arise. Providing support for ARINC-653 s time and space partitioning is nontrivial, though there are implicit benefits for partial order reduction possible as a consequence of the API s strict interprocess communication policy.

Thompson, Sarah J.

FAILSAFE Health Management for Embedded Systems

The FAILSAFE project is developing concepts and prototype implementations for software health management in mission- critical, real-time embedded systems. The project unites features of the industry-standard ARINC 653 Avionics Application Software Standard Interface and JPL s Mission Data System (MDS) technology (see figure). The ARINC 653 standard establishes requirements for the services provided by partitioned, real-time operating systems. The MDS technology provides a state analysis method, canonical architecture, and software framework that facilitates the design and implementation of software-intensive complex systems. The MDS technology has been used to provide the health management function for an ARINC 653 application implementation. In particular, the focus is on showing how this combination enables reasoning about, and recovering from, application software problems.

Horvath, Gregory A.

BRAINSTACK – A Platform for Artificial Intelligence & Machine Learning Collaborative Experiments on a Nano-Satellite

As space missions continue to become more ambitious, complex, and distant to Earth, the need for advanced on-board intelligent decision making to guide everything from mission operations to fault detection and recovery has become a major front of space research. While the prevalence of research on such Artificial Intelligence / Machine Learning (AI/ML) modules has exploded, the capacity to experimentally validate such modules in space in a rapid and inexpensive format has not. To this end, the Nano Orbital Workshop (NOW) group at NASA Ames Research Center has been at the forefront of performing initial flight evaluation tests of ‘commercially’ available AI/ML computational platforms via the TechEdSat (TES-n) flight series as part of what is programmatically referred to as the BRAINSTACK. BRAINSTACK will provide an orbital AI/ML evaluation laboratory where computational experiments are pre-loaded into memory prior to launch, and then executed as desired during the mission, with results reported back and program tweaks or new data sets uploaded as needed. Processors selected as part of the BRAINSTACK are of ideal size, packaging, and power consumption for easy integration into a cube satellite structure. These experiments have included the evaluation of small, high-performance GPUs and more recently, neuromorphic processors in LEO operations. Neuromorphic processors are of particular interest due to their superior computational power efficiency over GPUs. The first TES-n flight test of an Intel first-generation Loihi neuromorphic processor launched on January 13, 2022 and continues to operate in orbit despite almost no space environment modifications. The Intel Loihi Gen-1 is characterized by a 14nm 128-core Spiking Neural Network (SNN) able to support on-chip training. This experiment utilized a Loihi packaged in the ‘Kapoho Bay’ USB module, providing a relatively straight-forward interface to the bus avionics system. The Kapoho Bay was in turn managed by a host Intel Pentium single-board computer to handle scheduling of the AI/ML application payloads, and communications with the satellite vehicle manager. The recently released Intel Loihi Gen-2, able to support integer-valued spike payloads and produced using 7nm process, will form part of the basis of the evolving BRAINSTACK in the upcoming three TES-n/NOW flights. Additionally, it is planned to measure the radiation environment these processors experience to understand any degradation or computational artifacts caused by long term space radiation exposure on these novel architectures. This evolving flexible and collaborative environment involving various research teams across NASA and other organizations is intended to be a convenient orbital test platform from which many anticipated future space AI/ML applications may be initially tested.

Artificial Intelligence

BRAINSTACK – A Platform for Artificial Intelligence & Machine Learning Collaborative Experiments on a Nano-Satellite

As space missions continue to become more ambitious, complex, and distant to Earth, the need for advanced on-board intelligent decision making to guide everything from mission operations to fault detection and recovery has become a major front of space research. While the prevalence of research on such Artificial Intelligence / Machine Learning (AI/ML) modules has exploded, the capacity to experimentally validate such modules in space in a rapid and inexpensive format has not. To this end, the Nano Orbital Workshop (NOW) group at NASA Ames Research Center has been at the forefront of performing initial flight evaluation tests of ‘commercially’ available AI/ML computational platforms via the TechEdSat (TES-n) flight series as part of what is programmatically referred to as the BRAINSTACK. BRAINSTACK will provide an orbital AI/ML evaluation laboratory where computational experiments are pre-loaded into memory prior to launch, and then executed as desired during the mission, with results reported back and program tweaks or new data sets uploaded as needed. Processors selected as part of the BRAINSTACK are of ideal size, packaging, and power consumption for easy integration into a cube satellite structure. These experiments have included the evaluation of small, high-performance GPUs and more recently, neuromorphic processors in LEO operations. Neuromorphic processors are of particular interest due to their superior computational power efficiency over GPUs. The first TES-n flight test of an Intel first-generation Loihi neuromorphic processor launched on January 13, 2022 and continues to operate in orbit despite almost no space environment modifications. The Intel Loihi Gen-1 is characterized by a 14nm 128-core Spiking Neural Network (SNN) able to support on-chip training. This experiment utilized a Loihi packaged in the ‘Kapoho Bay’ USB module, providing a relatively straight-forward interface to the bus avionics system. The Kapoho Bay was in turn managed by a host Intel Pentium single-board computer to handle scheduling of the AI/ML application payloads, and communications with the satellite vehicle manager. The recently released Intel Loihi Gen-2, able to support integer-valued spike payloads and produced using 7nm process, will form part of the basis of the evolving BRAINSTACK in the upcoming three TES-n/NOW flights. Additionally, it is planned to measure the radiation environment these processors experience to understand any degradation or computational artifacts caused by long term space radiation exposure on these novel architectures. This evolving flexible and collaborative environment involving various research teams across NASA and other organizations is intended to be a convenient orbital test platform from which many anticipated future space AI/ML applications may be initially tested.

Artificial Intelligence

BRAINSTACK – A Platform for Artificial Intelligence & Machine Learning Collaborative Experiments on a Nano-Satellite

As the space economy continues to expand through increasingly easy access to advanced and inexpensive technology, space missions themselves have become more ambitious with exploration targets growing ever distant while simultaneously requiring larger guidance and communication budgets. These conflicting desires of distance and control drive the need for advanced on-board intelligent decision making to reduce communication and control limitations by automating as many mission functions as possible in-situ. While the amount of research on such Artificial Intelligence and Machine Learning (AI/ML) software modules has grown exponentially, the capacity to experimentally validate such software modules in space in a rapid and inexpensive format has not. To this end, the Nano Orbital Workshop (NOW) group at NASA Ames Research Center has been at the forefront of performing initial flight evaluation tests of ‘commercially’ available bleeding-edge computational platforms via what is programmatically referred to as the BrainStack on the TechEdSat (TES-n) flight series. This on-orbit computational platform provides an evaluation laboratory where advanced software experiments are pre-loaded into memory prior to launch, then executed as payloads during mission operations with results reported back and program tweaks or new training sets uploaded as needed. Processors selected as part of the BrainStack are of ideal size, packaging, and power consumption for easy integration into a cube satellite structure. These experiments have included the evaluation of small, high-performance GPUs and, more recently, neuromorphic processors, in LEO operations. Neuromorphic processors are of particular interest due to their superior power efficiency over GPUs in intelligent automation applications. The first TES-n flight test of an Intel first-generation Loihi neuromorphic processor launched on TES-13, January 13, 2022, and continues to operate in orbit despite no significant modifications to harden the processor against the space environment. The Intel Loihi Gen-1 on TES-13 is characterized by a 14nm 128-core Spiking Neural Network (SNN) able to support on-chip training. The processor is packaged in the Kapoho Bay USB module, providing a relatively straight-forward interface to the bus avionics system. The Kapoho Bay was in turn managed by an Intel Pentium single-board computer to handle scheduling of the software application payloads and communications with the satellite’s primary computer. The recently released Intel Loihi Gen-2, able to support integer-valued spike payloads and produced using 7nm process, will form part of the continually evolving BrainStack in the upcoming three TES-n/NOW flights. The Kapoho Point unit will incorporate eight Loihi-2 processors, enabling neural networks of up to one million neurons and one billion synapsis. Additionally, it is planned to measure the radiation environment these processors experience to understand any degradation or computational artifacts caused by long term space radiation exposure on these novel architectures. This evolving flexible and collaborative environment involving various research teams across NASA and other organizations is intended to be a convenient orbital test platform from which many anticipated future space automation applications may be initially tested.

Artificial Intelligence

Design of an Ada expert system shell for the VHSIC avionic modular flight processor

The Embedded Computer System Expert System Shell (ES Shell) is an Ada-based expert system shell developed at the Avionics Laboratory for use on the VHSIC Avionic Modular Processor (VAMP) running under the Ada Avionics Real-Time Software (AARTS) Operating System. The ES Shell provides the interface between the expert system and the avionics environment, and controls execution of the expert system. Testing of the ES Shell in the Avionics Laboratory's Integrated Test Bed (ITB) has demonstrated its ability to control a non-deterministic software application executing on the VAMP's which can control the ITB's real-time closed-loop aircraft simulation. The results of these tests and the conclusions reached in the design and development of the ES Shell have played an important role in the formulation of the requirements for a production-quality expert system inference engine, an ingredient necessary for the successful use of expert systems on the VAMP embedded avionic flight processor.

Fanning, F. Jesse