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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS2013

Remote Memory Access Protocol Target Node Intellectual Property

The MagnetoSpheric Multiscale (MMS) mission had a requirement to use the Remote Memory Access Protocol (RMAP) over its SpaceWire network. At the time, no known intellectual property (IP) cores were available for purchase. Additionally, MMS preferred to implement the RMAP functionality with control over the low-level details of the design. For example, not all the RMAP standard functionality was needed, and it was desired to implement only the portions of the RMAP protocol that were needed. RMAP functionality had been previously implemented in commercial off-the-shelf (COTS) products, but the IP core was not available for purchase. The RMAP Target IP core is a VHDL (VHSIC Hardware Description Language description of a digital logic design suitable for implementation in an FPGA (field-programmable gate array) or ASIC (application-specific integrated circuit) that parses SpaceWire packets that conform to the RMAP standard. The RMAP packet protocol allows a network host to access and control a target device using address mapping. This capability allows SpaceWire devices to be managed in a standardized way that simplifies the hardware design of the device, as well as the development of the software that controls the device. The RMAP Target IP core has some features that are unique and not specified in the RMAP standard. One such feature is the ability to automatically abort transactions if the back-end logic does not respond to read/write requests within a predefined time. When a request times out, the RMAP Target IP core automatically retracts the request and returns a command response with an appropriate status in the response packet s header. Another such feature is the ability to control the SpaceWire node or router using RMAP transactions in the extended address range. This allows the SpaceWire network host to manage the SpaceWire network elements using RMAP packets, which reduces the number of protocols that the network host needs to support.

Haddad, Omar↗
NASA NTRS2013

Rad-Hard Structured ASIC Body of Knowledge

Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application

Heidecker, Jason↗
NASA NTRS2015

Data Concentrator

Orbital Research, Inc., developed, built, and tested three high-temperature components for use in the design of a data concentrator module in distributed turbine engine control. The concentrator receives analog and digital signals related to turbine engine control and communicates with a full authority digital engine control (FADEC) or high-level command processor. This data concentrator follows the Distributed Engine Controls Working Group (DECWG) roadmap for turbine engine distributed controls communication development that operates at temperatures at least up to 225 C. In Phase I, Orbital Research developed detailed specifications for each component needed for the system and defined the total system specifications. This entailed a combination of system design, compiling existing component specifications, laboratory testing, and simulation. The results showed the feasibility of the data concentrator. Phase II of this project focused on three key objectives. The first objective was to update the data concentrator design modifications from DECWG and prime contractors. Secondly, the project defined requirements for the three new high-temperature, application-specific integrated circuits (ASICs): one-time programmable (OTP), transient voltage suppression (TVS), and 3.3V. Finally, the project validated each design by testing over temperature and under load.

Willett, Mike↗
NASA NTRS2016

Development and Performance of a Suprathermal Electron Spectrometer to Study Auroral Precipitations

The design, development, and performance of Medium-energy Electron SPectrometer (MESP), dedicated to the in situ observation of suprathermal electrons in the auroral ionosphere, are summarized in this paper. MESP employs a permanent magnet filter with a light tight structure to select electrons with proper energies guided to the detectors. A combination of two avalanche photodiodes and a large area solid-state detector (SSD) provided 46 total energy bins (1 keV resolution for 3-20 keV range for APDs, and 7 keV resolution for greater than 20 keV range for SSDs). Multi-channel ultra-low power application-specific integrated circuits are also verified for the flight operation to read-out and analyze the detector signals. MESP was launched from Poker F1at Research Range on 3 March 2014 as a part of ground-to-rocket electrodynamics-electrons correlative experiment (GREECE) mission. MESP successfully measured the precipitating electrons from 3 to 120 keV in 120-ms time resolution and characterized the features of suprathermal distributions associated with auroral arcs throughout the flight. The measured electrons were showing the inverted-V type spectra, consistent with the past measurements. In addition, investigations of the suprathermal electron population indicated the existence of the energetic non-thermal distribution corresponding to the brightest aurora.

Ogasawara, Keiichi↗
NASA NTRS2016

A Low-Power Correlator ASIC for Arrays with Many Antennas

We report the design of a new application-specific integrated circuit (ASIC) for use in radio telescope correlators. It supports the construction of correlators for an arbitrarily large number of signals. The ASIC uses an intrinsically low-power architecture along with design techniques and a process that together result in unprecedentedly low power consumption. The design is flexible in that it can support telescopes with almost any number of antennas N. It is intended for use in an "FX" correlator, where a uniform filter bank breaks each signal into separate frequency channels prior to correlation.

radio telescopes↗
NASA NTRS2018

Guideline for Single-Event Effect (SEE) Testing of System on a Chip (SOC) Devices

The use of complex single and multicore processors with significant cache memory, on-chip peripherals, memory controllers, and high speed input/output (IO) that integrate many of the parts of a traditional computer system is becoming more common in space applications. Such devices are often referred to as system on a chip devices (SOCs), even though the term is used somewhat inaccurately due to the lack of analog and mixed signal subcircuits. These devices are complex combinations of single- or multi-core processors with memory controllers, high-speed input/output (IO), and other peripheral structures that formerly would have been handled by off-chip resources. In the past the processors were tested for single event effects (SEE) separately, and the peripherals were often put into custom application-specific integrated circuits (ASICs) along with other resources required by the user. Performance and cost pressures have pushed commercial devices to incorporate many of the functional blocks into a single chip, an SOC. The NASA Electronic Parts and Packaging Program (NEPP) has been examining ways to perform SEE radiation hardness assurance (RHA) testing of these processor-centric SOCs to achieve reasonable understanding of their performance in space missions.

Guertin, Steven M.↗
NASA NTRS2022

Single-Event Effect Testing of the PNI RM3100 Magnetometer for Space Applications

The results of a destructive single-event effect susceptibility radiation test of the PNI RM3100 magnetometer sensor, specifically the MagI 2 C ASIC (application-specific integrated circuit) on the sensor board are presented. The sensor is a low-resource commercial off-the-shelf (COTS) magneto-inductive magnetometer. The device was monitored for destructive events and functional interruptions during exposure to a heavy ion beam at the Lawrence Berkeley National Laboratory's 88′′ Cyclotron. The RM3100 did not experience any destructive single-event effects when irradiated to a total fluence of 1.4 × 10 7 cm −2 at an effective linear energy transfer (LET) of 76.7 MeV cm 2 mg −1 while operated at nominal voltage (3.3 V) and elevated temperature (85 ∘C). When these results are combined with previous total ionizing dose tests showing no failures up to 150 kRad (Si), we conclude that the PNI RM3100 is extremely radiation tolerant and can be used in a variety of space environments.

Mark B. Moldwin↗
DOE OSTI2024

An Open-Source Framework for Rapid Validation of Scientific ASICs

Spacely is an open-source framework for the post-silicon validation of analog, digital, and mixed-signal ASICs (Application-Specific Integrated Circuits) which maximizes the reuse of hardware and software, reducing the time taken to achieve meaningful test results. Spacely specifically addresses the needs of small, flexible ASIC design teams commonly found in academia or research institutions which benefit most from sharing the overhead of test stand creation between many unique ASIC designs. Spacely is a set of software, firmware, and design practices. It targets two primary hardware platforms (NI-PXI and Caribou) as well as offering extensible support for bench instruments. Spacely provides a high-level Python interface to all test hardware for accessibility, while also giving more sophisticated teams the opportunity to integrate custom test firmware. The design principles of Spacely are presented, along with a demonstrative example of using Spacely to test a pixel detector readout ASIC.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware

We present hls4ml, a free and open-source platform that translates machine learning (ML) models from modern deep learning frameworks into high-level synthesis (HLS) code that can be integrated into full designs for field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). With its flexible and modular design, hls4ml supports a large number of deep learning frameworks and can target HLS compilers from several vendors, including Vitis HLS, Intel oneAPI and Catapult HLS. Together with a wider eco-system for software-hardware co-design, hls4ml has enabled the acceleration of ML inference in a wide range of commercial and scientific applications where low latency, resource usage, and power consumption are critical. In this paper, we describe the structure and functionality of the hls4ml platform. The overarching design considerations for the generated HLS code are discussed, together with selected performance results.

Schulte, Jan-Frederik [Purdue U.] (ORCID:000000034↗
DOE OSTI2025

Automating Testing of DUNE Electronics via a Finite State Machine

The Deep Underground Neutrino Experiment (DUNE) is a flagship international collaboration designed to study neutrinos—tiny, nearly massless particles that may hold answers to fundamental questions about the Universe. Fermilab’s Robotic Test Stand (RTS) plays a critical role in ensuring the quality of approximately 50,000 Application-Specific Integrated Circuit (ASIC) chips that will be used in DUNE’s massive liquid argon detectors. These electronics will be inside the cryostat; therefore, they will need to have a high yield of working chips and low noise. To improve the automation and reliability of the RTS, this project focused on designing and implementing a Python-based finite state machine (FSM) to manage chip handling workflows. The FSM was developed as a modular software framework to coordinate robotic arm movements, manage chip tray positions, and monitor system states during testing. Key features include robust error handling routines, a pause/resume system for safe mid-cycle interruptions, and a simulation mode for iterative testing without hardware dependencies. The system was designed to prepare for seamless integration with RTS hardware components such as the robotic arm and vision system. This integration will streamline collaboration and enable efficient deployment of updates across the six institutions performing testing. The outcomes of this internship contribute to Fermilab’s mission to advance high-energy physics and support the DOE’s national goals by directly improving the testing of equipment to be used in DUNE. The project also provided valuable experience in software design and contributing to the success of DUNE.

Kang, Caleb [Fermilab]↗
DOE OSTI2026

On-chip probabilistic inference for charged-particle tracking at the sensor edge

Modern scientific instruments operate under increasingly extreme constraints on bandwidth, latency, and power. Inference at the sensor edge determines experimental data collection efficiency by deciding which information to save for further analysis. Particle tracking detectors at the Large Hadron Collider exemplify this challenge: pixelated silicon sensors generate rich spatiotemporal ionization patterns, yet most of this information is discarded due to data-rate limitations. Concurrently, advancements in co-design tools provide rapid turn-around for incorporating machine learning into application-specific integrated circuits, motivating designs for particle detectors with new integrated technologies. We demonstrate that neural networks embedded in the front-end electronics can infer charged-particle kinematic parameters from a single silicon layer. We regress hit positions and incident angles with calibrated uncertainties, while satisfying stringent constraints on numerical precision, latency, and silicon area. Our results establish a path toward probabilistic inference directly at the edge, opening new opportunities for intelligent sensing in high-rate scientific instruments.

Das, Arghya Ranjan [Purdue U.] (ORCID:000000018451↗
DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗
DOE OSTI2022

Cryogenic electronics for noble liquid neutrino detectors

In this paper we present the general features of cryogenic (or “cold”) electronics for noble liquid time projection chambers, with design principles and details for neutrino physics, a brief history of the technology and details of recent research and development that is driving the design of the detectors under construction. Finally, some comments on future R&D envisioned and the impact of this work on other fields is described. “Cold” in the context of this work applies to CMOS devices operated at 77 K and above, at liquids temperatures of LAr (89 K), LKr (125 K) and LXe (165 K), with most of the tests performed in, or at LN 2 (77 K). Additionally, the paper is concentrated on the design of cold electronics for large liquid argon TPCs, those that have been successfully operated, MicroBooNE and ProtoDUNE, and those designed or under construction, such as SBND and DUNE first and second 10 kton modules. The high performance achieved with MicroBooNE and ProtoDUNE – a high signal-to-noise ratio combined with high stability of response – is mainly due to the integral approach to design and construction of sensing electrodes with cold readout electronics in a modular approach with the cryostat signal feed-throughs incorporating warm interface electronics into a Faraday cage with the cryostat. The integral concept is described in some detail in this paper.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS2009

Economical Implementation of a Filter Engine in an FPGA

A logic design has been conceived for a field-programmable gate array (FPGA) that would implement a complex system of multiple digital state-space filters. The main innovative aspect of this design lies in providing for reuse of parts of the FPGA hardware to perform different parts of the filter computations at different times, in such a manner as to enable the timely performance of all required computations in the face of limitations on available FPGA hardware resources. The implementation of the digital state-space filter involves matrix vector multiplications, which, in the absence of the present innovation, would ordinarily necessitate some multiplexing of vector elements and/or routing of data flows along multiple paths. The design concept calls for implementing vector registers as shift registers to simplify operand access to multipliers and accumulators, obviating both multiplexing and routing of data along multiple paths. Each vector register would be reused for different parts of a calculation. Outputs would always be drawn from the same register, and inputs would always be loaded into the same register. A simple state machine would control each filter. The output of a given filter would be passed to the next filter, accompanied by a "valid" signal, which would start the state machine of the next filter. Multiple filter modules would share a multiplication/accumulation arithmetic unit. The filter computations would be timed by use of a clock having a frequency high enough, relative to the input and output data rate, to provide enough cycles for matrix and vector arithmetic operations. This design concept could prove beneficial in numerous applications in which digital filters are used and/or vectors are multiplied by coefficient matrices. Examples of such applications include general signal processing, filtering of signals in control systems, processing of geophysical measurements, and medical imaging. For these and other applications, it could be advantageous to combine compact FPGA digital filter implementations with other application-specific logic implementations on single integrated-circuit chips. An FPGA could readily be tailored to implement a variety of filters because the filter coefficients would be loaded into memory at startup.

Kowalski, James E.↗
NASA NTRS1985

Progress in knowledge representation research

Brief descriptions are given of research being carried out in the field of knowledge representation. Dynamic simulation and modelling of planning systems with real-time sensor inputs; development of domain-independent knowledge representation tools which can be used in the development of application-specific expert and planning systems; and development of a space-borne very high speed integrated circuit processor are among the projects discussed.

Lum, Henry↗
DOE OSTI2023

ML-ACCEPT: Machine-Learning-enhanced Automated Circuit Configuration and Evaluation of Power Converters

This project, ML-ACCEPT, took a significant step toward achieving the first objective of the DIFFERENTIATE program: to help engineers to more rapidly and cost-effectively consider a wider range of more novel concepts before selecting an engineering-optimal architecture for high-fidelity detailed design and evaluation. Compared to existing methods, the ML-ACCEPT project investigated innovative technologies to make the design of power converters more cost-effective and time-efficient by i) integrating recent breakthroughs in ML, power electronics, simulation software, and optimization to research, develop, and developed a suite of ML-enhanced hypothesis generation tools for power converter design; and ii) facilitating the integration of the proposed software tools into existing power-converter design work-flows. Some existing tools for power-converter design have a certain level of intelligence to aid the design process, but to our knowledge none of them has ML-enhanced capability of automating the electrical circuit design process by selecting, configuring, and tailoring the individual components that enable available resources (e.g., high-voltage DC power) to be converted to the desired output (e.g., lower-voltage DC power with a desired voltage ripple), subject to application-specific (e.g., plasma generation and automotive applications) thermal and packaging considerations. The state-of-the-art circuit design of power converters is still heavily reliant on human experts to select the optimal topology and search for design parameters with human’s experience and intuitions, which can be very time-consuming, inefficient, and labor intensive. The team is composed of University of Michigan-Dearborn (UM-Dearborn), Lawrence Livermore National Laboratory (LLNL), Oak Ridge National Laboratory (ORNL), Modelon Inc., and lighthouse customers.

42 ENGINEERING↗
NASA NTRS2003

Micro-Detection System for Determination of the Biotic or Abiotic Origin of Amino Acids

The research carried out under this PIDDP involves the development of a breadboard version of a spacecraft-based system for the detection of amino acid chirality (molecular handedness) on solar system bodies. Chirality provides an unambiguous way of distinguishing between abiotic and biotic origins since only one mirror-image form is used in the functional molecules of life. Recent advances in a variety of nano-fabrication technologies have resulted in concepts for enabling miniaturized chemical and biological analytical systems. These are complete application-specific systems that integrate fluid micro handling systems for extracting and reacting target molecules, micro-separation technologies for enhanced sensitivity and resolution, and advanced detection technologies. This effort makes use of a relatively new technology that shows demonstrated promise for spacecraft-based amino acid analysis: microchip-based capillary electrophoresis (μCE). The μCE system is capable of analyzing the type of amino acids present as well as the relative amounts of their mirror image forms. The system we developed will be able to chirally resolve all of the major amino acids found in extraterrestrial material (Gly, Ala, Val, Pro, Asp, Glu, a-aminoisobutyric acid, and isovaline) at sub-part-per-billion levels. The -CE analysis requires that the amino acids be extracted from the sample and derivatized for either optical or electrochemical detection. In our implementation, the amino acids are released from the sample by sublimation and prepared for μCE analysis using a microfluidic circuit. In addition, we have investigated the use of a microfluidic circuit for the release of amino acids from samples in which sublimation has proven to be problematic.

Jeffrey L Bada↗