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At least 73 records · Page 4

Neural network methods for radiation detectors and imaging

Recent advances in image data proccesing through deep learning allow for new optimization and performance-enhancement schemes for radiation detectors and imaging hardware. This enables radiation experiments, which includes photon sciences in synchrotron and X-ray free electron lasers as a subclass, through data-endowed artificial intelligence. We give an overview of data generation at photon sources, deep learning-based methods for image processing tasks, and hardware solutions for deep learning acceleration. Most existing deep learning approaches are trained offline, typically using large amounts of computational resources. However, once trained, DNNs can achieve fast inference speeds and can be deployed to edge devices. A new trend is edge computing with less energy consumption (hundreds of watts or less) and real-time analysis potential. While popularly used for edge computing, electronic-based hardware accelerators ranging from general purpose processors such as central processing units (CPUs) to application-specific integrated circuits (ASICs) are constantly reaching performance limits in latency, energy consumption, and other physical constraints. These limits give rise to next-generation analog neuromorhpic hardware platforms, such as optical neural networks (ONNs), for high parallel, low latency, and low energy computing to boost deep learning acceleration (LA-UR-23-32395).

edge computing↗

Towards Automatic and Agile AI/ML Accelerator Design with End-to-End Synthesis

Domain-specific designs offer greater energy efficiency and performance gain than general-purpose processors. For this reason, modern system-on-chips have a significant portion of their silicon area with custom accelerators. However, designing hardware by hand is laborious and time-consuming, given the large design space and the performance, power, and area constraints that are not realized in the software. Moreover, domain-specific algorithms (e.g., machine learning models) are evolving quickly, challenging the accelerator design further. To address these issues, this paper presents SODA Synthesizer, an automated open-source high-level ML framework to Verilog modular compiler targeting AI/ML Application-Specific Integrated Circuits (ASICs) accelerators. SODA tightly couples the Multi- Level Intermediate Representation (MLIR) compiler infrastructure [24] and open-source HLS approaches. Thus, SODA can support various ML frameworks and algorithms and can perform optimizations that combine specialized architecture templates and conventional HLS to generate the hardware modules. In addition, SODA’s closed-loop design space exploration (DSE) engine allows developers to perform end-to-end design space explorations on different metrics and technology nodes.

Zhang, Jeff↗

Peak Prediction Using Multi Layer Perceptron (MLP) for Edge Computing ASICs Targeting Scientific Applications

High data rate detectors play an integral part in scientific research and their development is actively pursued at High Energy Physics (HEP) facilities around the world. Edge Machine Learning (ML) offers the ability to reduce data rates by integrating ML algorithms into Application Specific Integrated Circuits (ASICs) on the front end electronics. In this work, we explore a set of neural network architectures for predicting the peak amplitudes in the detector's sensor response. We have designed and synthesized several MLP based neural networks comparing their inference accuracy, power consumption, and area targeting for minimal latency. The neural networks are synthesized in a commercial 65nm process. The effect of quantizing the network's weights and biases on hardware performance and area is reported. We also conduct design space exploration to compare between design alternatives

47 OTHER INSTRUMENTATION↗

An Open-Source Framework for Rapid Validation of Scientific ASICs

Spacely is an open-source framework for the post-silicon validation of analog, digital, and mixed-signal ASICs (Application-Specific Integrated Circuits) which maximizes the reuse of hardware and software, reducing the time taken to achieve meaningful test results. Spacely specifically addresses the needs of small, flexible ASIC design teams commonly found in academia or research institutions which benefit most from sharing the overhead of test stand creation between many unique ASIC designs. Spacely is a set of software, firmware, and design practices. It targets two primary hardware platforms (NI-PXI and Caribou) as well as offering extensible support for bench instruments. Spacely provides a high-level Python interface to all test hardware for accessibility, while also giving more sophisticated teams the opportunity to integrate custom test firmware. The design principles of Spacely are presented, along with a demonstrative example of using Spacely to test a pixel detector readout ASIC.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Automating Testing of DUNE Electronics via a Finite State Machine

The Deep Underground Neutrino Experiment (DUNE) is a flagship international collaboration designed to study neutrinos—tiny, nearly massless particles that may hold answers to fundamental questions about the Universe. Fermilab’s Robotic Test Stand (RTS) plays a critical role in ensuring the quality of approximately 50,000 Application-Specific Integrated Circuit (ASIC) chips that will be used in DUNE’s massive liquid argon detectors. These electronics will be inside the cryostat; therefore, they will need to have a high yield of working chips and low noise. To improve the automation and reliability of the RTS, this project focused on designing and implementing a Python-based finite state machine (FSM) to manage chip handling workflows. The FSM was developed as a modular software framework to coordinate robotic arm movements, manage chip tray positions, and monitor system states during testing. Key features include robust error handling routines, a pause/resume system for safe mid-cycle interruptions, and a simulation mode for iterative testing without hardware dependencies. The system was designed to prepare for seamless integration with RTS hardware components such as the robotic arm and vision system. This integration will streamline collaboration and enable efficient deployment of updates across the six institutions performing testing. The outcomes of this internship contribute to Fermilab’s mission to advance high-energy physics and support the DOE’s national goals by directly improving the testing of equipment to be used in DUNE. The project also provided valuable experience in software design and contributing to the success of DUNE.

Kang, Caleb [Fermilab]↗

On-chip probabilistic inference for charged-particle tracking at the sensor edge

Modern scientific instruments operate under increasingly extreme constraints on bandwidth, latency, and power. Inference at the sensor edge determines experimental data collection efficiency by deciding which information to save for further analysis. Particle tracking detectors at the Large Hadron Collider exemplify this challenge: pixelated silicon sensors generate rich spatiotemporal ionization patterns, yet most of this information is discarded due to data-rate limitations. Concurrently, advancements in co-design tools provide rapid turn-around for incorporating machine learning into application-specific integrated circuits, motivating designs for particle detectors with new integrated technologies. We demonstrate that neural networks embedded in the front-end electronics can infer charged-particle kinematic parameters from a single silicon layer. We regress hit positions and incident angles with calibrated uncertainties, while satisfying stringent constraints on numerical precision, latency, and silicon area. Our results establish a path toward probabilistic inference directly at the edge, opening new opportunities for intelligent sensing in high-rate scientific instruments.

Das, Arghya Ranjan [Purdue U.] (ORCID:000000018451↗

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.

Alcalde Bessia, Fabricio↗

A Sub-electron-noise Skipper-CCD Readout ASIC with Improved Channel-to-channel Isolation and an Integrated Cryogenic Voltage Reference

The MIDNA application specific integrated circuits (ASICs) are a series of skipper-CCD readout chips fabricated in a 65 nm low-power CMOS process that implement a correlated double sampling signal processing chain based on dual-slope integrators. They are capable of working from room to cryogenic temperatures, down to 84 K. The present iteration of the ASIC has been fabricated including several design updates and the addition of an on-chip voltage reference, resulting in improved performance. This work presents the main vulnerabilities solved, the changes carried out, and the resulting performance benefits. Measurements with a skipper-CCD and the ASIC at 140 K showed that the single-electron resolution can be reached by averaging the measured charge in the analog domain using the analog pile-up technique with a readout noise as low as 0.11 erms of equivalent charge for 1200 samples. The channel-to-channel crosstalk was also characterized showing values better than -62 dB.

Alcalde Bessia, Fabricio↗

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗

Cryogenic electronics for noble liquid neutrino detectors

In this paper we present the general features of cryogenic (or “cold”) electronics for noble liquid time projection chambers, with design principles and details for neutrino physics, a brief history of the technology and details of recent research and development that is driving the design of the detectors under construction. Finally, some comments on future R&D envisioned and the impact of this work on other fields is described. “Cold” in the context of this work applies to CMOS devices operated at 77 K and above, at liquids temperatures of LAr (89 K), LKr (125 K) and LXe (165 K), with most of the tests performed in, or at LN 2 (77 K). Additionally, the paper is concentrated on the design of cold electronics for large liquid argon TPCs, those that have been successfully operated, MicroBooNE and ProtoDUNE, and those designed or under construction, such as SBND and DUNE first and second 10 kton modules. The high performance achieved with MicroBooNE and ProtoDUNE – a high signal-to-noise ratio combined with high stability of response – is mainly due to the integral approach to design and construction of sensing electrodes with cold readout electronics in a modular approach with the cryostat signal feed-throughs incorporating warm interface electronics into a Faraday cage with the cryostat. The integral concept is described in some detail in this paper.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

On-PIC Light Source Integration & Micro-dispensing of Solder Paste for Flip Chip Application

To reach the next level benefits of photonic integrated circuits (PICs), the Integrated Photonic Systems Roadmap-International describes the necessity of either heterogeneous or hybrid integration of light sources [1]. A new approach for hybrid integration is Photonic Wire Bonding where 3D nanolithography is used to pattern a polymer waveguide that connects light sources to PIC waveguides. The waveguides resemble electrical wire bonds and essentially do the same as their electrical counterpart for packaging photonic chips together. In order to reap the full benefits of a photonic wire bonds, the light source must be carefully packaged. In this work I seek to expand RIT’s photonic packaging capability by establishing a packaging process to integrate light sources, specifically an Indium Phosphide distributed feedback lasers and a reflective semiconductor optical amplifiers, directly onto a photonic integrated circuits. Another necessary requirement for PIC packaging is densely integrated electrical connectivity. In this thesis I developed a fine pitch flip chip interconnect technique demonstrated using gold stud bumps in conjunction with micro-dispensed solder paste. This work opens the door to high density photonic flip chip applications. The micro-dispensed solder paste dots having diameters 50-125 µm are currently being tested at a pitch of 150 µm . The gold stud bumps are formed with 1mil gold wire creating bumps with a diameter of 40-60 µm depending on specific parameter values. These capabilities will allow RIT to assemble and test novel photonic integrated devices, cutting down on the time and cost associated with third party assembly and tests facilities. Thereby keeping RIT at the forefront of photonic research.

Wongk, Nicole↗

A Comparative Evaluation and Selection of High-Temperature Heat Exchangers for Application to Integrated Energy Systems

The following report aims to create a refined and well-structured method for comparatively evaluating heat exchanger technologies for integrated energy systems that caters customers’ specific needs while meeting engineering requirements. For the evaluation, this study elevates previous evaluation metrics, enhances the knowledge base via literature and market surveys, and identifies the figures of merit with robust rationales to enhance the quality of decisions made throughout the proposed heat exchanger evaluation process. The heat exchanger designs evaluated as part of the case study are shell and tube heat exchangers, printed circuit heat exchangers, plate heat exchangers, spiral heat exchangers, and heat pipe heat exchangers. The information presented in this report is meant for industries interested in making a preliminary screening process to identify the most suitable heat exchanger design for their application of interest.

42 ENGINEERING↗

A Comparative Evaluation and Selection of High-Temperature Heat Exchangers for Application to Integrated Energy Systems

The following report aims to create a refined and well-structured method for comparatively evaluating heat exchanger technologies for integrated energy systems that caters customers’ specific needs while meeting engineering requirements. For the evaluation, this study elevates previous evaluation metrics, enhances the knowledge base via literature and market surveys, and identifies the figures of merit with robust rationales to enhance the quality of decisions made throughout the proposed heat exchanger evaluation process. The heat exchanger designs evaluated as part of the case study are shell and tube heat exchangers, printed circuit heat exchangers, plate heat exchangers, spiral heat exchangers, and heat pipe heat exchangers. The information presented in this report is meant for industries interested in making a preliminary screening process to identify the most suitable heat exchanger design for their application of interest.

42 - ENGINEERING↗

A feasible path for the use of ferromagnetic josephson junctions in quantum circuits: The ferro-transmon

We discuss the capabilities of ferromagnetic (F) Josephson junctions (JJs) in a variety of layouts and configurations. The main goal is to demonstrate the potential of these hybrid JJs to disclose new physics and the possibility to integrate them in superconducting classical and quantum electronics for various applications. The feasible path towards the use of ferromagnetic Josephson junctions in quantum circuits starts from experiments demonstrating macroscopic quantum tunneling in NbN/GdN/NbN junctions with ferro-insulator barriers and with triplet components of the supercurrent, supported by a self-consistent electrodynamic characterization as a function of the barrier thickness. This has inspired further studies on tunnel ferromagnetic junctions with a different layout and promoted the first generation of ferromagnetic Al-based JJs, specifically Al/AlO x /Al/Py/Al. This layout takes advantage of the capability to integrate the ferromagnetic layer in the junction without affecting the quality of the superconducting electrodes and of the tunnel barrier. The high quality of the devices paves the way for the possible implementation of Al tunnel-ferromagnetic JJs in superconducting quantum circuits. These achievements have promoted the notion of a novel type of qubit incorporating ferromagnetic JJs. This qubit is based on a transmon design featuring a tunnel JJ in parallel with a ferromagnetic JJ inside a SQUID loop capacitively coupled to a superconducting readout resonator. In conclusion, the effect of an external RF field on the magnetic switching processes of ferromagnetic JJs has been also investigated.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Module-Fluidics: Building Blocks for Spatio-Temporal Microenvironment Control

Generating the desired solute concentration signal in micro-environments is vital to many applications ranging from micromixing to analyzing cellular response to a dynamic microenvironment. We propose a new modular design to generate targeted temporally varying concentration signals in microfluidic systems while minimizing perturbations to the flow field. The modularized design, here referred to as module-fluidics, similar in principle to interlocking toy bricks, is constructed from a combination of two building blocks and allows one to achieve versatility and flexibility in dynamically controlling input concentration. The building blocks are an oscillator and an integrator, and their combination enables the creation of controlled and complex concentration signals, with different user-defined time-scales. We show two basic connection patterns, in-series and in-parallel, to test the generation, integration, sampling and superposition of temporally-varying signals. All such signals can be fully characterized by analytic functions, in analogy with electric circuits, and allow one to perform design and optimization before fabrication. Such modularization offers a versatile and promising platform that allows one to create highly customizable time-dependent concentration inputs which can be targeted to the specific application of interest.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

Circuit Modeling, Simulation, and Experimental Validation of a 100-kW Polyphase Wireless Power Transfer System for EV Applications

Polyphase wireless power transfer (WPT) systems can achieve much higher surface power densities (kW/m2) and specific power levels (kW/kg) compared to the conventional circular single phase WPT systems. Therefore, polyphase WPT systems can reduce the size, weight, volume, and cost of the WPT systems and can simplify the electric vehicle integration with less demand for space. This study presents the high-performance and compact 100-kW WPT development using polyphase electromagnetic coupling coils with rotating magnetic fields.

Onar, Omer [ORNL] (ORCID:0000000292028857)↗

Integration of Ultrawide Bandgap Photoconducting Semiconductor Switches into High-Voltage, High-Current Pulser Systems

In this feasibility study we will evaluate the viability of integrating ultrawide bandgap (UWBG) photoconducting semiconductor switches (PCSS) in high-voltage pulser systems capable of driving low-impedance dynamic loads critical for next-generation accelerator and RF-source applications. The project consisted of developing modelling tools that would inform design of UWBG PCSS packages that could be mounted onto conventional circuit boards. Specifically, we are interested in evaluating the following through simulation software: (1) resistance to electrical breakdown (2) proximity effects due to high-frequency skin effect (3) transient behavior from switching (4) effective transmission of RF signals (5) thermal dynamics of the switch under operation (6) sensitivity to inhomogeneities in optical excitation of the material (7) cross-talk effects from parallel switching structures, and (8) susceptibility of system to damaged components. The project resulted in the development of a special-purpose circuit code that implements photoconductivity physics. This code was used to evaluate objectives 1-6 above, identifying a critical requirement associated with the need for fine control of dopant concentrations in the UWBG material to reach an optimal solution for voltage standoff and laser light responsivity requirements. In addition, we identified that the temperature dependence of the electrical conductivity of this material was typically not well-measured and developed a platform for measuring both the “dark” and “illuminated” conductivity on real physical switches in the lab to better inform our models.

24 POWER TRANSMISSION AND DISTRIBUTION↗

Detecting defects that reduce breakdown voltage using machine learning and optical profilometry

Abstract Semiconductor wafer manufacturing relies on the precise control of various performance metrics to ensure the quality and reliability of integrated circuits. In particular, GaN has properties that are advantageous for high voltage and high frequency power devices; however, defects in the substrate growth and manufacturing are preventing vertical devices from performing optimally. This paper explores the application of machine learning techniques utilizing data obtained from optical profilometry as input variables to predict the probability of a wafer meeting performance metrics, specifically the breakdown voltage (V bk ). By incorporating machine learning techniques, it is possible to reliably predict performance metrics that cause devices to fail at low voltage. For diodes that fail at a higher (but still below theoretical) breakdown voltage, alternative inspection methods or a combination of several experimental techniques may be necessary.

42 ENGINEERING↗