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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS1991

The MARCOR GPS mobile data system

Market research revealed several key demands for an Automatic Vehicle Location (AVL) Global Positioning System (GPS) radio. The demands were for minimization of urban building blockage, easy programmability to minimize mobile data transmission costs, high accuracy for street map level coordination, interface capability with non-digital Specialized Mobile Radios (SMR), and a selling price close to that of alternatives such as Signposts and Loran-C. A team of experts was assembled to surmount these challenges and deliver a GPS radio for $500 to $1000, which operates at high accuracy in an urban environment and is plug-compatible with nearly all vehicle radios. Among the engineering and production breakthroughs described here are a unique Simultrac (Trademark) approach to satellite tracking, enabling up to eight GPS satellites to be used for position determination with a 2-channel receiver, and a receiver-in-a-microphone design. A powerful Application Specific Integrated Circuit (ASIC) allowed GPS to be brought within easy reach of millions of AVL users such as bus, taxi, and delivery vehicle fleets.

Rothblatt, Martin↗
NASA NTRS1992

Flexible high speed CODEC (FHSC)

This paper describes the on going NASA/Harris FHSC CODEC program. The program objectives are to design and build an encoder decoder that allows operation in either burst or continuous modes at data rates of up to 300 megabits per second. The decoder handles both hard and soft decision decoding and can switch between modes on a burst by burst basis. Bandspreading is low since the code rate is greater than or equal to 7/8. The encoder and a hard decision decoder fit on a single application specific integrated circuit (ASIC) chip. A soft decision applique is implemented using 300 K ECL logic which can be easily translated to an ECL gate array.

Segallis, G. P.↗
NASA NTRS1991

Imaging pulse-counting detector systems for space ultraviolet astrophysics missions

A family of imaging, pulse-counting, photoelectric detector systems, the Multi-Anode Microchannel Arrays (MAMAs), are now under active development for use on a number of space ultraviolet astrophysics missions at far-ultraviolet (FUV) and extreme-ultraviolet wavelengths between about 300 and 28 nm. Specifically, MAMA detectors are being fabricated and tested for use in two instruments on the ESA/NASA Solar and Heliospheric Observatory mission, for the NASA Goddard Space Flight Center's Hubble Space Telescope Imaging Spectrograph, and for the prime FUV spectrograph of the Far Ultraviolet Spectroscopic Explorer FUSE/Lyman mission. The construction and performance characteristics of the different MAMA detector systems are described, and techniques for improving the spatial resolution of each of the detector systems by the use of custom application specific integrated circuits in the electronics are discussed.

Timothy, J. G.↗
NASA NTRS1991

Next generation functional components for space telemetry data processing

The use of new design methodologies to continue the evolution of telemetry data systems to higher levels of integration is discussed. In particular, hardware description languages and automated logic synthesis tools are used to create very dense Application Specific Integrated Circuits (ASICs) that generically implement telemetry processing functions. The use of the ASICs will make it possible to develop a new generation of functional components, each of the components integrating several telemetry processing subsystems into a single card.

Bennett, Toby↗
NASA NTRS1993

Predicting Lifetimes Of CMOS ASIC's From Test Data

Concise report discusses recent developments in use of semiempirical mathematical models to predict rates of failure and operating lifetimes of complementary metal oxide/semiconductor (CMOS) application-specific integrated circuits (ASIC's). Each model represents specific mechanism of failure. Once failure mechanisms and models relevant to given ASIC chosen, adjustable parameters in models fitted to life-test data acquired from representative integrated-circuit structures on test coupons fabricated along with ASIC's. Then design parameters of ASIC's incorporated into models, and models yield lifetimes.

Buehler, Martin G.↗
NASA NTRS1992

Spacecraft optical disk recorder memory buffer control

The goal of this project is to develop an Application Specific Integrated Circuit (ASIC) for use in the control electronics of the Spacecraft Optical Disk Recorder (SODR). Specifically, this project is to design an extendable memory buffer controller ASIC for rate matching between a system Input/Output port and the SODR's device interface. The aforementioned goal can be partitioned into the following sub-goals: (1) completion of ASIC design and simulation (on-going via ASEE fellowship); (2) ASIC Fabrication (at ASIC manufacturer); and (3) ASIC Testing (NASA/LaRC, Christopher Newport University).

Hodson, Robert F.↗
NASA NTRS1993

Fuzzy efficiency optimization of AC induction motors

This paper describes the early states of work to implement a fuzzy logic controller to optimize the efficiency of AC induction motor/adjustable speed drive (ASD) systems running at less than optimal speed and torque conditions. In this paper, the process by which the membership functions of the controller were tuned is discussed and a controller which operates on frequency as well as voltage is proposed. The membership functions for this dual-variable controller are sketched. Additional topics include an approach for fuzzy logic to motor current control which can be used with vector-controlled drives. Incorporation of a fuzzy controller as an application-specific integrated circuit (ASIC) microchip is planned.

Jani, Yashvant↗
NASA NTRS1991

High resolution decoding of Multi-Anode Microchannel Array detectors

The Multi-Anode Microchannel Array (MAMA) is a photon counting detector which utilizes a photocathode for photon to electron conversion, a microchannel plate (MCP) for signal amplification and a proximity focused anode array for position sensitivity. The detector electronics decode the position of an event through coincidence discrimination. The decoding algorithm which associates a given event with the appropriate pixel is determined by the geometry of the array. A new algorithm incorporated into a CMOS Application Specific Integrated Circuit (ASIC) decoder which improves the pixel spatial resolution is described. The new algorithm does not degrade the detector throughput and does not require any modifications to the detector tube. The standard MAMA detector has a pixel size of 25 x 25 square microns, but with the new decoder circuit the pixel size is reduced to 12.5 x 12.5 square microns. We have built the first set of decode electronics utilizing the new ASIC chips and report here on the first imaging tests of this system.

Kasle, David B.↗
NASA NTRS1993

Preliminary results from the MAMA detectors for the SOHO mission

Multi-Anode Microchannel Array (MAMA) detector systems are being fabricated and tested for use in the Solar Ultraviolet Measurements of Emitted Radiation (SUMER) and the Ultraviolet Coronagraph Spectrometer (UVCS) instruments on the ESA/NASA Solar and Heliospheric Observatory (SOHO) mission. The SOHO MAMA detector systems have formats of 360 x 1024 pixels and pixel dimensions of 25 x 25 sq microns and are optimized for operation at Extreme Ultraviolet (EUV) wavelengths between 40 and 160 nm. In this paper we report on the initial results of measurements of the performance characteristics of the first flight-configuration detector system employing the new custom Application Specific Integrated Circuits (ASICs) which are designed to improve both the dynamic range and the uniformity of response. The performance characteristics of this detector system are compared with those of earlier breadboard systems employing discrete-component electronics circuits.

Slater, David C.↗
NASA NTRS1994

A Motion-Compensating Image-Compression Scheme

Chrominance used (in addition to luminance) in estimating motion. Variable-rate digital coding scheme for compression of color-video-image data designed to deliver pictures of good quality at moderate compressed-data rate of 1 to 2 bits per pixel, or of fair quality at rate less than 1 bit per pixel. Scheme, in principle, implemented by use of commercially available application-specific integrated circuits. Incorporates elements of some prior coding schemes, including motion compensation (MC) and discrete cosine transform (DCT).

Wong, Carol↗
NASA NTRS1994

Estimating Delays In ASIC's

Verification is important aspect of process of designing application-specific integrated circuit (ASIC). Design must not only be functionally accurate, but must also maintain correct timing. IFA, Intelligent Front Annotation program, assists in verifying timing of ASIC early in design process. This program speeds design-and-verification cycle by estimating delays before layouts completed. Written in C language.

Burke, Gary↗
NASA NTRS1990

High performance VLSI telemetry data systems

NASA's deployment of major space complexes such as Space Station Freedom (SSF) and the Earth Observing System (EOS) will demand increased functionality and performance from ground based telemetry acquisition systems well above current system capabilities. Adaptation of space telemetry data transport and processing standards such as those specified by the Consultative Committee for Space Data Systems (CCSDS) standards and those required for commercial ground distribution of telemetry data, will drive these functional and performance requirements. In addition, budget limitations will force the requirement for higher modularity, flexibility, and interchangeability at lower cost in new ground telemetry data system elements. At NASA's Goddard Space Flight Center (GSFC), the design and development of generic ground telemetry data system elements, over the last five years, has resulted in significant solutions to these problems. This solution, referred to as the functional components approach includes both hardware and software components ready for end user application. The hardware functional components consist of modern data flow architectures utilizing Application Specific Integrated Circuits (ASIC's) developed specifically to support NASA's telemetry data systems needs and designed to meet a range of data rate requirements up to 300 Mbps. Real-time operating system software components support both embedded local software intelligence, and overall system control, status, processing, and interface requirements. These components, hardware and software, form the superstructure upon which project specific elements are added to complete a telemetry ground data system installation. This paper describes the functional components approach, some specific component examples, and a project example of the evolution from VLSI component, to basic board level functional component, to integrated telemetry data system.

Chesney, J.↗
NASA NTRS1990

Digital control of magnetic bearings in a cryogenic cooler

This paper describes the design of a digital control system for control of magnetic bearings used in a spaceborne cryogenic cooler. The cooler was developed by Philips Laboratories for the NASA Goddard Space Flight Center. Six magnetic bearing assemblies are used to levitate the piston, displacer, and counter-balance of the cooler. The piston and displacer are driven by linear motors in accordance with Stirling cycle thermodynamic principles to produce the desired cooling effect. The counter-balance is driven by a third linear motor to cancel motion induced forces that would otherwise be transmitted to the spacecraft. An analog control system is currently used for bearing control. The purpose of this project is to investigate the possibilities for improved performance using digital control. Areas for potential improvement include transient and steady state control characteristics, robustness, reliability, adaptability, alternate control modes, size, weight, and cost. The present control system is targeted for the Intel 80196 microcontroller family. The eventual introduction of application specific integrated circuit (ASIC) technology to this problem may produce a unique and elegant solution both here and in related industrial problems.

Feeley, J.↗
NASA NTRS1993

Telemetry ground system development via the component approach

NASA's deployment of major space projects such as the Earth Observing System (EOS) will demand increased functionality and ground-based telemetry processing performance well above current capabilities. At the NASA/Goddard Space Flight Center, custom hardware and software components have been developed and combined into a unique architecture to address this problem. The hardware components utilize Application Specific Integrated Circuits (ASIC's) developed specifically to support NASA's telemetry data systems needs and designed to handle data rates up to 300 Mbps. A generalized set of software components, called the Telemetry Processing Control Environment facilitate the rapid construction of control and monitoring functions for the ground-based telemetry processing systems. This combination of hardware and software elements enables rapid construction of flexible, cost-effective telemetry processing systems capable of meeting the performance requirements facing NASA in the coming decade.

Thorn, Karen E.↗
NASA NTRS1993

NASA's spacecraft data system

The NASA Small Explorer Data System (SEDS), a space flight data system developed to support the Small Explorer (SMEX) project, is addressed. The system was flown on the Solar Anomalous Magnetospheric Particle Explorer (SAMPEX) SMEX mission, and with reconfiguration for different requirements will fly on the X-ray Timing Explorer (XTE) and the Tropical Rainfall Measuring Mission (TRMM). SEDS is also foreseen for the Hubble repair mission. Its name was changed to Spacecraft Data System (SDS) in view of expansions. Objectives, SDS hardware, and software are described. Each SDS box contains two computers, data storage memory, uplink (command) reception circuitry, downlink (telemetry) encoding circuitry, Instrument Telemetry Controller (ITC), and spacecraft timing circuitry. The SDS communicates with other subsystems over the MIL-STD-1773 data bus. The SDS software uses a real time Operating System (OS) and the C language. The OS layer, communications and scheduling layer, application task layer, and diagnostic software, are described. Decisions on the use of advanced technologies, such as ASIC's (Application Specific Integrated Circuits) and fiber optics, led to technical improvements, such as lower power and weight, without increasing the risk associated with the data system. The result was a successful SAMPEX development, integration and test, and mission using SEDS, and the upgrading of that system to SDS for TRMM and XTE.

Cudmore, Alan↗
NASA NTRS1993

Spacecraft optical disk recorder memory buffer control

This paper discusses the research completed under the NASA-ASEE summer faculty fellowship program. The project involves development of an Application Specific Integrated Circuit (ASIC) to be used as a Memory Buffer Controller (MBC) in the Spacecraft Optical Disk System (SODR). The SODR system has demanding capacity and data rate specifications requiring specialized electronics to meet processing demands. The system is being designed to support Gigabit transfer rates with Terabit storage capability. The complete SODR system is designed to exceed the capability of all existing mass storage systems today. The ASIC development for SODR consist of developing a 144 pin CMOS device to perform format conversion and data buffering. The final simulations of the MBC were completed during this summer's NASA-ASEE fellowship along with design preparations for fabrication to be performed by an ASIC manufacturer.

Hodson, Robert F.↗
NASA NTRS1994

SODR Memory Control Buffer Control ASIC

The Spacecraft Optical Disk Recorder (SODR) is a state of the art mass storage system for future NASA missions requiring high transmission rates and a large capacity storage system. This report covers the design and development of an SODR memory buffer control applications specific integrated circuit (ASIC). The memory buffer control ASIC has two primary functions: (1) buffering data to prevent loss of data during disk access times, (2) converting data formats from a high performance parallel interface format to a small computer systems interface format. Ten 144 p in, 50 MHz CMOS ASIC's were designed, fabricated and tested to implement the memory buffer control function.

Hodson, Robert F.↗
NASA NTRS1994

Hardware description languages

Hardware description languages are special purpose programming languages. They are primarily used to specify the behavior of digital systems and are rapidly replacing traditional digital system design techniques. This is because they allow the designer to concentrate on how the system should operate rather than on implementation details. Hardware description languages allow a digital system to be described with a wide range of abstraction, and they support top down design techniques. A key feature of any hardware description language environment is its ability to simulate the modeled system. The two most important hardware description languages are Verilog and VHDL. Verilog has been the dominant language for the design of application specific integrated circuits (ASIC's). However, VHDL is rapidly gaining in popularity.

Tucker, Jerry H.↗