Cryogenic Preamplification using a Heterojunction-Bipolar-Transistor Inline with a Silicon Single-Electron-Transistor.
Abstract not provided.
Curry, Matthew Jon↗
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Impact of 12-nm FinFET Technology Variations on TID Effects: A Comparative Study of GF 12LP and 12LP+ at the Transistor Level
Here, this article presents a comparative analysis of total ionizing dose (TID) response in GlobalFoundries’ (GF) 12 low-power (LP) and 12LP+12-nm bulk fin field effect transistor (FinFET) technologies using 10-keV X-rays. Our findings show that 12LP+ n-type transistors demonstrate higher sensitivity to TID degradation of the off-state leakage drain current compared to 12LP. Data indicate that for both 12LP and 12LP+, transistors with higher threshold voltages (VTs) exhibit lower off-state drain-source leakage postirradiation compared to transistors with lower VTs. Data consistently show that transistors with fewer fins per transistor show superior TID tolerance, in both 12LP and 12LP+ technologies. Lower VT transistors in both technologies display similar preirradiation leakage currents. On the other hand, higher VT transistors in 12LP+ show lower preirradiation leakage currents than those in 12LP, highlighting that the front-end-of-line of 12LP+ technology has been modified compared to 12LP. p-type devices in 12LP+ presented negligible degradation. Larger TID sensitivity in 12LP+ might be attributed to the implementation of dual-metal gate work functions, reduced halo doping, deeper source/drain (S/D) doping profiles, and/or 12LP+ having narrower fins compared to 12LP.
Dual-metal gate work functions↗
Increase the threshold voltage of high voltage GaN transistors by low temperature atomic hydrogen treatment
High-electron-mobility transistors (HEMTs) based on AlGaN/GaN epitaxial heterostructures are a promising element base for the fabrication of high voltage electronic devices of the next generation. This is caused by both the high mobility of charge carriers in the transistor channel and the high electric strength of the material, which makes it possible to attain high breakdown voltages. For use in high-power switches, normally off-mode GaN transistors operating under enhancement conditions are required. To fabricate normally off GaN transistors, one most frequently uses a subgate region based on magnesium-doped p-GaN. However, optimization of the p-GaN epitaxial-layer thickness and the doping level makes it possible to attain a threshold voltage of GaN transistors close to V{sub th} = +2 V. In this study, it is shown that the use of low temperature treatment in an atomic hydrogen flow for the p-GaN-based subgate region before the deposition of gate-metallization layers makes it possible to increase the transistor threshold voltage to V{sub th} = +3.5 V. The effects under observation can be caused by the formation of a dipole layer on the p-GaN surface induced by the effect of atomic hydrogen. The heat treatment of hydrogen-treated GaN transistors in a nitrogen environment at a temperature of T = 250°C for 12 h reveals no degradation of the transistor’s electrical parameters, which can be caused by the formation of a thermally stable dipole layer at the metal/p-GaN interface as a result of hydrogenation.
36 MATERIALS SCIENCE↗
High-voltage MIS-gated GaN transistors
Transistors with a high electron mobility based on AlGaN/GaN epitaxial heterostructures are promising component types for creating high-power electronic devices of the next generation. This is due both to a high charge-carrier mobility in the transistor channel and a high electric durability of the material making it possible to achieve high breakdown voltages. For use in power switching devices, normally off GaN transistors operating in the enrichment mode are required. To create normally off GaN transistors, the subgate region on the basis of p-GaN doped with magnesium is more often used. However, optimization of the p-GaN epitaxial-layer thickness and doping level makes it possible to achieve a threshold voltage close to V{sub th} = +2 V for the on-mode of GaN transistors. In this study, it is shown that the use of a subgate MIS (metal–insulator–semiconductor) structure involved in p-GaN transistors results in an increase in the threshold voltage for the on-mode to V{sub th} = +6.8 V, which depends on the subgate-insulator thickness in a wide range. In addition, it is established that the use of the MIS structure results in a decrease in the initial transistor current and the gate current in the on mode, which enables us to decrease the energy losses when controlling powerful GaN transistors.
36 MATERIALS SCIENCE↗
Efficient and Robust p-Type Transistor Based on Ultrawide-Bandgap Semiconductor
The p-type transistor is an indispensable component of semiconductor technology, enabling a complementary operation with n-channel transistors for computation, storage, and communication. Achieving both high robustness and high efficiency is highly desirable but challenging for p-type transistors due to the limited semiconductors with reliable hole transport and their high activation energies. Here, in this study, we achieved a robust yet efficient p-type transistor by heterogeneously integrating an ultrawide-bandgap semiconductor and a high-κ dielectric layer through van der Waals integration. The p-type transistor employs a two-dimensional hole channel on hydrogenated diamond (bandgap 5.6 eV) combined with a high-κ (30.5) SrTiO 3 perovskite membrane. At room temperature, the transistor exhibits stable operation with a high on-current (∼200 mA/mm), low subthreshold swing (70 mV/dec), high hole mobility (566 cm 2 /(V·s) to 572 cm 2 /(V·s)), and high on–off ratio (∼10 9 ). Furthermore, tuning the annealing temperature allows operation in either enhancement or depletion mode. The robust p-type transistor with high efficiency holds great potential for future power electronics, ultraviolet (UV) optoelectronics, and harsh-environment electronic applications.
high-κ membrane↗
Analysing organic transistors based on interface approximation
Temperature-dependent characteristics of organic transistors are analysed thoroughly using interface approximation. In contrast to amorphous silicon transistors, it is characteristic of organic transistors that the accumulation layer is concentrated on the first monolayer, and it is appropriate to consider interface charge rather than band bending. On the basis of this model, observed characteristics of hexamethylenetetrathiafulvalene (HMTTF) and dibenzotetrathiafulvalene (DBTTF) transistors with various surface treatments are analysed, and the trap distribution is extracted. In turn, starting from a simple exponential distribution, we can reproduce the temperature-dependent transistor characteristics as well as the gate voltage dependence of the activation energy, so we can investigate various aspects of organic transistors self-consistently under the interface approximation. Small deviation from such an ideal transistor operation is discussed assuming the presence of an energetically discrete trap level, which leads to a hump in the transfer characteristics. The contact resistance is estimated by measuring the transfer characteristics up to the linear region.
36 MATERIALS SCIENCE↗
Reducing the Barrier Height in Organic Transistors
Abstract Reducing the Schottky barrier height and Fermi level de‐pinning in metal‐organic semiconductor contacts are crucial for enhancing the performance of organic transistors. The reduction of the Schottky barrier height in bottom‐contact top‐gate organic transistors is demonstrated by adding 1 nm thick atomic layer deposited Al 2 O 3 on the source and drain contacts. By using two different donor‐acceptor copolymers, both p‐ and n‐ type transistors are investigated. Temperature‐dependent current–voltage measurements from non‐treated, self‐assembled monolayer treated, and Al 2 O 3 treated Au source‐drain contact field‐effect transistors with varying channel lengths are carried out. The drain current versus drain voltage near zero gate voltage, which may be described by the thermionic emission model at temperatures above 150 K, allows the estimation of the Schottky barrier height ( φ B ). The Al 2 O 3 contact‐treated transistors show more than 40% lower φ B compared with the non‐treated contacts in the p ‐type transistor. Similarly, an isoindigo‐based transistor, with n ‐type transport, shows a reduction in φ B with Al 2 O 3 treated contacts suggesting that such ultrathin oxide layers provide a universal method for reducing the barrier height.
Ghobadi, Arash↗
Nonlinear photoresponse of field effect transistors terahertz detectors at high irradiation intensities
Terahertz power dependence of the photoresponse of field effect transistors, operating at frequencies from 0.1 to 3 THz for incident radiation power density up to 100 kW/cm{sup 2} was studied for Si metal–oxide–semiconductor field-effect transistors and InGaAs high electron mobility transistors. The photoresponse increased linearly with increasing radiation intensity up to the kW/cm{sup 2} range. Nonlinearity followed by saturation of the photoresponse was observed for all investigated field effect transistors for intensities above several kW/cm{sup 2}. The observed photoresponse nonlinearity is explained by nonlinearity and saturation of the transistor channel current. A theoretical model of terahertz field effect transistor photoresponse at high intensity was developed. The model explains quantitative experimental data both in linear and nonlinear regions. Our results show that dynamic range of field effect transistors is very high and can extend over more than six orders of magnitudes of power densities (from ∼0.5 mW/cm{sup 2} to ∼5 kW/cm{sup 2})
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
High-Power, High-Frequency Si-Based (SiGe) Transistors Developed
Future NASA, DOD, and commercial products will require electronic circuits that have greater functionality and versatility but occupy less space and cost less money to build and integrate than current products. System on a Chip (SOAC), a single semiconductor substrate containing circuits that perform many functions or containing an entire system, is widely recognized as the best technology for achieving low-cost, small-sized systems. Thus, a circuit technology is required that can gather, process, store, and transmit data or communications. Since silicon-integrated circuits are already used for data processing and storage and the infrastructure that supports silicon circuit fabrication is very large, it is sensible to develop communication circuits on silicon so that all the system functions can be integrated onto a single wafer. Until recently, silicon integrated circuits did not function well at the frequencies required for wireless or microwave communications, but with the introduction of small amounts of germanium into the silicon to make silicon-germanium (SiGe) transistors, silicon-based communication circuits are possible. Although microwavefrequency SiGe circuits have been demonstrated, there has been difficulty in obtaining the high power from their transistors that is required for the amplifiers of a transmitter, and many researchers have thought that this could not be done. The NASA Glenn Research Center and collaborators at the University of Michigan have developed SiGe transistors and amplifiers with state-of-the-art output power at microwave frequencies from 8 to 20 GHz. These transistors are fabricated using standard silicon processing and may be integrated with CMOS integrated circuits on a single chip. A scanning electron microscope image of a typical SiGe heterojunction bipolar transistor is shown in the preceding photomicrograph. This transistor achieved a record output power of 550 mW and an associated power-added efficiency of 33 percent at 8.4 GHz, as shown. Record performance was also demonstrated at 12.6 and 18 GHz. Developers have combined these state-of-the-art transistors with transmission lines and micromachined passive circuit components, such as inductors and capacitors, to build multistage amplifiers. Currently, a 1-W, 8.4-GHz power amplifier is being built for NASA deep space communication architectures.
Ponchak, George E.↗
Transistor-based particle detection systems and methods
Transistor-based particle detection systems and methods may be configured to detect charged and non-charged particles. Such systems may include a supporting structure contacting a gate of a transistor and separating the gate from a dielectric of the transistor, and the transistor may have a near pull-in bias and a sub-threshold region bias to facilitate particle detection. The transistor may be configured to change current flow through the transistor in response to a change in stiffness of the gate caused by securing of a particle to the gate, and the transistor-based particle detection system may configured to detect the non-charged particle at least from the change in current flow.
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
High voltage switch with cascaded transistor topology
A switching apparatus includes three or more series-connected transistors, and it further includes a balancing network. The balancing network includes a resistor network configured to divide a voltage from a voltage source across the series-connected transistors. The resistor network includes at least two resistive legs connected in parallel. In each resistive leg, two or more resistors are connected in series. The balancing network may further comprise at least one capacitive leg of series-connected capacitors connected across the series-connected transistors, and it may further comprise at least one leg of series-connected avalanche diodes connected across the series-connected transistors for overvoltage protection. In example embodiments, the series-connected transistors are JFETs. In other example embodiments, the series-connected transistors may be HEMTs or GaN transistors.
Gill, Lee↗
Large scale electromechanical transistor with application in mass sensing
Nanomechanical transistor (NMT) has evolved from the single electron transistor, a device that operates by shuttling electrons with a self-excited central conductor. The unfavoured aspects of the NMT are the complexity of the fabrication process and its signal processing unit, which could potentially be overcome by designing much larger devices. This paper reports a new design of large scale electromechanical transistor (LSEMT), still taking advantage of the principle of shuttling electrons. However, because of the large size, nonlinear electrostatic forces induced by the transistor itself are not sufficient to drive the mechanical member into vibration—an external force has to be used. In this paper, a LSEMT device is modelled, and its new application in mass sensing is postulated using two coupled mechanical cantilevers, with one of them being embedded in the transistor. The sensor is capable of detecting added mass using the eigenstate shifts method by reading the change of electrical current from the transistor, which has much higher sensitivity than conventional eigenfrequency shift approach used in classical cantilever based mass sensors. Numerical simulations are conducted to investigate the performance of the mass sensor.
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
High Accuracy Transistor Compact Model Calibrations
Typically, transistors are modeled by the application of calibrated nominal and range models. These models consists of differing parameter values that describe the location and the upper and lower limits of a distribution of some transistor characteristic such as current capacity. Correspondingly, when using this approach, high degrees of accuracy of the transistor models are not expected since the set of models is a surrogate for a statistical description of the devices. The use of these types of models describes expected performances considering the extremes of process or transistor deviations. In contrast, circuits that have very stringent accuracy requirements require modeling techniques with higher accuracy. Since these accurate models have low error in transistor descriptions, these models can be used to describe part to part variations as well as an accurate description of a single circuit instance. Thus, models that meet these stipulations also enable the calculation of quantification of margins with respect to a functional threshold and uncertainties in these margins. Given this need, new model high accuracy calibration techniques for bipolar junction transistors have been developed and are described in this report.
42 ENGINEERING↗
Gyrator employing field effect transistors
A gyrator circuit of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180 deg phase reversal is examined. All active elements are MOS field effect transistors. Each amplifier comprises a differential amplifier configuration with current limiting transistor, followed by an output transistor in cascode configuration, and two load transistors of opposite conductivity type from the other transistors. A voltage divider control circuit comprises a series string of transistors with a central voltage input to provide control, with locations on the amplifiers receiving reference voltages by connection to appropriate points on the divider. The circuit produces excellent response and is well suited for fabrication by integrated circuits.
Hochmair, E. S.↗
Preventing Simultaneous Conduction In Switching Transistors
High voltage spikes and electromagnetic interference suppressed. Power-supply circuit including two switching transistors easily modified to prevent simultaneous conduction by both transistors during switching intervals. Diode connected between collector of each transistor and driving circuit for opposite transistor suppresses driving signal to transistor being turned on until transistor being turned off ceases to carry current.
Mclyman, William T.↗
Evolvable circuit with transistor-level reconfigurability
An evolvable circuit includes a plurality of reconfigurable switches, a plurality of transistors within a region of the circuit, the plurality of transistors having terminals, the plurality of transistors being coupled between a power source terminal and a power sink terminal so as to be capable of admitting power between the power source terminal and the power sink terminal, the plurality of transistors being coupled so that every transistor terminal to transistor terminal coupling within the region of the circuit comprises a reconfigurable switch.
Stoica, Adrian↗
Operation of SOI P-Channel Field Effect Transistors, CHT-PMOS30, under Extreme Temperatures
Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures over the range of -190 C to +225 C in terms of its voltage/current characteristic curves. The test temperatures included +22, -50, -100, -150, -175, -190, +50, +100, +150, +175, +200, and +225 C. Limited thermal cycling testing was also performed on the device. These tests consisted of subjecting the transistor to a total of twelve thermal cycles between -190 C and +225 C. A temperature rate of change of 10 C/min and a soak time at the test temperature of 10 minutes were used throughout this work. Post-cycling measurements were also performed at selected temperatures. In addition, re-start capability at extreme temperatures, i.e. power switched on while the device was soaking for a period of 20 minutes at the test temperatures of -190 C and +225 C, was investigated.
Patterson, Richard↗
TiO{sub 2} nanotube-based field effect transistors and their application as humidity sensors
Highlights: Black-Right-Pointing-Pointer Individual TiO{sub 2} nanotubes fabricated by directly anodizing a Ti foil followed by ultrasonification. Black-Right-Pointing-Pointer Individual TiO{sub 2} nanotubes used to construct field effect transistors. Black-Right-Pointing-Pointer Electrical properties measured from the TiO{sub 2} nanotube-based field effect transistors. Black-Right-Pointing-Pointer Sensitive response of the TiO{sub 2} nanotube-based field effect transistors to water vapor. -- Abstract: TiO{sub 2} nanotubes are the building units of various devices of energy- and environment-related applications and the property studies of individual TiO{sub 2} nanotubes are important to understand and improve the performance of TiO{sub 2} nanotubes-based devices. Here we report the electrical property study of individual TiO{sub 2} nanotubes enabled by the construction of field effect transistors based on individual TiO{sub 2} nanotubes. It is found that individual TiO{sub 2} nanotubes exhibit typical n-type electrical conduction characteristics, with electron mobility of 6.9 Multiplication-Sign 10{sup -3} cm{sup 2}/V s at V{sub ds} = 1 V, and electron concentration of 2.8 Multiplication-Sign 10{sup 17} cm{sup -3}. Moreover, the on-off ratio of the TiO{sub 2} nanotube-based field effect transistors is as high as 10{sup 3}. Humidity sensing test shows the sensitive response of the individual TiO{sub 2} nanotubes to water vapor.
36 MATERIALS SCIENCE↗