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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS2018

Cryogenic Parametric Characterization of Gallium Nitride Switches

This report presents the parametric characterization results of four GaN field-effect transistor (FET) devices from three manufacturers, one of which is a cascode device, and compares those results to a Si power metal-oxide-semiconductor fieldeffect transistor (MOSFET) and a SiC power MOSFET. The devices were first characterized at ambient temperature, then at cryogenic temperatures down to -196 C (LN2 temperature), and finally at ambient temperature again in the event that the device parameters were permanently affected by the cryogenic temperatures. In general, the results indicate that the GaN devices show significant improvement overall at cryogenic temperatures in the parameters characterized, such as onresistance and leakage currents, compared to the Si and SiC devices. The results show that the SiC device tested should not be used at cryogenic temperatures due to the significant increase in on-resistance. The results also show that the GaN and Si parameters characterized were either not affected by the cryogenic temperatures or changed by no more than +/-20 percent post LN2 submersion. The device that exhibited the most parametric change post LN2 submersion was the SiC power MOSFET in its leakage currents.

Gonzalez, Marcelo C.↗
NASA NTRS2004

Step Free Surface Heteroepitaxy of 3C-SiC Layers on Patterned 4H/6H-SiC Mesas and Cantilevers

The off-axis approach to SiC epitaxial growth has not prevented many substrate crystal defects from propagating into SiC epilayers, and does not permit the realization of SiC heteropolytype devices. This paper reviews recent advancements in SiC epitaxial growth that begin to overcome the above shortcomings for arrays of device-sized mesas patterned into on-axis 4H/6HSiC wafers. These on-axis mesa growth techniques have produced 4H/6H-SiC homoepilayers and 3C-SiC heteroepilayers with substantially lower dislocation densities. The results should enable improved homojunction and heterojunction silicon carbide prototype devices.

Neudeck, P. G.↗
NASA NTRS2007

Growth and Characterization of 3C-SiC and 2H-AIN/GaN Films and Devices Produced on Step-Free 4H-SiC Mesa Substrates

While previously published experimental results have shown that the step-free (0 0 0 1) 4H-SiC mesa growth surface uniquely enables radical improvement of 3C-SiC and 2H-AlN/GaN heteroepitaxial film quality (greater than 100-fold reduction in extended defect densities), important aspects of the step-free mesa heterofilm growth processes and resulting electronic device benefits remain to be more fully elucidated. This paper reviews and updates recent ongoing studies of 3C-SiC and 2H-AlN/GaN heteroepilayers grown on top of 4H-SiC mesas. For both 3C-SiC and AlN/GaN films nucleated on 4H-SiC mesas rendered completely free of atomic-scale surface steps, TEM studies reveal that relaxation of heterofilm strain arising from in-plane film/substrate lattice constant mismatch occurs in a remarkably benign manner that avoids formation of threading dislocations in the heteroepilayer. In particular, relaxation appears to occur via nucleation and inward lateral glide of near-interfacial dislocation half-loops from the mesa sidewalls. Preliminary studies of homojunction diodes implemented in 3C-SiC and AlN/GaN heterolayers demonstrate improved electrical performance compared with much more defective heterofilms grown on neighbouring stepped 4H-SiC mesas. Recombination-enhanced dislocation motion known to degrade forward-biased 4H-SiC bipolar diodes has been completely absent from our initial studies of 3C-SiC diodes, including diodes implemented on defective 3C-SiC heterolayers grown on stepped 4H-SiC mesas.

Neudeck, P. G.↗
NASA NTRS1999

Electrical Impact of SiC Structural Crystal Defects on High Electric Field Devices (Invited)

As illustrated by the invited paper at this conference and other works, SiC wafers and epilayers contain a variety of crystallographic imperfections, including micropipes, closed-core screw dislocations, grain boundaries, basal plane dislocations, heteropolytypic inclusions, and surfaces that are often damaged and contain atomically rough features like step bunching and growth pits or hillocks. Present understanding of the operational impact of various crystal imperfections on SiC electrical devices is reviewed, with an emphasis placed on high-field SiC power devices and circuits.

Neudeck, Philip G.↗
NASA NTRS1993

Chemical Vapor Deposition Of Silicon Carbide

Large single-crystal SiC boules from which wafers of large area cut now being produced commerically. Availability of wafers opens door for development of SiC semiconductor devices. Recently developed chemical vapor deposition (CVD) process produces thin single-crystal SiC films on SiC wafers. Essential step in sequence of steps used to fabricate semiconductor devices. Further development required for specific devices. Some potential high-temperature applications include sensors and control electronics for advanced turbine engines and automobile engines, power electronics for electromechanical actuators for advanced aircraft and for space power systems, and equipment used in drilling of deep wells. High-frequency applications include communication systems, high-speed computers, and microwave power transistors. High-radiation applications include sensors and controls for nuclear reactors.

Powell, J. Anthony↗
NASA NTRS2016

Long-Term Reliability of a Hard-Switched Boost Power Processing Unit Utilizing SiC Power MOSFETs

Silicon carbide (SiC) power devices have demonstrated many performance advantages over their silicon (Si) counterparts. As the inherent material limitations of Si devices are being swiftly realized, wide-band-gap (WBG) materials such as SiC have become increasingly attractive for high power applications. In particular, SiC power metal oxide semiconductor field effect transistors' (MOSFETs) high breakdown field tolerance, superior thermal conductivity and low-resistivity drift regions make these devices an excellent candidate for power dense, low loss, high frequency switching applications in extreme environment conditions. In this paper, a novel power processing unit (PPU) architecture is proposed utilizing commercially available 4H-SiC power MOSFETs from CREE Inc. A multiphase straight boost converter topology is implemented to supply up to 10 kilowatts full-scale. High Temperature Gate Bias (HTGB) and High Temperature Reverse Bias (HTRB) characterization is performed to evaluate the long-term reliability of both the gate oxide and the body diode of the SiC components. Finally, susceptibility of the CREE SiC MOSFETs to damaging effects from heavy-ion radiation representative of the on-orbit galactic cosmic ray environment are explored. The results provide the baseline performance metrics of operation as well as demonstrate the feasibility of a hard-switched PPU in harsh environments.

Ikpe, Stanley A.↗
NASA NTRS2001

Silicon Carbide Electronic Devices

The status of emerging silicon carbide (SiC) widebandgap semiconductor electronics technology is briefly surveyed. SiC-based electronic devices and circuits are being developed for use in high-temperature, high-power, and/or high-radiation conditions under which conventional semiconductors cannot function. Projected performance benefits of SiC electronics are briefly illustrated for several applications. However, most of these operational benefits of SiC have yet to be realized in actual systems, primarily owing to the fact that the growth techniques of SiC crystals are relatively immature and device fabrication technologies are not yet sufficiently developed to the degree required for widespread, reliable commercial use. Key crystal growth and device fabrication issues that limit the performance and capability of high-temperature and/or high-power SiC electronics are identified. The electrical and material quality differences between emerging SiC and mature silicon electronics technology are highlighted.

Neudeck, P. G.↗
NASA NTRS2004

Reproducible Growth of High-Quality Cubic-SiC Layers

Semiconductor electronic devices and circuits based on silicon carbide (SiC) are being developed for use in high-temperature, high-power, and/or high-radiation conditions under which devices made from conventional semiconductors cannot adequately perform. The ability of SiC-based devices to function under such extreme conditions is expected to enable significant improvements in a variety of applications and systems. These include greatly improved high-voltage switching for saving energy in public electric power distribution and electric motor drives; more powerful microwave electronic circuits for radar and communications; and sensors and controls for cleaner-burning, more fuel-efficient jet aircraft and automobile engines.

Neudeck, Philip G.↗
NASA NTRS1998

SiC Technology

Silicon carbide (SiC)-based semiconductor electronic devices and circuits are presently being developed for use in high-temperature, high-power, and/or high-radiation conditions under which conventional semiconductors cannot adequately perform. Silicon carbide's ability to function under such extreme conditions is expected to enable significant improvements to a far-ranging variety of applications and systems. These range from greatly improved high-voltage switching [1- 4] for energy savings in public electric power distribution and electric motor drives to more powerful microwave electronics for radar and communications [5-7] to sensors and controls for cleaner-burning more fuel-efficient jet aircraft and automobile engines. In the particular area of power devices, theoretical appraisals have indicated that SiC power MOSFET's and diode rectifiers would operate over higher voltage and temperature ranges, have superior switching characteristics, and yet have die sizes nearly 20 times smaller than correspondingly rated silicon-based devices [8]. However, these tremendous theoretical advantages have yet to be realized in experimental SiC devices, primarily due to the fact that SiC's relatively immature crystal growth and device fabrication technologies are not yet sufficiently developed to the degree required for reliable incorporation into most electronic systems [9]. This chapter briefly surveys the SiC semiconductor electronics technology. In particular, the differences (both good and bad) between SiC electronics technology and well-known silicon VLSI technology are highlighted. Projected performance benefits of SiC electronics are highlighted for several large-scale applications. Key crystal growth and device-fabrication issues that presently limit the performance and capability of high temperature and/or high power SiC electronics are identified.

Neudeck, Philip G.↗
NASA NTRS1991

Material properties and device evaluations of ECR-deposited a-Si:H and a-SiC:H films

Device-quality a-Si:H and a-SiC:H films have been deposited using electron cyclotron resonance (ECR) microwave plasmas of SiH4, CH4, and H2 mixtures. Typical material properties of ECR-deposited, photosensitive a-Si:H films are: (1) high photosensitivity up to 2 x 106 with a photoconductivity of 10 exp -5 to 10 exp -4/(Ohm-cm), (2) a Tauc gap of 1.75 to 1.85 eV, (3) an Urbach slope of 50-60 meV determined by the constant photocurrent method, and (4) an integrated defect density of 1-2 x 10 exp 16/cu cm determined by junction capacitance measurements. Highly conductive, p-type a-SiC:H films have been produced by ECR plasmas with a conductivity of 0.2/(Ohm-cm).

Shing, Y. H.↗
NASA NTRS2004

Quantification Of 4H- To 3C-Polymorphism In Silicon Carbide (SiC) Epilayers And An Investigation Of Recombination-Enhanced Dislocation Motion In SiC By Optical Emission Microscopy (Oem) Techniques

Environments that impose operational constraints on conventional silicon-(Si) based semiconductor devices frequently appear in military- and space-grade applications. These constraints include high temperature, high power, and high radiation environments. Silicon carbide (SiC), an alternative type of semiconductor material, has received abundant research attention in the past few years, owing to its radiation-hardened properties as well as its capability to withstand high temperatures and power levels. However, the growth and manufacture of SiC devices is still comparatively immature, and there are severe limitations in present crystal growth and device fabrication processes. Among these limitations is a variety of crystal imperfections known as defects. These imperfections can be point defects (e.g., vacancies and interstitials), line defects (e.g., edge and screw dislocations), or planar defects (e.g., stacking faults and double-positioning boundaries). All of these defects have been experimentally shown to be detrimental to the performance of electron devices made from SiC. As such, it is imperative that these defects are significantly reduced in order for SiC devices to become a viable entity in the electronics world. The NASA Glenn High Temperature Integrated Electronics & Sensors Team (HTIES) is working to identify and eliminate these defects in SiC by implementing improved epitaxial crystal growth procedures. HTIES takes two-inch SiC wafers and etches patterns, producing thousands of mesas into each wafer. Crystal growth is then carried out on top of these mesas in an effort to produce films of improved quality-resulting in electron devices that demonstrate superior performance-as well as fabrication processes that are cost-effective, reliable, and reproducible. In this work, further steps are taken to automate HTIES' SiC wafer inspection system. National Instruments LabVIEW image processing and pattern recognition routines are developed that are capable of quantifying and mapping defects on both the substrate and mesa surfaces, and of quantifying polymorphic changes in the grown materials. In addition, an optical emission microscopy (OEM) system is developed that will facilitate comprehensive study of recombination-enhanced dislocation motion (REDM).

Speer, Kevin M.↗
NASA NTRS2010

Development of SiC Large Tapered Crystal Growth

Majority of very large potential benefits of wide band gap semiconductor power electronics have NOT been realized due in large part to high cost and high defect density of commercial wafers. Despite 20 years of development, present SiC wafer growth approach is yet to deliver majority of SiC's inherent performance and cost benefits to power systems. Commercial SiC power devices are significantly de-rated in order to function reliably due to the adverse effects of SiC crystal dislocation defects (thousands per sq cm) in the SiC wafer.

Neudeck, Phil↗
NASA NTRS2017

Silicon Carbide Power Devices and Integrated Circuits

An overview of the NASA NEPP Program Silicon Carbide Power Device subtask is given, including the current task roadmap, partnerships, and future plans. Included are the Agency-wide efforts to promote development of single-event effect hardened SiC power devices for space applications.

single-event gate rupture (SEGR)↗
NASA NTRS1996

Dopant Incorporation Efficiency in CVD Silicon Carbide Epilayers

In order to ensure reproducible and reliable SiC semiconductor device characteristics, controlled dopant incorporation must be accomplished. Some of the many factors which greatly influence dopant incorporation are the site-competition effect, SiC(0001) substrate polarity, substrate temperature, and the dopant-source reactor concentration. In this paper, dopant incorporation is considered and compared for various dopants in the context of dopant incorporation efficiency. By using secondary ion mass spectrometry (SIMS), the relative dopant incorporation efficiencies were calculated by dividing the SIMS determined dopant concentration in the resulting epitaxial layer by the intentional gas phase dopant concentration used during the SiC CVD. Specifically, the relative magnitudes of dopant incorporation efficiencies for nitrogen, phosphorus, and boron in 6H-SiC (0001) Si-face epitaxial layers are compared as a function of the site-competition effect and the dopant-source reactor concentrations. This serves as a first approximation for comparison of the relative 'doping potencies' of some common dopants used in SiC CVD epitaxial growth.

Larkin, D. J.↗
NASA NTRS2017

Pt: Ti Diffusion Barrier, Interconnect, and Simultaneous Ohmic Contacts to n- and p-type 4H-SiC

We report the initial results of using co-sputtered Pt:Ti 80:20 at. % composition ratio metallization as a diffusion barrier against gold (Au) and oxygen (O), as an interconnect layer, as well as forming simultaneous ohmic contacts to n-and p-type 4H-SiC. Having a single conductor with such combined multi-functional attributes would appreciably reduce the fabrication costs, processing time and complexity that are inherent in the production of SiC based devices. Auger Electron Spectroscopy, Focused Ion Beam-assisted Field Emission Scanning Electron Microscopy and Energy Dispersive Spectroscopy analyses revealed no Au and O migration to the SiC contact surface and minimal diffusion through the Pt:Ti barrier layer after 15 minutes of exposure at 800 °C in atmosphere, thus offering potential long term stability of the ohmic contacts. Specific contact resistance values of 7 x 10(exp -5) and 7.4 x 10(exp -4) Ω-sq.cm were obtained on the n (N(sub d)=7 x 10(exp 18) per cu.cm and p (N(sub a)=2 x 10(exp 20) per cu. cm) -type 4H-SiC, respectively. The resistivity of 75 μΩ-cm was obtained for the Pt:Ti layer that was sandwiched between two SiO2 layers and annealed in pure O ambient up to 900 °C, which offers promise as a high temperature interconnect metallization.

Simultaneous Ohmic Contact↗
NASA NTRS1988

Microwave and millimeter-wave power generation in silicon carbide avalanche devices

Numerical simulations were performed to investigate the typical power-generating capabilities of SiC IMPATT diodes. Using available material parameters, SiC double-drift IMPATT diodes were simulated at 10, 35, 60, and 94 GHz, and the operating characteristics of these devices were compared to those of Si and GaAs devices. Compared to the Si and GaAs IMPATT performances in the pulsed mode, the SiC IMPATT performance was found to be far superior. The performance of SiC devices in the CW mode was also superior to that of GaAs devices, especially at lower frequencies. At a high frequency (94 GHz), the performance of the SiC device was found to be comparable to that of Si devices.

Mehdi, I.↗
NASA NTRS2004

Web Growth Used to Confine Screw Dislocations to Predetermined Lateral Positions in 4H-SiC Epilayers

Silicon-carbide- (SiC-) based power devices could enable substantial aerospace electronics benefits over today's silicon-based electronics. However, present-day SiC wafers contain electrically harmful dislocations (including micropipes) that are unpredictably distributed in high densities across all commercial 4H- and 6H-SiC wafers. The NASA Glenn Research Center recently demonstrated a crystal growth process that moves SiC wafer dislocations to predetermined lateral positions in epitaxial layers so that they can be reproducibly avoided during subsequent SiC electronic device fabrication. The process starts by reactive ion etching mesa patterns with enclosed trench regions into commercial on-axis (0001) 4H- or 6H-SiC substrates. An example of a pregrowth mesa geometry with six enclosed triangular-shaped trench regions is shown. After the etch mask is stripped, homoepitaxial growth is carried out in pure stepflow conditions that enable thin cantilevers to grow laterally from the tops of mesas whose pregrowth top surfaces are not threaded by substrate screw dislocations. The image in the bottom figure shows the postgrowth structure that forms after the lateral cantilevers expand to coalesce and completely roof over each of the six triangular trench regions. Atomic force microscope (AFM) measurements of the roof revealed that three elementary screw dislocation growth spirals, each shown in the AFM insets of the bottom image on the previous page, formed in the film roof at three respective points of cantilever film coalescence. The image above shows the structure following an etch in molten potassium hydroxide (KOH) that produced surface etch pits at the dislocation defects. The larger KOH etch pits--S1, S2, and S3--shown in this image correspond to screw dislocations relocated to the final points of cantilever coalescence. The smaller KOH etch pits are consistent with epilayer threading edge dislocations from the pregrowth substrate mesa (P1, P3, and P4) and a final cantilever coalescence point (P2). No defects (i.e., no etch pits) are observed in other cantilevered portions of the film surface. On the basis of the principle of dislocation Burgers vector conservation, we hypothesize that all vertically propagating substrate dislocations in an enclosed trench region become combined into a single dislocation in the webbed film roof at the point of final roof coalescence. The point of final roof coalescence, and therefore the lateral location of a webbed roof dislocation, can be designed into the pregrowth mesa pattern. Screw dislocations with predetermined lateral positions can then be used to provide the new growth steps necessary for growing a 4H/6H-SiC epilayer with a lower dislocation density than the substrate. Devices fabricated on top of such films can be positioned to avoid the preplaced dislocations.

Powell, J. Anthony↗