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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Predicting failure parameters of semiconductor devices subjected to stress conditions

A method for predicting failure parameters of semiconductor devices can include receiving a set of data that includes (i) characteristics of a sample semiconductor device, and (ii) parameters characterizing a stress condition. The method further includes extracting a plurality of feature values from the set of data and inputting the plurality of feature values into a trained model executing on the one or more processors, wherein the trained model is configured according to an artificial intelligence (AI) algorithm based on a previous plurality of feature values, and wherein the trained model is operable to output a failure prediction based on the plurality of feature values. Further, the method includes generating, via the trained model, a predicted failure parameter of the sample semiconductor device due to the stress condition.

Ahmed, Moinuddin↗
DOE OSTI2019

Electrothermal Modeling and Analysis of Gallium Oxide Power Switching Devices: Preprint

Gallium oxide is an emerging wide band-gap material that has the potential to penetrate the power electronics market in the near future. In this paper, a finite-element gallium oxide semiconductor model is presented that can predict the electrical and thermal characteristics of the device. The finite element model of the two-dimensional device architecture is developed inside the Sentaurus environment. A vertical FinFET device architecture is employed to assess the device's behavior and its static and dynamic behavior. Enhancement-mode device operation is realized with this type of device architecture without the need for any selective area doping. The dynamic thermal behavior of the device is characterized through its short-circuit behavior. Based on the device static and dynamic behavior, it is envisioned that reliable vertical transistors can be fabricated for the power electronics applications.

33 ADVANCED PROPULSION SYSTEMS↗
NASA NTRS1991

Optimization of transistor design including large signal device/circuit interactions at extremely high frequencies (20-100+GHz)

Transistor design for extremely high frequency applications requires consideration of the interaction between the device and the circuit to which it is connected. Traditional analytical transistor models are to approximate at some of these frequencies and may not account for variations of dopants and semiconductor materials (especially some of the newer materials) within the device. Physically based models of device performance are required. These are based on coupled systems of partial differential equations and typically require 20 minutes of Cray computer time for a single AC operating point. A technique is presented to extract parameters from a few partial differential equation solutions for the device to create a nonlinear equivalent circuit model which runs in approximately 1 second of personal computer time. This nonlinear equivalent circuit model accurately replicates the contact current properties of the device as computed by the partial differential solver on which it is based. Using the nonlinear equivalent circuit model of the device, optimization of systems design can be performed based on device/circuit interactions.

Levy, Ralph↗
DOE OSTI2025

Real-Time Lifetime Prediction of Semiconductor Devices Using Hardware-in-the-Loop

This paper presents a unique approach to enable real-time lifespan prediction of semiconductor power modules using a Hardware-in-the-Loop (HIL) system. By integrating the module's overall loss characteristics-specifically switching and conduction losses-with a thermoelectric model of the thermal management system, this research demonstrates that the model can dynamically estimates the junction temperature profile of the semiconductor devices in response to a changing torque demand profile for the motor drive system. This capability enables continuous monitoring of the module's operational time and cumulative stress induced on the devices to compute accumulated remaining lifetime or time-to-failure (TTF). This study provides an architectural framework for the HIL system with high-fidelity component models of multiple physical domains, allowing simulation of dynamic behaviors of a closely-coupled motor drive system. The advanced real-time computation and measurement functionalities of the HIL system allow for both dynamic lifetime calculations based on simulated data and aggregate lifetime predictions utilizing historical data. Moreover, this paper details an algorithm that not only computes cumulative damage but also synthesizes these data into a comprehensive aggregated lifetime metric. This methodology can enhance the maintenance scheduling strategies and operational reliability of semiconductor devices in critical applications, ultimately extending their service life while optimizing performance.

hardware-in-the-loop (HIL)↗
NASA NTRS1983

Semiconductor photoelectrochemistry

Semiconductor photoelectrochemical reactions are investigated. A model of the charge transport processes in the semiconductor, based on semiconductor device theory, is presented. It incorporates the nonlinear processes characterizing the diffusion and reaction of charge carriers in the semiconductor. The model is used to study conditions limiting useful energy conversion, specifically the saturation of current flow due to high light intensity. Numerical results describing charge distributions in the semiconductor and its effects on the electrolyte are obtained. Experimental results include: an estimate rate at which a semiconductor photoelectrode is capable of converting electromagnetic energy into chemical energy; the effect of cell temperature on the efficiency; a method for determining the point of zero zeta potential for macroscopic semiconductor samples; a technique using platinized titanium dioxide powders and ultraviolet radiation to produce chlorine, bromine, and iodine from solutions containing their respective ions; the photoelectrochemical properties of a class of layered compounds called transition metal thiophosphates; and a technique used to produce high conversion efficiency from laser radiation to chemical energy.

Buoncristiani, A. M.↗
DOE OSTI2024

How Accurate Are Simulations and Experiments for the Lattice Energies of Molecular Crystals?

Molecular crystals play a central role in a wide range of scientific fields, including pharmaceuticals and organic semiconductor devices. However, they are challenging systems to model accurately with computational approaches because of a delicate interplay of intermolecular interactions such as hydrogen bonding and Van der Waals dispersion forces. Here, by exploiting recent algorithmic developments, we report the first set of diffusion Monte Carlo lattice energies for all 23 molecular crystals in the popular and widely used X23 dataset. Comparisons with previous state-of-the-art lattice energy predictions (on a subset of the dataset) and a careful analysis of experimental sublimation enthalpies reveals that high-accuracy computational methods are now at least as reliable as (computationally derived) experiments for the lattice energies of molecular crystals. Overall, this work demonstrates the feasibility of high-level explicitly correlated electronic structure methods for broad benchmarking studies in complex condensed phase systems, and signposts a route towards closer agreement between experiment and simulation. Published by the American Physical Society 2024

Physics↗
NASA NTRS1995

On-wafer, cryogenic characterization of ultra-low noise HEMT devices

Significant advances in the development of high electron-mobility field-effect transistors (HEMT's) have resulted in cryogenic, low-noise amplifiers (LNA's) whose noise temperatures are within an order of magnitude of the quantum noise limit (hf/k). Further advances in HEMT technology at cryogenic temperatures may eventually lead to the replacement of maser and superconducting insulator superconducting front ends in the 1- to 100-GHz frequency band. Key to identification of the best HEMT's and optimization of cryogenic LNA's are accurate and repeatable device measurements at cryogenic temperatures. This article describes the design and operation of a cryogenic coplanar waveguide probe system for the characterization and modeling of advanced semiconductor transistors at cryogenic temperatures. Results on advanced HEMT devices are presented to illustrate the utility of the measurement system.

Bautista, J. J.↗
DOE OSTI2023

Predicting electronic structures at any length scale with machine learning

The properties of electrons in matter are of fundamental importance. They give rise to virtually all material properties and determine the physics at play in objects ranging from semiconductor devices to the interior of giant gas planets. Modeling and simulation of such diverse applications rely primarily on density functional theory (DFT), which has become the principal method for predicting the electronic structure of matter. While DFT calculations have proven to be very useful, their computational scaling limits them to small systems. We have developed a machine learning framework for predicting the electronic structure on any length scale. It shows up to three orders of magnitude speedup on systems where DFT is tractable and, more importantly, enables predictions on scales where DFT calculations are infeasible. Our work demonstrates how machine learning circumvents a long-standing computational bottleneck and advances materials science to frontiers intractable with any current solutions.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Charon User Manual (V.2.1) (Rev.01)

This manual gives usage information for the Charon semiconductor device simulator. Charon was developed to meet the modeling needs of Sandia National Laboratories and to improve on the capabilities of the commercial TCAD simulators; in particular, the additional capabilities are running very large simulations on parallel computers and modeling displacement damage and other radiation effects in significant detail. The parallel capabilities are based around the MPI interface which allows the code to be ported to a large number of parallel systems, including linux clusters and proprietary "big iron" systems found at the national laboratories and in large industrial settings.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2022

Charon User Manual: v. 2.2 (revision1)

This manual gives usage information for the Charon semiconductor device simulator. Charon was developed to meet the modeling needs of Sandia National Laboratories and to improve on the capabilities of the commercial TCAD simulators; in particular, the additional capabilities are running very large simulations on parallel computers and modeling displacement damage and other radiation effects in significant detail. The parallel capabilities are based around the MPI interface which allows the code to be ported to a large number of parallel systems, including linux clusters and proprietary “big iron” systems found at the national laboratories and in large industrial settings.

42 ENGINEERING↗
DOE OSTI2025

Trap-assisted Auger-Meitner recombination in GaN p-i-n diodes

Most properties of semiconductor devices are dominated by shallow impurities. However, deep defects often play an important role, for instance, in recombination processes or high field transport. While a variety of techniques are available to assess the density and energy levels of impurities, other properties, such as the recombination mechanisms of the defects, escape observation. We report on the direct measurement of hot electrons generated by trap-assisted Auger-Meitner recombination (TAAR) in GaN p-i-n diodes. By performing electron emission spectroscopy (EES) on diodes with surfaces activated to negative electron affinity by cesium, we observe the expected overflow electrons of p-i-n diodes under low current injection. However, when operating the devices at higher current densities, as low as ∼25 A/c⁢m 2 , we measure the emission of high-energy electrons. At variance with the observed hot electrons in light-emitting diodes (LEDs) using EES, the hot electrons generated in p-i-n diodes at our tested currents cannot be from eeh Auger-Meitner recombination due to the diodes' significantly lower carrier densities compared to those in LEDs. During our measurements, we observe the emission of accumulated electrons with energies ∼0.42 eV, ∼0.99 eV, ∼1.43 eV, and ∼2.32 eV above the conduction-band minimum (CBM) at various bias conditions, suggesting the existence of conduction-band features in GaN at these energies where electrons can be long-lived, such as satellite-valley minima and inflection points. We also measure incompletely relaxed hot electrons approaching energies 1.97 ± 0.13 eV and 2.94 ± 0.13 eV above the CBM, as the diodes are biased to high currents, suggesting at least some of the TAAR partaking defects have an energy level ≳1.97 eV and ≳2.94 eV away from either the conduction or valence band edges. Additionally, at our highest operating currents, we measure hot electrons with energies 3.28 ± 0.13 eV above the CBM, providing direct evidence of TAAR processes involving shallow impurities. This unexpected observation of TAAR in GaN p-i-n diodes spotlights the importance of further studies of defects in GaN and the necessity to incorporate the multi-phonon emission, radiative, and TAAR capture steps of defect-assisted recombination cycles into device modeling. Furthermore, this experiment demonstrates the applicability of the simplest semiconductor structures, p-i-n diodes, as a test bed to study the rich recombination physics of semiconductor materials.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
NASA NTRS2004

Single Event Effects in Highly Scaled Devices for Space Applications

This paper discusses single-event upset (SEU) in memories and microprocessors that are the "drivers" of highly scaled commercial integrated circuits. Despite the decrease in critical charge that occurs for highly scaled CMOS devices, recent test data has shown that SEU rates are actually somewhat lower for scaled devices compared to older devices with larger feature size. Hard errors, which are increasingly important for memories, are discussed along with conventional soft errors. Functional errors in memories and microprocessors are particularly significant, and tend to dominate the response of highly scaled devices from an application standpoint. Predictions for future devices are made using the Semiconductor Industry Roadmap along with recent modeling and radiation test results.

microelectronics↗
DOE OSTI2024

Evaluation of Converter Performance Considering Static and Dynamic Device Part-to-Part Variability

This paper presents a methodology to incorporate and analyze the impact of semiconductor device part-to-part variation on power converter performance. By integrating extensive static and dynamic device characterization data with an automated compact model generation process that reflects manufacturing variability, device models with inherent variability features are utilized in converter simulations for a comprehensive assessment of performance impacts. The traditional converter performance evaluation process typically yields fixed efficiency values, often dismissing the inherent part-to-part variability caused by the manufacturing process of semiconductor devices. To address this limitation, a large population of devices was characterized to capture variations in static parameters-such as transfer, output, and capacitance characteristics-as well as dynamic behaviors, including switching losses. This data-driven approach enables the development of individual compact models, which were then integrated into converter simulations to evaluate efficiency ranges rather than single point estimated values. The converter simulation results show that part-to-part component variation can lead to significant efficiency deviations, exceeding several percentage points in high-power conversion applications. By offering a more accurate representation of converter behavior under real-world manufacturing conditions, this methodology enables designers to anticipate performance variability, improving the robustness of power converter designs.

device characterization↗
DOE OSTI2024

Autonomous hybrid optimization of a SiO 2 plasma etching mechanism

Computational modeling of plasma etching processes at the feature scale relevant to the fabrication of nanometer semiconductor devices is critically dependent on the reaction mechanism representing the physical processes occurring between plasma produced reactant fluxes and the surface, reaction probabilities, yields, rate coefficients, and threshold energies that characterize these processes. The increasing complexity of the structures being fabricated, new materials, and novel gas mixtures increase the complexity of the reaction mechanism used in feature scale models and increase the difficulty in developing the fundamental data required for the mechanism. This challenge is further exacerbated by the fact that acquiring these fundamental data through more complex computational models or experiments is often limited by cost, technical complexity, or inadequate models. In this paper, we discuss a method to automate the selection of fundamental data in a reduced reaction mechanism for feature scale plasma etching of SiO 2 using a fluorocarbon gas mixture by matching predictions of etch profiles to experimental data using a gradient descent (GD)/Nelder–Mead (NM) method hybrid optimization scheme. These methods produce a reaction mechanism that replicates the experimental training data as well as experimental data using related but different etch processes.

36 MATERIALS SCIENCE↗
NASA NTRS1999

Multi-Dimensional Quantum Tunneling and Transport Using the Density-Gradient Model

We show that quantum effects are likely to significantly degrade the performance of MOSFETs (metal oxide semiconductor field effect transistor) as these devices are scaled below 100 nm channel length and 2 nm oxide thickness over the next decade. A general and computationally efficient electronic device model including quantum effects would allow us to monitor and mitigate these effects. Full quantum models are too expensive in multi-dimensions. Using a general but efficient PDE solver called PROPHET, we implemented the density-gradient (DG) quantum correction to the industry-dominant classical drift-diffusion (DD) model. The DG model efficiently includes quantum carrier profile smoothing and tunneling in multi-dimensions and for any electronic device structure. We show that the DG model reduces DD model error from as much as 50% down to a few percent in comparison to thin oxide MOS capacitance measurements. We also show the first DG simulations of gate oxide tunneling and transverse current flow in ultra-scaled MOSFETs. The advantages of rapid model implementation using the PDE solver approach will be demonstrated, as well as the applicability of the DG model to any electronic device structure.

Biegel, Bryan A.↗
NASA NTRS1998

Profile Evolution Simulation in Etching Systems Using Level Set Methods

Semiconductor device profiles are determined by the characteristics of both etching and deposition processes. In particular, a highly anisotropic etch is required to achieve vertical sidewalls. However, etching is comprised of both anisotropic and isotropic components, due to ion and neutral fluxes, respectively. In Ar/Cl2 plasmas, for example, neutral chlorine reacts with the Si surfaces to form silicon chlorides. These compounds are then removed by the impinging ion fluxes. Hence the directionality of the ions (and thus the ion angular distribution function, or IAD), as well as the relative fluxes of neutrals and ions determines the amount of undercutting. One method of modeling device profile evolution is to simulate the moving solid-gas interface between the semiconductor and the plasma as a string of nodes. The velocity of each node is calculated and then the nodes are advanced accordingly. Although this technique appears to be relatively straightforward, extensive looping schemes are required at the profile corners. An alternate method is to use level set theory, which involves embedding the location of the interface in a field variable. The normal speed is calculated at each mesh point, and the field variable is updated. The profile comers are more accurately modeled as the need for looping algorithms is eliminated. The model we have developed is a 2-D Level Set Profile Evolution Simulation (LSPES). The LSPES calculates etch rates of a substrate in low pressure plasmas due to the incident ion and neutral fluxes. For a Si substrate in an Ar/C12 gas mixture, for example, the predictions of the LSPES are identical to those from a string evolution model for high neutral fluxes and two different ion angular distributions.(2) In the figure shown, the relative neutral to ion flux in the bulk plasma is 100 to 1. For a moderately isotropic ion angular distribution function as shown in the cases in the left hand column, both the LSPES (top row) and rude's string method (bottom row) predict tapered profiles. The LSPES uses an AD with a FWHM = 13.5 degrees, and rude's model uses a ratio of sheath voltage to ion temperature of 50. The more anisotropic IADs produce profiles with more vertical sidewalls and a wider bottom surface, as shown in the right hand column. Here, the LSPES has an AD with a FWHM = 2 degrees, and rude's model uses a ratio of 500 of sheath voltage to ion temperature. The agreement between the LSPES and rude's model is excellent in both cases. We will present etching profiles generated by the LSPES, including calculations of the re-emitted fluxes of both neutrals and ions off of the profile walls. In addition, we will show the effect of geometric structures (overhangs, etc.) on the etching profiles. Other physical aspects, such as surface diffusion, will also be included in the model.

Hwang, Helen H.↗
NASA NTRS1995

High Performance Parallel Computational Nanotechnology

At a recent press conference, NASA Administrator Dan Goldin encouraged NASA Ames Research Center to take a lead role in promoting research and development of advanced, high-performance computer technology, including nanotechnology. Manufacturers of leading-edge microprocessors currently perform large-scale simulations in the design and verification of semiconductor devices and microprocessors. Recently, the need for this intensive simulation and modeling analysis has greatly increased, due in part to the ever-increasing complexity of these devices, as well as the lessons of experiences such as the Pentium fiasco. Simulation, modeling, testing, and validation will be even more important for designing molecular computers because of the complex specification of millions of atoms, thousands of assembly steps, as well as the simulation and modeling needed to ensure reliable, robust and efficient fabrication of the molecular devices. The software for this capacity does not exist today, but it can be extrapolated from the software currently used in molecular modeling for other applications: semi-empirical methods, ab initio methods, self-consistent field methods, Hartree-Fock methods, molecular mechanics; and simulation methods for diamondoid structures. In as much as it seems clear that the application of such methods in nanotechnology will require powerful, highly powerful systems, this talk will discuss techniques and issues for performing these types of computations on parallel systems. We will describe system design issues (memory, I/O, mass storage, operating system requirements, special user interface issues, interconnects, bandwidths, and programming languages) involved in parallel methods for scalable classical, semiclassical, quantum, molecular mechanics, and continuum models; molecular nanotechnology computer-aided designs (NanoCAD) techniques; visualization using virtual reality techniques of structural models and assembly sequences; software required to control mini robotic manipulators for positional control; scalable numerical algorithms for reliability, verifications and testability. There appears no fundamental obstacle to simulating molecular compilers and molecular computers on high performance parallel computers, just as the Boeing 777 was simulated on a computer before manufacturing it.

Saini, Subhash↗