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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Multiplicity trigger detector for the S π RIT experiment

A multiplicity trigger detector (MTD) was developed for the SπRIT experiment that aims to probe the high- density symmetry energy via heavy-ion collisions (HICs). The MTD is designed to measure the charged-particle multiplicity in HICs to provide a trigger signal that can be used to select high-multiplicity events induced by central collisions. The MTD consists of two side-walls segmented into 30 plastic scintillation paddles, each equipped with a multi-pixel photon counter. A custom board with EASIROC front-end ASIC is used as readout electronics. A multiplicity logic signal is generated by an on-board FPGA that processes the discriminated signals from EASIROCs. The overall latency of the whole detector system for outputting the trigger is less than 100 ns, including 52 ns of electronics latency for processing the signals. During the measurement of 112 Sn + 124 Sn reactions at an incident energy of 270 MeV/nucleon, the minimum multiplicity threshold of the MTD was set to 4, where the overall trigger efficiency was obtained to be about 39 % for inclusive nuclear reactions. Furthermore, a simulation study with a numerical calculation of HICs found that the central collisions of impact parameters of less than 4 fm can be triggered with a high efficiency of more than 95 % by the experimental trigger condition.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize and retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. GBCR survives the total ionizing dose of 200 kGy.

47 OTHER INSTRUMENTATION↗
DOE OSTI2021

Characterization of the CMS Endcap Timing Layer readout chip prototype with charge injection

We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm CMOS technology, reads out a 16× 16 pixel matrix of the Low-Gain Avalanche Detector (LGAD). The jitter contribution from ETROC is required to be below 40 ps to achieve the 50 ps overall time resolution per hit. The analog readout circuits in ETROC consist of the preamplifier and the discriminator. The preamplifier handles the LGAD charge signal with the most probable value of around 15 fC. The discriminator generates the digital pulse, which provides the Time-Of-Arrival (TOA, leading edge) and Time-Over-Threshold (TOT, pulse width) information. The prototype of ETROC (ETROC0) that implements a single channel of analog readout circuits has been evaluated with charge injection. The jitter of the analog readout circuits, measured from the discriminator's leading edge, is better than 16 ps for a charge larger than 15 fC with the sensor capacitance. The time walk resulting from different pulse heights can be corrected using the TOT measurement. The time resolution distribution has a standard deviation of 29 ps after the time-walk correction from the charge injection. At room temperature, the preamplifier's power consumption is measured to be 0.74 mW and 1.53 mW per pixel in the low- and high-power mode, respectively. Finally, the measured power consumption of the discriminator is 0.84 mW per pixel. With the ASIC alone or the LGAD sensor, The characterization performances fulfill the ETL's challenging requirements.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Test and characterization of finely segmented pixel CZT detectors for future hard x-ray missions

The NuSTAR (Nuclear Spectroscopic Telescope Array) mission was launched in 2012, and it has successfully deployed the first orbiting telescopes to focus high energy X-ray (3 - 79 keV) light, providing a wealth of new information on high-energy X-rays sources. Follow-up missions, such as the proposed HEX-P, BEST, and FORCE, could perform a deeper black hole census providing a more refined measurement of black hole spins, allowing for greater knowledge about supermassive black holes. Here, these missions are motivated by the recent breakthroughs in the hard X-ray mirror technologies, where mirrors, either made of monolithic silicon segments, or made directly or via replication of shells, demonstrate the feasibility of making hard X-ray mirrors with angular resolutions of 5-10 arc-seconds Half Power Diameter (HPD) compared to the NuSTAR’s 1 arc-minute HPD. Such a high angular resolution requires matched detectors with higher degree of segmentation to fully benefit from the achievable improved spatial resolution. In the above framework, the HEXID ASIC, a novel pixelated front-end suitable for reading out a finely segmented CZT sensor with 150 μm pixel pitch in a hexagonal arrangement has been developed. This readout pixelated chip is capable of processing photon-generated charge packets over a large dynamic range (from 2 keV up to 180 keV), while keeping a low input noise (ENC <20 e - ). In this work, the initial characterization of the ASIC prototype will be presented.

47 OTHER INSTRUMENTATION↗
DOE OSTI2024

A Modular 512-Channel Neural Signal Acquisition ASIC for High-Density 4096 Channel Electrophysiology

The complexity of information processing in the brain requires the development of technologies that can provide spatial and temporal resolution by means of dense electrode arrays paired with high-channel-count signal acquisition electronics. In this work, we present an ultra-low noise modular 512-channel neural recording circuit that is scalable to up to 4096 simultaneously recording channels. The neural readout application-specific integrated circuit (ASIC) uses a dense 8.2 mm × 6.8 mm 2D layout to enable high-channel count, creating an ultra-light 350 mg flexible module. The module can be deployed on headstages for small animals like rodents and songbirds, and it can be integrated with a variety of electrode arrays. The chip was fabricated in a TSMC 0.18 µm 1.8 V CMOS technology and dissipates a total of 125 mW. Each DC-coupled channel features a gain and bandwidth programmable analog front-end along with 14 b analog-to-digital conversion at speeds up to 30 kS/s. Additionally, each front-end includes programmable electrode plating and electrode impedance measurement capability. We present both standalone and in vivo measurements results, demonstrating the readout of spikes and field potentials that are modulated by a sensory input.

47 OTHER INSTRUMENTATION↗
DOE OSTI2024

Functional Verification for Endcap Concentrator ASICs in the High-Granularity Calorimeter Upgrade of CMS

The High-Granularity Calorimeter (HGCAL) of CMS will undergo a major upgrade during Long-Shutdown 3. The Endcap Concentrator (ECON) ASICs represent key elements in the readout chain, processing trigger (ECON-T) and data (ECON-D) streams from the HGCROC to the lpGBT. The ECONs will operate in a radiation environment with a High-Energy Hadron (HEH) flux of $3\cdot10^{6} cm^{-2}s^{-1}$. This contribution describes the Universal Verification Methodology (UVM)-based functional verification of the ECON ASICs focusing on the re-use of existing components to manage the complexity of the verification environment.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

SAMPA Based Streaming Readout Data Acquisition Prototype

We have assembled a small-scale streaming data acquisition system based on the SAMPA front-end ASIC. The 32-channel SAMPA chip was designed for the high-luminosity upgrade of the ALICE Time Projection Chamber (TPC) detector at the CERN Large Hadron Collider. The goals of the prototype system are to determine if the SAMPA chip is appropriate for use in detector systems at Jefferson Lab, and to gain experience with the hardware and software required to deploy streaming data acquisition systems in nuclear physics experiments. The 800 channel system is composed of components used in the ALICE TPC data acquisition upgrade. Five front-end cards (FEC) support five SAMPA chips each. SAMPA data streams on an FEC are concentrated into two high-speed (4.48 Gb/s) serial data streams by a pair Gigabit Transceiver ASICs (GBTx). These ten streams (44.8 Gb/s) are transmitted from the FECs over fibers to a PCIe based readout unit. The FPGA engine on the readout unit compresses data for transmission to a server via 100 Gb ethernet. Components on the FECs are radiation tolerant. High data rates can be handled. The system is by design scalable and thus provides a functional prototype for high-rate streaming readout at Jefferson Lab and the future Electron Ion Collider. We have made fundamental measurements (noise, linearity, time resolution) on the SAMPA ASIC. We have also coupled the readout system to a small Gas Electron Multiplier (GEM) detector and have studied its response to cosmic rays. A beam test of the system is planned.

ABBOTT, David↗
DOE OSTI2023

Pulse shape measurements for neutron/gamma discrimination using the TOFPET2 ASIC

Many highly pixelated organic scintillator detection systems would benefit from independent readout of each scintillator pixel. Recent advances in Silicon Photomultiplier (SiPM) technology makes this goal feasible, however the data acquisition from potentially hundreds or thousands of channels requires a low-cost and compact solution. For pixelated neutron detection with organic scintillators, the capability to distinguish between neutron and gamma interactions using Pulse Shape Discrimination (PSD) is required along with pulse charge and time of arrival. The TOFPET2 ASIC from PETsys Electronics is a 64-channel readout chip providing pulse time and charge integration measurements from SiPMs, and is specifically designed for time-of-flight positron-emission tomography. Using an 8 × 8 array of 6 mm × 6 mm J-series SiPMs from SensL/OnSemi (ArrayJ-60035-64P-PCB), we have studied the energy and PSD performance of the TOFPET2 ASIC using a 4 × 4 array of 6 mm × 6 mm × 30 mm trans -Stilbene crystals from Inrad Optics and a custom SiPM routing board from PETsys Electronics. In conclusion, using a time-over-threshold method, we measure a maximum PSD figure-of-merit of approximately 1.2 at 478 keV (the Compton edge of 662 keV) for a J-series SiPM operating at an over-voltage of 3V.

47 OTHER INSTRUMENTATION↗
DOE OSTI2022

Signal formation and sharing in AC-LGADs using the ALTIROC 0 front-end chip

The development of detectors that provide high resolution in four dimensions has attracted wide-spread interest in the scientific community for applications in high-energy physics, nuclear physics, medical imaging, mass spectroscopy as well as quantum information. However, finding a technology capable of fulfilling such aspiration proved to be an arduous task. Among other silicon-based candidates, the Low-Gain Avalanche Diode (LGAD) has already shown excellent timing performances but proved to be unsuitable for fine pixelization. Therefore, the AC-coupled LGAD (AC-LGAD) approach was introduced to provide high resolution in both time and space, making it a promising candidate for future 4D detectors. However, appropriate readout electronics must be developed to match the sensor's fast-time and fine-pitch capabilities. This is currently a major technological challenge. Here, we test AC-LGAD prototypes read out by the fast-time ASIC ALTIROC 0, originally developed for the readout of DC-coupled LGADs for the ATLAS experiment at the High Luminosity-LHC. Signal generated by either betas from a 90 Sr source or a focused infra-red laser were analyzed. This paper details the first successful readout of an AC-LGAD sensor using a readout chip. This result will pave the way for the design and construction of a new generation of AC-LGAD-based 4D detectors.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

The CLAS12 Micromegas Vertex Tracker

The Micromegas Vertex Tracker was designed to improve upon the tracking capabilities of the baseline design of the CLAS12 spectrometer in Hall~B at Jefferson Laboratory. A Barrel Micromegas Tracker made with six concentric cylinders, each made of three 120$^\circ$-sector tiles, surrounds the Silicon Vertex Tracker, and a Forward Micromegas Tracker composed of 6 disks is placed 30~cm downstream of the liquid-hydrogen target. Both trackers sit in a 5~T solenoid magnetic field. All Micromegas elements are based on resistive technology to withstand luminosities up to $10^{35}$~cm$^{-2}$s$^{-1}$, as well as on bulk technology to enforce gain uniformity and mechanical robustness. Due to the high magnetic field, dedicated electronics have been designed and displaced $\sim$2~m away from the detectors. The electronics readout is based on the DREAM ASICs that allow sustained operation up to 20~kHz trigger rate at the maximum luminosity.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Overview of the front-end electronics of CMS HGCal - including readout and powering

The end-cap calorimeters of CMS will be upgraded to a single High Granularity Calorimeter (HG-Cal) for the HL-LHC, including both silicon sensors and scintillator tiles with on-tile SiPMs as active elements. The readout of the active elements is performed by an ASIC (HGCROC in 130 nm CMOS technology) that measures the amplitude and arrival time of the signals. The amplitude is measured over a large dynamic range to allow calibration with single particles and the measurement of TeV showers. The time of arrival of high-energy showers will be measured with a precision of around 30 ps. A second pair of “concentrator” ASICs - ECON-T and ECON-D - takes the data from the HGCROC channels and packages them for transmission via optical links to the off-detector electronics. The ECON-T transmits trigger data at 40 MHz, to form part of the level-1 trigger. The ECON-D transmits concentrated data packets at up to 1 MHz, upon reception of a level-1 trigger signal. In addition to these ASICs, HGCal will use modified versions of common HL-LHC electronics developments, for the power chain and the optical control and readout. The dense nature of the HGCal provides additional challenges for the electronic boards and cabling. In this proceedings the overall HGCal front electronics scheme, including the latest performance of the HGCROC and ECON ASICs is presented.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

Performance and Commissioning of the BigBite Timing Hodoscope for Nucleon Form Factor Measurements at Jefferson Lab

The BigBite Timing Hodoscope detector is the primary subject of this thesis. The Super BigBite Spectrometer is a Jefferson Lab Hall A Collaboration project that has and will continue to measure nucleon electromagnetic form factors. This spectrometer includes the Timing Hodoscope which provides high resolution particle timing data for scattered electrons in the electron arm of BigBite. The Timing Hodoscope utilizes 90, 25 × 25 × 600 mm3 scintillator bars stacked on top of each other to form a single detector plane, and these bars are connected to 180 photo-multiplier tubes via light guides. Particles collide with the scintillating material creating a shower of optical photons and these particle events in the bars are collected to generate signals that are readout by the data acquisition (DAQ) electronics. NINO ASIC amplifier-discriminator cards output signals from the photo-multiplier tubes into analogue and logic signals, which are sent to analogue-to-digital (ADC) and time-to-digital (TDC) converter data acquisition readout modules. This data is then used for analysis of the detector. The focus of this thesis is the construction, commissioning, calibration, and performance of the BigBite Timing Hodoscope before and during the first of five nucleon electromagnetic form factor experiments at Jefferson Lab Hall A. Before the neutron magnetic form factor, G n M, experiment, cosmic ray data was collected during commissioning to confirm proper operation of the Timing Hodoscope electronics by observing the ADC and TDC data. Commissioning studies for charge normalization, gain matching, and other ADC and TDC detector data variables were performed before moving the detector into Hall A. Following installation in Hall A, several calibration studies were implemented to fine-tune the detector in preparation for use in the experiment. The calibration studies included analysis of timing cuts, TDC alignment, the time-walk effect, time difference offsets, and scintillator velocity corrections. Once the Timing Hodoscope was well-calibrated, data-taking during the experiment commenced and the beam-on-target data was used to characterize the Timing Hodoscope performance during the G n M experiment run-time. The performance analysis included studies observing energy deposit, cluster size, rates, accidentals, pile-up, tracking efficiency, position resolution, and time resolution. After application of physics cuts to ensure a data set comprised of particle tracks corresponding to elastic electrons, which is the main data of interest for measurement of G n M, the Timing Hodoscope is shown on average across all kinematic settings to have a >98% tracking efficiency, a position resolution of 4-6 cm in the non-dispersive plane and 1.5-2 cm in the dispersive plane, and a time resolution of 500-750 ps. These performance results are compared to a GEANT4 based performance simulation of the BigBite Timing Hodoscope for reference, showing to what degree the measured performance values match those taken from the simulation.

Marinaro, Ralph↗
DOE OSTI2025

Setup and Testing of PSEC5 ASIC Boards

The PSEC5 ASIC is a high-speed waveform sampling chip developed for precise measurements. This report presents the design review, test board configurations, and results from functional validation of the PSEC5 device. Key aspects examined include power integrity, voltage-controlled oscillator (VCO) behavior, SPI register functionality, clock division characteristics, readout performance, and analog biasing response. Tests were conducted across two boards under varied voltage conditions and signal configurations. Notable observations include robust VCO output, SPI communication irregularities, and anomalous readout conditions. The findings support design iterations for improved ASIC operability and firmware integration.

Fahey, Alexander [North Central Coll.]↗
DOE OSTI2023

Scalable Skipper-CCD Analog Readout Electronics (SSCARE) for the Massive Multichannel OSCURA Experiment

We present a multiplexed analog readout electronics system for Skipper-CCDs based on the MIDNA ASIC. It allows for subelectron noise-level operation while maintaining a minimal number of acquisition channels. In addition, it requires low-disk storage and low-bandwidth data transfer with zero added multiplexing time during the simultaneous operation of thousands of channels. We describe the implementation of such a system in a new instrument composed by 16 sensors operated with a two-stage analog multiplexed readout scheme. The instrument is a part of the R&D effort of the OSCURA experiment.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2025

A Radiation-Hard 8-Channel 15-Bit 40-MSPS ADC for the ATLAS Liquid Argon Calorimeter Readout

The custom design of a radiation-hardened, 8-channel, 40-MSPS, 15-bit resolution, 14.2-bit dynamic range, 11.4-ENOB ADC data acquisition ASIC fabricated in a commercial 65-nm triple-well CMOS technology is presented. The ADC is developed for and integrates seamlessly into the readout system for the ATLAS liquid argon (LAr) calorimeter in the high-luminosity large hadron collider (HLLHC) upgrade at CERN, which will require a total of 364 936 ADC channels. A three-stage MDAC+SAR pipelined ADC architecture was designed to meet the physics requirements and scientific goals of the ATLAS experiment. The ADC is a fully self-contained data acquisition system that includes foreground calibration, digital data processing, digital control, and supporting circuitry. The measured performance shows the ADC achieves a competitive dynamic range and SNDR, and it meets or exceeds the ATLAS analog requirements. Radiation tolerance and scalability design considerations were implemented at the device-, circuit-, and system-level. Radiation-hardening-by-design techniques used include redundancy for digital circuits, the use of MiM capacitors, and a hybrid RC-DAC for the ADC core. The ADC ASIC was demonstrated to be robust against the effects of the intense radiation expected in the HL-LHC experimental environment.

DAQ↗
DOE OSTI2020

The Analog Front-end for the LGAD Based Precision Timing Application in CMS ETL

The analog front-end for the Low Gain Avalanche Detector (LGAD) based precision timing application in the CMS Endcap Timing Layer (ETL) has been prototyped in a 65 nm CMOS mini-ASIC named ETROC0. Serving as the very first prototype of ETL readout chip (ETROC), ETROC0 aims to study and demonstrate the performance of the analog frontend, with the goal to achieve 40 to 50 ps time resolution per hit with LGAD (therefore reach about 30ps per track with two detector-layer hits per track). ETROC0 consists of preamplifier and discriminator stages, which amplifies the LGAD signal and generates digital pulses containing time of arrival and time over threshold information. This paper will focus on the design considerations that lead to the ETROC front-end architecture choice, the key design features of the building blocks, the methodology of using the LGAD simulation data to evaluate and optimize the front-end design. The ETROC0 prototype chips have been extensively tested using charge injection and the measured performance agrees well with simulation. The initial beam test results are also presented, with time resolution of around 33 ps observed from the preamplifier waveform analysis and around 41 ps from the discriminator pulses analysis. A subset of ETROC0 chips have also been tested to a total ionizing dose of 100 MRad with X-ray and no performance degradation been observed.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

PSEC5 Physical Verification

Ultra-Fast timing detectors, having a time resolution of 10pSec or less, are becoming increasingly important for many scientific disciplines, including High Energy Physics, Nuclear Physics, Medical Imaging and more. When developing ultra-fast detectors such as MCPs, LAPPDs, LGADs, SNSPDs, it is necessary to have access to a readout system that is low power, can support many channels and is cost effective. The PSEC5 chip was an application specific integrated circuit (ASIC) developed by the pioneering group of Prof. Henry Frisch at University of Chicago and micro electronic engineers at Fermi National Accelerator Laboratory. Three boards were designed, two to implement the readout system for an LAPPD and one to only characterize the PSEC1 chip. The main goal of the project shifted to setting up a testing environment to focus on the characterization of the chip. My student and I tested and characterized this ASIC using the third chip-on-board printed circuit board. Results show the successful fabrication and operation of some of the key building blocks and lead to the suggestions on modification for the second iteration of the chip.

Rico Aniles, H. D. [Unlisted]↗