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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Rate-capability of the VMM3a front-end in the RD51 Scalable Readout System

The VMM3a is an Application Specific Integrated Circuit (ASIC), specifically developed for the readout of gaseous detectors. Originally developed within the ATLAS New Small Wheel (NSW) upgrade, it has been successfully integrated into the Scalable Readout System (SRS) of the RD51 collaboration. This allows, to use the VMM3a also in small laboratory set-ups and mid-scale experiments, which make use of Micro-Pattern Gaseous Detectors (MPGDs). As part of the integration of the VMM3a into the SRS, the readout and data transfer scheme was optimised to reach a high rate-capability of the entire readout system and profit from the VMM3a's high single-channel rate-capability of 3.6Mhits/s. The optimisation focused mainly on the handling of the data output stream of the VMM3a, but also on the development of a trigger-logic between the front-end cards and the DAQ computer. In this article, two firmware implementations of the non-ATLAS continuous readout mode are presented, as well as the implementation of the trigger-logic. Afterwards, a short overview on X-ray imaging results is presented, to illustrate the high rate-capability from an application point-of-view.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2024

Characterization of ORNL PSD ASIC

The performance of the ORNL ASIC and its readout system was tested with pixelated organic scintillators. We use a pixelated trans-Stilbene scintillator array from Inrad Optics and a pixelated organic glass scintillator array developed at Sandia National Laboratories to characterize the energy and timing resolutions and the pulse-shape discrimination (PSD) figure-of-merit (FoM). The results are compared to previous work in which the same metrics were measured on waveforms digitized at 250 MHz with 14-bit resolution. We found that the PSD FoM at 340 keVee of the ASIC configuration compared to waveform data varied with the scintillator type. We measured a PSD FoM of 1.12 ± 0.14 with the ASIC configuration versus 1.39 ± 0.23 with waveform data using the trans-Stilbene array. We measured a PSD FoM of 0.52 ± 0.18 with the ASIC configuration versus 1.25 ± 0.19 with waveform data using the the organic glass scintillator array. The coincidence timing resolution was measured using two 6x6x6 mm 3 cubes of trans-Stilbene. It was measured to be 805 ± 9 ps with the ASIC configuration versus 300 ps on average with waveform data.

42 ENGINEERING↗
NASA NTRSDate not supplied

Design and Performance of the CdZnTe VFG Imaging Calorimeter Prototype for Gamma-ray Astronomy

We present the design and first results of the CdZnTe Imaging calorimeter prototype. The CdZnTe Imaging calorimeter has been designed for use in large astrophysical gamma-ray space instruments, and we report here on a small prototype built to validate the approach. The calorimeter is based on virtual Frisch-grid drift-bar CdZnTe detectors. The design is modular, such that multiple crates of 16 bars, each served by a single ASIC, can be arranged in to different configurations depending on the specific requirements for an instrument. The modules are plugged into the readout motherboard in the designed configuration for a given instrument. The detectors are capable of measuring the interaction point of an incident photon in three dimensions and the energy deposited. In this work, we have designed and built a prototype consisting of 4 by 4 module array and have tested it with various radioactive sources to measure its position and energy resolution. The preliminary results demonstrate ~1% FWHM energy resolution and 1-2 mm position resolution for 662 keV photons (Cs137), subject to the further improvement by applying various corrections. We tested the module with a “conventional” analog ASIC readout as well as a wave-front sampling ASIC to compare the results, which is critical for the optimization of the future instrument.

A. A. Moiseev↗
DOE OSTI2024

ETROC1: the first full chain precision timing prototype ASIC for CMS MTD endcap timing layer upgrade

We present the design and characterization of the first fullchain precision timing prototype ASIC, named ETL Readout Chipversion 1 (ETROC1) for the CMS MTD endcap timing layer (ETL)upgrade. The ETL utilizes Low Gain Avalanche Diode (LGAD) sensors todetect charged particles, with the goal to achieve a time resolutionof 40–50 ps per hit, and 30–40 ps per track with hits from twodetector layers. The ETROC1 is composed of a 5 × 5 pixelarray and peripheral circuits. The pixel array includes a4 × 4 active pixel array with an H-tree shaped networkdelivering clock and charge injection signals. Each active pixel iscomposed of various components, including a bump pad, a chargeinjection circuit, a pre-amplifier, a discriminator, adigital-to-analog converter, and a time-to-digital converter. Thesecomponents play essential roles as the front-end link in processingLGAD signals and measuring timing-related information. Theperipheral circuits provide clock signals and readoutfunctionalities. The size of the ETROC1 chip is7 mm× 9 mm. ETROC1 has been fabricated in a 65 nmCMOS process, and extensively tested under stimuli of chargeinjection, infrared laser, and proton beam. The time resolution ofbump-bonded ETROC1 + LGAD chipsets reaches 42–46 ps per hit in thebeam test.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRSDate not supplied

Radiation-Hard Parallel Readout Circuit for Low-Frequency Voltage Signal Measurements

NASA Goddard Space Flight Center (GSFC) has successfully developed and tested a custom-designed low-noise multi-channel digitizer (MCD) application specific integrated circuit (ASIC) for operation in harsh radiation environments. The MCD-ASIC is optimized for low-frequency and low-voltage signal measurements from sensors and transducers. It has 20 input channels where each channel is comprised of auto-zeroed chopper variable-gain amplifier, post amplifier, and a second order ∑∆ modulator. ∑∆ analog-to-digital converter (ADC) relies on oversampling and noise shaping to achieve high-resolution conversion. However, the MCD-ASIC requires digital filtering and decimation to convert the output single bit streams from the ADC to useful data words. A parallel digital platform such as a field-programmable-gate-array (FPGA) is highly suitable to fully leverage the capabilities of the MCD-ASIC. The FPGA controls the MCD-ASIC via serial peripheral interface (SPI) protocol and acquires data from it. A Python-script communicates with the FPGA board through a USB interface on a cross operating platform. Using this architecture, the system is capable of monitoring up to 20 voltage readout channels simultaneously in a real-time manner. Each channel’s parameters can be programmed independently allowing maximum user versatility. In this paper, we present analysis of the analog front-end, the implementation of the digital processing unit on the FPGA, and provide noise performance results from the MCD-ASIC readout.

ASIC↗
DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗
DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗
DOE OSTI2023

The COLUTA ADC ASIC and the ATLAS HL-LHC Liquid Argon Front-End Readout

Abstract The upgraded High-Luminosity Large Hadron Collider (HL-LHC) requires a new radiation tolerant ATLAS Liquid Argon (LAr) Calorimeter readout operating at 40 MHz with 16-bit dynamic range. The Front-End Board 2 (FEB2) will provide the front-end readout for the calorimeter, and will interface a series of custom ASICs due to radiation tolerance requirements of the HL-LHC. The COLUTA is a 65 nm CMOS custom 8-channel 15-bit 40 MSPS ADC ASIC developed for this application. This contribution will present performance results of the final prototype of the COLUTA, surpassing specifications at >11.5 ENOB for relevant frequencies, as well as non-linearity and radiation requirements. Preliminary integration results of the front-end readout components will also be described by means of the FEB2 Pre-Prototype, the “Slice Testboard”.

Instruments & Instrumentation↗
DOE OSTI2024

Performance of a second generation of the Fermilab Constant Fraction Discriminator ASIC for time-stamping long-strip AC-LGAD sensors.

We present the design and performance characterization results of the second generation of the novel Fermilab Constant Fraction Discriminator ASIC (FCFD) developed to readout AC-coupled low gain avalanche detector (AC-LGAD) sensors. This study presents the performance of the ASIC which was optimized specifically for reading out strip AC-LGAD sensors designed for ePIC experiment at EiC. Performance was measured using charge injection and particle beams with prototype AC-LGAD sensors wirebonded to the FCFD ASIC.

Apresyan, A.↗
DOE OSTI2024

ASIC Scoping Study Final Report

This report documents the results and findings of a one-year scoping study investigating multichannel readout application specific integrated circuits (ASICs) for interfacing to, and processing data from, silicon photomultiplier (SiPM) arrays. We document ASIC desired and required specifications for four applications supporting national security mission areas: neutron radiography, associated particle imaging, and two versions of kinematic neutron imaging cameras. While each application has a few unique requirements that stress capability, there is generally good agreement among most. Two recently developed ASIC devices were evaluated in a system-like configuration by interfacing these to scintillator crystals exposed to gamma and neutron sources. The 64-channel ORNL device delivered functional capability while meeting most mission requirements for neutron radiography. The Nalu Scientific device, a 32-channel full waveform digitizer, did not demonstrate reliable neutron / gamma separation but it is unclear if this was an ASIC issue or problems with test setup or firmware. A literature survey of other commercial and academic ASICs was undertaken to with the conclusion that existing devices do not meet all requirements.

42 ENGINEERING↗
DOE OSTI2026

Characterization of the First Prototype of the L1K65n Differential-Output Charge-Sensitive Preamplifier ASIC for High-Performance, Low-Background HPGe Detector Readout

Next-generation neutrinoless double-beta (0νββ) decay searches require a large detector/isotope mass and very low radioactive backgrounds. The upcoming LEGEND-1000 experiment (Large Enriched Germanium Experiment for Neutrinoless double-beta Decay) constitute a ton-scale array of several hundred high-purity germanium (HPGe) detectors enriched in 76Ge, the isotope of interest. It aims to reach a sensitivity beyond 10 28 years on the 0νββ decay half-life of 76Ge, necessitating an order of magnitude reduction in background with respect to the state of the art. This will require the implementation of a dedicated application specific integrated circuit (ASIC) preamplifier that will significantly lower background contribution compared to the conventional low-mass front end (LMFE) employed in the Majorana Demonstrator and LEGEND-200 experiments while maintaining or improving energy resolution and other performance parameters. Features include a high (9 MeV) dynamic range with noise low enough to achieve a trigger threshold of <1 keV, a single power supply to reduce background-inducing cabling, and a differential output to maintain signal integrity over several meters of transmission line. The chip would be optimized to operate in liquid argon (87 K) and be able to do so reliably for ten years. Following on from an earlier 180-nm prototype, we have developed a differential-output charge-sensitive preamplifier ASIC fabricated in a 65-nm process, 1×2 mm in size, that addresses these needs. Here, we present recent results from the successful testing and characterization of the first version of this device.

ASIC↗
DOE OSTI2023

Design and performance of the Fermilab Constant Fraction Discriminator ASIC

Here, we present the design and performance characterization results of the novel Fermilab Constant Fraction Discriminator ASIC (FCFD) developed to readout low gain avalanche detector (LGAD) signals by directly using a constant fraction discriminator (CFD) to measure signal arrival time. Silicon detectors with time resolutions less than 30ps will play a critical role in future collider experiments, and LGADs have been demonstrated to provide the required time resolution and radiation tolerance for many such applications. The FCFD has a specially designed discriminator that is robust against amplitude variations of the signal from the LGAD that normally requires an additional correction step when using a traditional leading edge discriminator. The application of the CFD directly in the ASIC promises to be more reliable and reduces the complication of evolving time-walk corrections throughout the operational lifetime of the detector system. We will present a summary of the measured performance of the FCFD for input signals generated by internal charge injection, LGAD signals from an infrared laser, and LGAD signals from minimum-ionizing particles. The mean time response for LGAD signals with charge ranging between 5 and 26 fC has been measured to vary no more than 10ps, orders of magnitude more stable than an uncorrected leading edge discriminator based measurement, and effectively removes the need for any additional time-walk correction. The measured contribution to the time resolution from the FCFD ASIC is found to be 10ps for signals with charge above 20fC.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

Multiplicity trigger detector for the S π RIT experiment

A multiplicity trigger detector (MTD) was developed for the SπRIT experiment that aims to probe the high- density symmetry energy via heavy-ion collisions (HICs). The MTD is designed to measure the charged-particle multiplicity in HICs to provide a trigger signal that can be used to select high-multiplicity events induced by central collisions. The MTD consists of two side-walls segmented into 30 plastic scintillation paddles, each equipped with a multi-pixel photon counter. A custom board with EASIROC front-end ASIC is used as readout electronics. A multiplicity logic signal is generated by an on-board FPGA that processes the discriminated signals from EASIROCs. The overall latency of the whole detector system for outputting the trigger is less than 100 ns, including 52 ns of electronics latency for processing the signals. During the measurement of 112 Sn + 124 Sn reactions at an incident energy of 270 MeV/nucleon, the minimum multiplicity threshold of the MTD was set to 4, where the overall trigger efficiency was obtained to be about 39 % for inclusive nuclear reactions. Furthermore, a simulation study with a numerical calculation of HICs found that the central collisions of impact parameters of less than 4 fm can be triggered with a high efficiency of more than 95 % by the experimental trigger condition.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2020

Characterization of a gigabit transceiver for the ATLAS inner tracker pixel detector readout upgrade

We present a gigabit transceiver prototype Application Specific Integrated Circuit (ASIC), GBCR, for the ATLAS Inner Tracker (ITk) Pixel detector readout upgrade. GBCR is designed in a 65-nm CMOS technology and consists of four upstream receiver channels, a downstream transmitter channel, and an Inter-Integrated Circuit (I2C) slave. The upstream channels receive the data at 5.12 Gbps passing through 5-meter 34-American Wire Gauge (AWG) Twin-axial (Twinax) cables, equalize and retime them with a recovered clock, and then drive an optical transmitter. The downstream channel receives the data at 2.56 Gbps from an optical receiver and drives the cable as same as the upstream channels. The jitter of the upstream channel output is measured to be 35 ps (peak-peak) when the Clock-Data Recovery (CDR) module is turned on and the jitter of the downstream channel output after the cable is 138 ps (peak-peak). The power consumption of each upstream channel is 72 mW when the CDR module is turned on and the downstream channel consumes 27 mW. GBCR survives the total ionizing dose of 200 kGy.

47 OTHER INSTRUMENTATION↗
DOE OSTI2021

Characterization of the CMS Endcap Timing Layer readout chip prototype with charge injection

We present the characterization of a readout Application-Specific Integrated Circuit (ASIC) for the CMS Endcap Timing Layer (ETL) of the High-Luminosity LHC upgrade with charge injection. The ASIC, named ETROC and developed in a 65 nm CMOS technology, reads out a 16× 16 pixel matrix of the Low-Gain Avalanche Detector (LGAD). The jitter contribution from ETROC is required to be below 40 ps to achieve the 50 ps overall time resolution per hit. The analog readout circuits in ETROC consist of the preamplifier and the discriminator. The preamplifier handles the LGAD charge signal with the most probable value of around 15 fC. The discriminator generates the digital pulse, which provides the Time-Of-Arrival (TOA, leading edge) and Time-Over-Threshold (TOT, pulse width) information. The prototype of ETROC (ETROC0) that implements a single channel of analog readout circuits has been evaluated with charge injection. The jitter of the analog readout circuits, measured from the discriminator's leading edge, is better than 16 ps for a charge larger than 15 fC with the sensor capacitance. The time walk resulting from different pulse heights can be corrected using the TOT measurement. The time resolution distribution has a standard deviation of 29 ps after the time-walk correction from the charge injection. At room temperature, the preamplifier's power consumption is measured to be 0.74 mW and 1.53 mW per pixel in the low- and high-power mode, respectively. Finally, the measured power consumption of the discriminator is 0.84 mW per pixel. With the ASIC alone or the LGAD sensor, The characterization performances fulfill the ETL's challenging requirements.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Test and characterization of finely segmented pixel CZT detectors for future hard x-ray missions

The NuSTAR (Nuclear Spectroscopic Telescope Array) mission was launched in 2012, and it has successfully deployed the first orbiting telescopes to focus high energy X-ray (3 - 79 keV) light, providing a wealth of new information on high-energy X-rays sources. Follow-up missions, such as the proposed HEX-P, BEST, and FORCE, could perform a deeper black hole census providing a more refined measurement of black hole spins, allowing for greater knowledge about supermassive black holes. Here, these missions are motivated by the recent breakthroughs in the hard X-ray mirror technologies, where mirrors, either made of monolithic silicon segments, or made directly or via replication of shells, demonstrate the feasibility of making hard X-ray mirrors with angular resolutions of 5-10 arc-seconds Half Power Diameter (HPD) compared to the NuSTAR’s 1 arc-minute HPD. Such a high angular resolution requires matched detectors with higher degree of segmentation to fully benefit from the achievable improved spatial resolution. In the above framework, the HEXID ASIC, a novel pixelated front-end suitable for reading out a finely segmented CZT sensor with 150 μm pixel pitch in a hexagonal arrangement has been developed. This readout pixelated chip is capable of processing photon-generated charge packets over a large dynamic range (from 2 keV up to 180 keV), while keeping a low input noise (ENC <20 e - ). In this work, the initial characterization of the ASIC prototype will be presented.

47 OTHER INSTRUMENTATION↗
DOE OSTI2024

A Modular 512-Channel Neural Signal Acquisition ASIC for High-Density 4096 Channel Electrophysiology

The complexity of information processing in the brain requires the development of technologies that can provide spatial and temporal resolution by means of dense electrode arrays paired with high-channel-count signal acquisition electronics. In this work, we present an ultra-low noise modular 512-channel neural recording circuit that is scalable to up to 4096 simultaneously recording channels. The neural readout application-specific integrated circuit (ASIC) uses a dense 8.2 mm × 6.8 mm 2D layout to enable high-channel count, creating an ultra-light 350 mg flexible module. The module can be deployed on headstages for small animals like rodents and songbirds, and it can be integrated with a variety of electrode arrays. The chip was fabricated in a TSMC 0.18 µm 1.8 V CMOS technology and dissipates a total of 125 mW. Each DC-coupled channel features a gain and bandwidth programmable analog front-end along with 14 b analog-to-digital conversion at speeds up to 30 kS/s. Additionally, each front-end includes programmable electrode plating and electrode impedance measurement capability. We present both standalone and in vivo measurements results, demonstrating the readout of spikes and field potentials that are modulated by a sensory input.

47 OTHER INSTRUMENTATION↗