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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4

All sources NASA NTRS DOE OSTI

NASA NTRS1985

Bubble memory module for spacecraft application

Bubble domain technology offers an all-solid-state alternative for data storage in onboard data systems. A versatile modular bubble memory concept was developed. The key module is the bubble memory module which contains all of the storage devices and circuitry for accessing these devices. This report documents the bubble memory module design and preliminary hardware designs aimed at memory module functional demonstration with available commercial bubble devices. The system architecture provides simultaneous operation of bubble devices to attain high data rates. Banks of bubble devices are accessed by a given bubble controller to minimize controller parts. A power strobing technique is discussed which could minimize the average system power dissipation. A fast initialization method using EEPROM (electrically erasable, programmable read-only memory) devices promotes fast access. Noise and crosstalk problems and implementations to minimize these are discussed. Flight memory systems which incorporate the concepts and techniques of this work could now be developed for applications.

Hayes, P. J.↗

NASA NTRS2013

FPGA Flash Memory High Speed Data Acquisition

The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

Gonzalez, April↗

NASA NTRS1985

Programable Driver for Voltage-Controlled Oscillators

Electronically programable read-only memory (EPROM) and digital-to-analog converter provide customized time-varying voltage for frequency modulation. Voltage used to modulate IMPATT oscillator that serves as microwave pump for solid-state maser in low-noise amplifier. EPROM simple to tailor voltage waveform to suit characteristics of given maser. Digital information for waveform programed into EPROM chip; digital-to-analog converter reads information and produces corresponding analog wave. Principle readily adapted to other applications.

Fowler, L. E.↗

NASA NTRS1988

Feedforward, high density, programmable read only neural network based memory system

Neural network-inspired, nonvolatile, programmable associative memory using thin-film technology is demonstrated. The details of the architecture, which uses programmable resistive connection matrices in synaptic arrays and current summing and thresholding amplifiers as neurons, are described. Several synapse configurations for a high-density array of a binary connection matrix are also described. Test circuits are evaluated for operational feasibility and to demonstrate the speed of the read operation. The results are discussed to highlight the potential for a read data rate exceeding 10 megabits/sec.

Daud, Taher↗

NASA NTRS1970

Rapid method for interconversion of binary and decimal numbers

Decoding tree consisting of 40-bit semiconductor read-only memories interconverts binary and decimal numbers 50 to 100 times faster than current methods. Decimal-to-binary conversion algorithm is based on a divided-by-2 iterative equation, binary-to-decimal conversion algorithm utilizes multiplied-by-2 iterative equation.

Lim, R. S.↗

NASA NTRS1972

Digital filter realizations using a special-purpose stored-program computer.

A special-purpose computer is organized to realize a second-order digital filter in a choice of 11 programming forms. Instructions for the forms are stored in a fast-access READ-ONLY memory. Also, a hard-wired multiplier is employed in the Arithmetic Unit to decrease computation time. The multiplier is organized into uniform functional blocks that are suitable for large-scale integration (LSI). A computer-aided design (CAD) program may be used to select the best filter programming form for a given filter transfer function D(z). The CAD program also aids in the location of the binary point in the data registers of the computer.

White, R.↗

NASA NTRS1973

Alphanumeric character generator for oscilloscope

Compact portable alphanumeric display device can be used with any general-purpose externally-triggered oscilloscope without need for Z-axis modulation. Factors limiting size of display are: output line capacitance, read-only memory speed, and persistence of cathode-ray-tube.

Lockerson, D. C.↗

NASA NTRS1973

Microprogrammed digital filters for strapdown guidance application.

Discussion of an approach for implementing digital filters using microprogrammed control logic with read only memory (ROM) for strapdown guidance applications, and description of a second-order multiplexed system using multiprogrammed control instruction. The microprogramming technique for control using ROM is shown to enhance higher order digital filter realization. The high speed of digital circuits reduces propagation time and facilitates multiplexing. Programmed ROM's can be altered easily for different algorithms.

Kapadia, K.↗

NASA NTRS1974

A magnetic bubble domain flight recorder

A feasibility model of an all-electronic bubble memory system has been constructed. It uses a small 60k bit bubble recorder consisting of 6 chips of 10k bits each mounted in three separate packages operating as a FIFO at a 150 KHz bubble data rate. In addition to serving as a direct tape recorder replacement, the bubble recorder can be programmed for random access to each individual chip for ranom block access operation or for self-checking or by-passing any malfunctioning memory chip. Read and write operations can be performed asynchronously from very low frequency up to basic recording field frequency. A large 50M bit prototype is planned.

Chen, T. T.↗

NASA NTRS1977

Microprogramed telemetry processor

Minimum hardware, reliable processor responds rapidly to changing requirements simply by changes in contents of programmable read-only memory. General purpose controller can transfer data onto and off of data bus, perform logic and arithmetic manipulations, and store pertinent data in small internal random-access memory.

Gordon, L. H.↗

NASA NTRS1975

An interactive method for digitizing zone maps

A method is presented for digitizing maps that consist of zones, such as contour or climatic zone maps. A color-coded map is prepared by any convenient process. The map is then read into memory of an Image 100 computer by means of its table scanner, using colored filters. Zones are separated and stored in themes, using standard classification procedures. Thematic data are written on magnetic tape and these data, appropriately coded, are combined to make a digitized image on tape. Step-by-step procedures are given for digitization of crop moisture index maps with this procedure. In addition, a complete example of the digitization of a climatic zone map is given.

Giddings, L. E.↗

NASA NTRS1975

Multimission spacecraft Dataplexer

The data multiplexing unit described is a low-power small-size building-block-type central data system designed for use on such spacecraft as the International Ultraviolet Explorer or the International Sun-Earth Explorer. Preprogrammed read-only memories are used to generate the telemetry format tailored to particular mission requirements. Low weight and low power dissipation are achieved with the aid of PMOS technology. The use of subcommutators in groups to meet particular spacecraft requirements allows low data rate experiments to be time-multiplexed into a single main input channel, to improve data collection and processing operations. The block diagram of the Dataplexer is discussed.

Cosme, R.↗

NASA NTRS1977

Programmable data communications controller requirements

The design requirements for a Programmable Data Communications Controller (PDCC) that reduces the difficulties in attaching data terminal equipment to a computer are presented. The PDCC is an interface between the computer I/O channel and the bit serial communication lines. Each communication line is supported by a communication port that handles all line control functions and performs most terminal control functions. The port is fabricated on a printed circuit board that plugs into a card chassis, mating with a connector that is joined to all other card stations by a data bus. Ports are individually programmable; each includes a microprocessor, a programmable read-only memory for instruction storage, and a random access memory for data storage.

Source record↗

NASA NTRS1979

CMOS-array design-automation techniques

Thirty four page report discusses design of 4,096-bit complementary metal oxide semiconductor (CMOS) read-only memory (ROM). CMOSROM is either mask or laser programable. Report is divided into six sections; section one describes background of ROM chips; section two presents design goals for chip; section three discusses chip implementation and chip statistics; conclusions and recommendations are given in sections four thru six.

Feller, A.↗

NASA NTRS1978

A cycle timer for testing electric vehicles

A cycle timer was developed to assist the driver of an electric vehicle in more accurately following and repeating SAE driving schedules. These schedules require operating an electric vehicle in a selected stop-and-go driving cycle and repeating this cycle pattern until the vehicle ceases to meet the requirements of the cycle. The heart of the system is a programmable read-only memory (PROM) that has the required test profiles permanently recorded on plug-in cards, one card for each different driving schedule. The PROM generates a direct current analog signal that drives a speedometer displayed on one scale of a dual movement meter. The second scale of the dual movement meter displays the actual speed of the vehicle as recorded by the fifth wheel. The vehicle operator controls vehicle speed to match the desired profile speed. The PROM controls the recycle start time as well as the buzzer activation. The cycle programmer is powered by the test vehicle's 12-volt accessory battery, through a 5-volt regulator and a 12-volt dc-to-dc converter.

Soltis, R. F.↗

NASA NTRS1979

A structure for digital notch filters

Narrow-band digital notch filters have their poles near the unit circle. As the sampling rate is increased, the poles move towards Z = +1. Implementing such filters requires long registers to overcome the sensitivity and roundoff errors. A filter structure based on digital incremental computers is proposed which has low sensitivity and round-off errors, and simple hardware implementation. The filter structure can be directly used on differentially pulse-code modulated signals. Hardware multipliers are not required as the poles approach z = +1, and excellent results can be obtained using multipliers with very short word lengths, or with small size read-only memories.

Abu-El-haija, A. I.↗

NASA NTRS1978

A cycle timer for testing electric vehicles

The paper presents a cycle timer which enables the accurate following and repetition of SAE driving schedules of stop and go cycles, for electric vehicles, by reducing the human factor. The system which consists of a programmable read-only memory (PROM) stores each of these cycles, which are detailed, on its own plug-in card. The actual vehicle speed, and the PROM indicated desired speed are displayed on a dual scale meter allowing the driver to match them. A speed change is preceded by a half second buzzer warning and a new cycle by a one second warning. The PROM controls the recycle start time as well as the buzzer activation. A 5 volt regulator providing logic power, and a 12 volt dc-dc converter providing analog and memory power are described.

Soltis, R. F.↗

NASA NTRS1980

Microprocessor-based detector for PSK commands

Command detector unit operates over wide range of data rates and signal levels in space environment. It consists of signal conditioning, read-only memory, random-access memory, and digital processor. Entire unit fits on single multilayer printed-wiring board.

Durden, J.↗