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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4

All sources NASA NTRS DOE OSTI

DOE OSTI2016

Communications systems and methods for subsea processors

A subsea processor may be located near the seabed of a drilling site and used to coordinate operations of underwater drilling components. The subsea processor may be enclosed in a single interchangeable unit that fits a receptor on an underwater drilling component, such as a blow-out preventer (BOP). The subsea processor may issue commands to control the BOP and receive measurements from sensors located throughout the BOP. A shared communications bus may interconnect the subsea processor and underwater components and the subsea processor and a surface or onshore network. The shared communications bus may be operated according to a time division multiple access (TDMA) scheme.

02 PETROLEUM↗

DOE OSTI2016

Multiple core computer processor with globally-accessible local memories

A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

Light-weight cache coherence for data processors with limited data sharing

A data processing system includes a plurality of processors, local memories associated with a corresponding processor, and at least one inter-processor link. In response to a first processor performing a load or store operation on an address of a corresponding local memory that is not currently in the local cache, a local cache allocates a first cache line and encodes a local state with the first cache line. In response to a load operation from an address of a remote memory that is not currently in the local cache, the local cache allocates a second cache line and encodes a remote state with the second cache line. The first processor performs subsequent loads and stores on the first cache line in the local cache in response to the local state, and subsequent loads from the second cache line in the local cache in response to the remote state.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

Multiple core computer processor with globally-accessible local memories

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2020

Subsea processor for underwater drilling operations

A subsea processor may be located near the seabed of a drilling site and used to coordinate operations of underwater drilling components. The subsea processor may be enclosed in a single interchangeable unit that fits a receptor on an underwater drilling component, such as a blow-out preventer (BOP). The subsea processor may issue commands to control the BOP and receive measurements from sensors located throughout the BOP. The subsea processor may relay information to the surface for recording or monitoring. The subsea processor may also be programmed with a model from which to base operation of the BOP, such as in emergency conditions.

42 ENGINEERING↗

NASA NTRS2015

An Efficient Solution Method for Multibody Systems with Loops Using Multiple Processors

This paper describes a multibody dynamics algorithm formulated for parallel implementation on multiprocessor computing platforms using the divide-and-conquer approach. The system of interest is a general topology of rigid and elastic articulated bodies with or without loops. The algorithm divides the multibody system into a number of smaller sets of bodies in chain or tree structures, called "branches" at convenient joints called "connection points", and uses an Order-N (O (N)) approach to formulate the dynamics of each branch in terms of the unknown spatial connection forces. The equations of motion for the branches, leaving the connection forces as unknowns, are implemented in separate processors in parallel for computational efficiency, and the equations for all the unknown connection forces are synthesized and solved in one or several processors. The performances of two implementations of this divide-and-conquer algorithm in multiple processors are compared with an existing method implemented on a single processor.

Multibody dynamics↗

DOE OSTI2018

Algorithmic Patterns for $$\mathcal {H}$$-Matrices on Many-Core Processors

In this work, we consider the reformulation of hierarchical ( $\mathcal {H}$ ) matrix algorithms for many-core processors with a model implementation on graphics processing units (GPUs). $\mathcal {H}$ matrices approximate specific dense matrices, e.g., from discretized integral equations or kernel ridge regression, leading to log-linear time complexity in dense matrix–vector products. The parallelization of $\mathcal {H}$ matrix operations on many-core processors is difficult due to the complex nature of the underlying algorithms. While previous algorithmic advances for many-core hardware focused on accelerating existing $\mathcal {H}$ matrix CPU implementations by many-core processors, we here aim at totally relying on that processor type. As main contribution, we introduce the necessary parallel algorithmic patterns allowing to map the full $\mathcal {H}$ matrix construction and the fast matrix–vector product to many-core hardware. In this work, crucial ingredients are space filling curves, parallel tree traversal and batching of linear algebra operations. The resulting model GPU implementation hmglib is the, to the best of the authors knowledge, first entirely GPU-based Open Source $\mathcal {H}$ matrix library of this kind. We investigate application examples as present in kernel ridge regression, Gaussian Process Regression and kernel-based interpolation. In this context, an in-depth performance analysis and a comparative performance study against a standard multi-core CPU $\mathcal {H}$ matrix library highlights profound speedups of our many-core parallel approach.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2017

Random access quantum information processors using multimode circuit quantum electrodynamics

Qubit connectivity is an important property of a quantum processor, with an ideal processor having random access—the ability of arbitrary qubit pairs to interact directly. This a challenge with superconducting circuits, as state-of-the-art architectures rely on only nearest-neighbor coupling. Here, we implement a random access superconducting quantum information processor, demonstrating universal operations on a nine-qubit memory, with a Josephson junction transmon circuit serving as the central processor. The quantum memory uses the eigenmodes of a linear array of coupled superconducting resonators. We selectively stimulate vacuum Rabi oscillations between the transmon and individual eigenmodes through parametric flux modulation of the transmon frequency. Utilizing these oscillations, we perform a universal set of quantum gates on 38 arbitrary pairs of modes and prepare multimode entangled states, all using only two control lines. We thus achieve hardware-efficient random access multi-qubit control in an architecture compatible with long-lived microwave cavity-based quantum memories.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2025

Mitigating cosmic-ray-like correlated events with a modular quantum processor

Quantum processors based on superconducting qubits are being scaled to larger qubit numbers, enabling the implementation of small-scale quantum error-correction codes. However, catastrophic chip-scale correlated errors have been observed in these processors, attributed to, e.g., cosmic ray impacts, which challenge conventional error-correction codes such as the surface code. These events are characterized by a temporary but pronounced suppression of the qubit-energy relaxation times. Here, in this study, we explore the potential for modular quantum computing architectures to mitigate such correlated energy decay events. We measure cosmic-ray-like events in a quantum processor comprising a motherboard and two flip-chip bonded daughterboard modules, each module containing two superconducting qubits. We monitor the appearance of correlated qubit decay events within a single module and across the physically separated modules. We find that while decay events within one module are strongly correlated (over 85%), events in separate modules only display approximately 2% correlations. We also report coincident decay events in the motherboard and in either of the two daughterboard modules, providing further insight into the nature of these decay events. These results suggest that modular architectures, combined with bespoke errorcorrection codes, offer a promising approach for protecting future quantum processors from chip-scale correlated errors.

Wu, Xuntao [Univ. of Chicago, IL (United States)] ↗

DOE OSTI2025

Efficient frequency allocation for superconducting quantum processors using improved optimization techniques

Building on previous research on frequency allocation optimization for superconducting circuit quantum processors, this work incorporates several techniques to improve overall solution quality. Here, we introduce constraints and imposed edgewise differences help to improve the optimization results. We also introduce optimization variables for the orientation of each edge, defined as the direction from the control qubit to the target qubit, to be chosen during optimization. To scale up to larger processors, multimodule designs are employed with various boundary conditions, thereby enhancing the collective yield. These enhancements allow for greater flexibility in processor design by eliminating the need for handpicked orientations. We support the efficient assembly of large processors with dense connectivity by choosing the best boundary conditions. Examples demonstrate that, at low computational cost, this optimization approach finds a frequency configuration for a square chip with over 1000 qubits and over 10% yield at much larger dispersion levels than required by previous approaches.

Zhang, Zewen [Argonne National Laboratory (ANL), A↗

DOE OSTI2021

Quantum Computer-Aided Design: Digital Quantum Simulation of Quantum Processors

With the increasing size of quantum processors, submodules that constitute the processor hardware will become too large to accurately simulate on a classical computer. Therefore, one would soon have to fabricate and test each new design primitive and parameter choice in time-consuming coordination between design, fabrication, and experimental validation. Here we show how one can design and test the performance of next-generation quantum hardware—by using existing quantum computers. Focusing on superconducting transmon processors as a prominent hardware platform, we compute the static and dynamic properties of individual and coupled transmons. We show how the energy spectra of transmons can be obtained by variational hybrid quantum-classical algorithms that are well suited for near-term noisy quantum computers. In addition, single- and two-qubit gate simulations are demonstrated via Suzuki-Trotter decomposition. Our methods pave a promising way towards designing candidate quantum processors when the demands of calculating submodule properties exceed the capabilities of classical computing resources.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2023

Mitigation of Cosmic Rays-Induced Errors in Superconducting Quantum Processors

Environmental radioactivity and cosmic-rays have recently been identified as a source of decoherence in super-conducting quantum bits (qubits). In particular, the absorption of cosmic-ray muons and gamma rays emitted by naturally occurring radioactive isotopes in the qubit substrate leads to correlated errors in superconducting quantum processors, posing significant challenges to quantum error correction. To enable quantum computing to scale, it is therefore necessary the devel-opment of mitigation strategies to prevent, or keep under control, error bursts due to particle impacts in the chip. While most environmental radioactive sources can be effectively suppressed using dedicated shielding, cosmic-ray muons, with their high penetration capability, can only be mitigated by moving the entire facility in a deep underground laboratory. This work explores the potential for developing a novel class of quantum processors equipped with an active veto system to protect superconducting-based quantum computers from the detrimental effects of atmospheric muons. Such a device would enable the identification of an atmospheric muon interaction within the processor and veto all operations performed during the occurrence of such an interaction. By demonstrating high detection efficiency and negligible dead time, we aim to establish that the future of quantum processors can be envisioned in above-around facilities.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2017

Acceleration of the IMplicit–EXplicit nonhydrostatic unified model of the atmosphere on manycore processors

We present the acceleration of an IMplicit-EXplicit (IMEX) nonhydrostatic atmospheric model on manycore processors such as graphic processing units (GPUs) and Intel's Many Integrated Core (MIC) architecture. IMEX time integration methods sidestep the constraint imposed by the Courant-Friedrichs-Lewy condition on explicit methods through corrective implicit solves within each time step. In this work, we implement and evaluate the performance of IMEX on manycore processors relative to explicit methods. Using 3D-IMEX at Courant number C = 15, we obtained a speedup of about 4x relative to an explicit time stepping method run with the maximum allowable C = 1. Moreover, the unconditional stability of IMEX with respect to the fast waves means the speedup can increase significantly with the Courant number as long as the accuracy of the resulting solution is acceptable. We show a speedup of 100x at C = 150 using 1D-IMEX to demonstrate this point. Several improvements on the IMEX procedure were necessary in order to outperform our results with explicit methods: (a) reducing the number of degrees of freedom of the IMEX formulation by forming the Schur complement, (b) formulating a horizontally explicit vertically implicit 1D-IMEX scheme that has a lower workload and better scalability than 3D-IMEX, (c) using high-order polynomial preconditioners to reduce the condition number of the resulting system, and (d) using a direct solver for the 1D-IMEX method by performing and storing LU factorizations once to obtain a constant cost for any Courant number. Without all of these improvements, explicit time integration methods turned out to be difficult to beat. We discuss in detail the IMEX infrastructure required for formulating and implementing efficient methods on manycore processors. Several parametric studies are conducted to demonstrate the gain from each of the abovementioned improvements. Lastly, we validate our results with standard benchmark problems in numerical weather prediction and evaluate the performance and scalability of the IMEX method using up to 4192 GPUs and 16 Knights Landing processors.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS1973

Highly reliable processor system for space application.

Description of a redundant processor organization which can be implemented with off-the-shelf processors for fault-tolerant operation. Reconfiguration can be performed automatically in a transientless manner. To support this system configuration and redundancy management concept, an operating system referred to as a synchronous executive has been designed. This system is directed at real-time closed-loop space applications where minimum response time, no degradation of software solution, and system simplicity are of importance. The system is based on a multicomputer organization with each machine solving the same problem based on a common set of inputs. Processor status is fed to a higher-level device which selects a controlling processor for controlling outputs and monitoring computers for fault detection.

Tsou, H. S. E.↗

NASA NTRS1974

Power processor design considerations for a solar electric propulsion spacecraft

Propulsion power processor design options are described. The propulsion power processor generated the regulated dc voltages and currents from a solar array source of a solar electric propelled spacecraft. The power processor consisted of 12 power supplies that provide the regulated voltages and currents necessary to power a 30-cm mercury ion thruster. The design options for processing unregulated solar array power and for generating the regulated power required by each supply are studied. The technical approaches utilized in the developed design and the technological limitation of the identified design options are discussed. Alternate approaches for delivering power to a number of mercury ion thrusters and methods of optimizing are described. It was concluded that this power processor design should be considered for application in solar electric propulsion missions of the future.

Costogue, E. N.↗

NASA NTRS1975

A reliability tradeoff study of interconnecting power processors to mercury ion thrusters

A Monte Carlo mission simulation program has been developed to optimize the solar electric propulsion (SEP) thrust subsystem configuration for an Encke comet rendezvous mission. This program examines several possible options for interconnecting power processors to the mercury ion thrusters in order to enhance mission reliability and to reduce SEP subsystem weight. The quantity of power processors and ion thrusters required to perform the mission successfully depends not only on the total required thrust, but also on the individual thruster and power processor performance and reliability. Based on these considerations, it was necessary to determine the quantity of the active power processors and ion thrusters required at any time and the means of providing redundancy. The results provide the basis for selecting an optimum SEP thrust subsystem for this mission and other missions.

Costogue, E. N.↗

NASA NTRS1975

An optical/digital processor - Hardware and applications

A real-time two-dimensional hybrid processor consisting of a coherent optical system, an optical/digital interface, and a PDP-11/15 control minicomputer is described. The input electrical-to-optical transducer is an electron-beam addressed potassium dideuterium phosphate (KD2PO4) light valve. The requirements and hardware for the output optical-to-digital interface, which is constructed from modular computer building blocks, are presented. Initial experimental results demonstrating the operation of this hybrid processor in phased-array radar data processing, synthetic-aperture image correlation, and text correlation are included. The applications chosen emphasize the role of the interface in the analysis of data from an optical processor and possible extensions to the digital feedback control of an optical processor.

Casasent, D.↗

NASA NTRS1978

Electrical Prototype Power Processor for the 30-cm Mercury electric propulsion engine

An Electrical Prototpye Power Processor has been designed to the latest electrical and performance requirements for a flight-type 30-cm ion engine and includes all the necessary power, command, telemetry and control interfaces for a typical electric propulsion subsystem. The power processor was configured into seven separate mechanical modules that would allow subassembly fabrication, test and integration into a complete power processor unit assembly. The conceptual mechanical packaging of the electrical prototype power processor unit demonstrated the relative location of power, high voltage and control electronic components to minimize electrical interactions and to provide adequate thermal control in a vacuum environment. Thermal control was accomplished with a heat pipe simulator attached to the base of the modules.

Biess, J. J.↗