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At least 73 records · Page 4

Uniform sampling analysis of a hybrid phase-locked loop with a sample-and-hold phase detector

Phase-locked-loop (PLL) bit synchronizers often employ integrate-and-dump type phase detectors that provide phase error information only at discrete points in time. Usually these phase detectors are followed by sample-and-hold circuits to produce a stairstep error voltage as the input to a standard analog circuit loop filter. When the loop is configured in this manner, it is referred to as a hybrid PLL. Sampled-data analysis methods (Z transforms) are used to determine the stability and transient response of this loop.

Barab, S.↗

The Phase-Locking of Tropical North Atlantic and the Contribution of ENSO

The Tropical North Atlantic (TNA) is characterized by significant interannual variability in sea surface temperature (SST), which is phase-locked to the boreal spring. In this study, the phase-locking of TNA is investigated by adopting a linear stochastic-dynamical model (SDM) using seasonally modulated TNA feedbacks together with the seasonal modulation of ENSO forcing. In the observations, the role of local TNA feedbacks and ENSO forcing in TNA phase-locking are equivalently important with both preferring the peak of TNA variability to appear in the boreal spring. Besides, the seasonal modulation of TNA feedbacks and ENSO forcing strength are both mainly controlled by thermodynamic processes. In most climate models, the contribution of ENSO on TNA phase-locking is weaker than that in observations. The strength of ENSO-related TNA phase-locking is highly correlated with the relationship between ENSO and TNA, which is mainly determined by the amplitude of ENSO and its teleconnection patterns.

54 ENVIRONMENTAL SCIENCES↗

Phase-locked loops and their application

A collection of papers is presented on the characteristics and capabilities of phase-locked loops (PLLs), along with some applications of interest. The discussion covers basic theory (linear and nonlinear); acquisition; threshold; stability; frequency demodulation and detection; tracking; cycle slipping and loss of lock; phase-locked oscillators; operation and performance in the presence of noise; AGC, AFC, and APC circuits and systems; digital PLL; and applications and miscellaneous. With the rapid development of IC technology, PLLs are expected to be used widely in consumer electronics.

Lindsey, W. C.↗

Digital phase-lock loop

An improved digital phase lock loop incorporates several distinctive features that attain better performance at high loop gain and better phase accuracy. These features include: phase feedback to a number-controlled oscillator in addition to phase rate; analytical tracking of phase (both integer and fractional cycles); an amplitude-insensitive phase extractor; a more accurate method for extracting measured phase; a method for changing loop gain during a track without loss of lock; and a method for avoiding loss of sampled data during computation delay, while maintaining excellent tracking performance. The advantages of using phase and phase-rate feedback are demonstrated by comparing performance with that of rate-only feedback. Extraction of phase by the method of modeling provides accurate phase measurements even when the number-controlled oscillator phase is discontinuously updated.

Thomas, Jr., Jess B.↗

State diagram of magnetostatic coupling phase-locked spin-torque oscillators

The state diagram of magnetostatic coupling phase-locked spin torque oscillator (STO) with perpendicular reference layer and planar field generation layer (FGL) is studied by the macrospin model and the micromagnetic model. The state diagrams of current densities are calculated under various external fields. The simulation shows that there are two phase-lock current density regions. In the phase-locked STOs in low current region I, the spin configuration of FGL is uniform; in high current region II, the spin configuration of FGL is highly nonuniform. In addition, the results with different STOs separation L{sub s} are compared, and the coupling between two STOs is largely decreased when L{sub s} is increased from 40 nm to 60 nm.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Influence of beam-loaded effects on phase-locking in the high power microwave oscillator

Owing to the power limitation of a single device, much more attentions are focused on developing high power microwave (HPM) oscillators that can be phase-locked to the external signal in the recent HPM researches. Although the phase-locking is proved to be feasible in the conventional devices (such as magnetrons), challenges still exist in the HPM devices due to beam-loaded effects, which are more obvious in HPM devices because of its high current and the low Q-factor of the device. A simple structured HPM oscillator (Bitron) is introduced to study such effects on the phase-locking in the HPM oscillator. The self-consistent analysis is carried out to study such effects together with particle in cell simulations. Then the modified Adler equation is established for the phase-locking HPM oscillator. Finally, conditions for the phase-locking in the HPM oscillator are given.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗

Phase-locked telemetry system for rotary instrumentation of turbomachinery, phase 1

A telemetry system for use in making strain and temperature measurements on the rotating components of high speed turbomachines employs phase locked transmitters, which offer greater measurement channel capacity and reliability than existing systems which employ L-C carrier oscillators. A prototype transmitter module was tested at 175 C combined with 40,000 g's acceleration.

Adler, A.↗

Integrated Advanced Microwave Sounding Unit-A (AMSU-A). Performance Verification Report: METSAT Phase Locked Oscillator Assembly, P/N 1334360-1, S/N's F03 and F04

Two Flight Model AMSU-A Phase Locked Oscillators (P/N 1348360-1, S/Ns F03 and F04) have been tested per AES Test Procedure AE-26758. The tests included vibration testing, thermal cycle testing, AM/FM Noise testing, and full functional testing. EMI/REO 2 Testing was not performed. (See test data for S/N F01). Both AMSU-A Phase Locked Oscillators satisfactorily passed all performance requirements of the AE-26633 Product specification. During thermal cycling of PLO serial number F03, the oven and data logger momentarily lost power, including a loss of data. The unit did not experience any thermal stress. TAR 003134 describes the corrective action. Prior to testing PLO serial number FO4, power was applied to the unit. (+15v,-15v) the unit did not display the proper phase lock. Upon test equipment check out a connector was found to be defective. TAR 003133 describes the corrective action. After completion of testing of PLO serial number F04 was installed into Receiver Assembly F02. Upon testing F02 Receiver Assembly the unit was found not to phase lock at ambient temperature. Removal of PLO Assembly F04 was required. R2 was the real issue. Solithane was secondary. Troubleshooting revealed excessive solithane on inner PLL Assembly cover inhibiting optimum grounding. Also, R2 was reselected which increased the lock range from -30 C to +60 C. TAR 002737 describes the corrective action.

Pines, D.↗

Parallel Digital Phase-Locked Loops

Wide-band microwave receivers of proposed type include digital phase-locked loops in which band-pass filtering and down-conversion of input signals implemented by banks of multirate digital filters operating in parallel. Called "parallel digital phase-locked loops" to distinguish them from other digital phase-locked loops. Systems conceived as cost-effective solution to problem of filtering signals at high sampling rates needed to accommodate wide input frequency bands. Each of M filters process 1/M of spectrum of signal.

Sadr, Ramin↗

Extrasensitive phase-locked-loop circuit

Modified phase-locked loop (PLL) generates clock from incoming data signal. To minimize effects of threshold phase-detector gain variations, the PLL uses a dither oscillator, a dither band-pass filter, and correlator instead of coherent amplitude detector.

Nyiri, E. J.↗

Digital phase-locked loop

An digital phase-locked loop is provided for deriving a loop output signal from an accumulator output terminal. A phase detecting exclusive OR gate is fed by the loop digital input and output signals. The output of the phase detector is a bi-level digital signal having a duty cycle indicative of the relative phase of the input and output signals. The accumulator is incremented at a first rate in response to a first output level of the phase detector and at a second rate in response to a second output level of the phase detector.

Cliff, R. A.↗

Phase-lock loop frequency control and the dropout problem

Technique automatically sets the frequency of narrow band phase-lock loops within automatic lock-in-range. It presets a phase-lock loop to a desired center frequency with a closed loop electronic frequency discriminator and holds the phase-lock loop to that center frequency until lock is achieved.

Attwood, S.↗

Performance evaluation of digital phase-locked loops for advanced deep space transponders

The performances of the digital phase-locked loops (DPLL's) for the advanced deep-space transponders (ADT's) are investigated. DPLL's considered in this article are derived from the analog phase-locked loop, which is currently employed by the NASA standard deep space transponder, using S-domain to Z-domain mapping techniques. Three mappings are used to develop digital approximations of the standard deep space analog phase-locked loop, namely the bilinear transformation (BT), impulse invariant transformation (IIT), and step invariant transformation (SIT) techniques. The performance in terms of the closed loop phase and magnitude responses, carrier tracking jitter, and response of the loop to the phase offset (the difference between in incoming phase and reference phase) is evaluated for each digital approximation. Theoretical results of the carrier tracking jitter for command-on and command-off cases are then validated by computer simulation. Both theoretical and computer simulation results show that at high sampling frequency, the DPLL's approximated by all three transformations have the same tracking jitter. However, at low sampling frequency, the digital approximation using BT outperforms the others. The minimum sampling frequency for adequate tracking performance is determined for each digital approximation of the analog loop. In addition, computer simulation shows that the DPLL developed by BT provides faster response to the phase offset than IIT and SIT.

Nguyen, T. M.↗

Phase-locked laser array

A phase-locked laser array comprises a substrate with two spaced-apart pluralities of channels extending towards different reflecting surfaces of the array. The axes of symmetry of the channels of one plurality are offset from the axes of symmetry of the channels of the second plurality. Coupling of light propagating in the optical waveguides over one plurality of channels into the waveguides over the second plurality of channels induces a zero phase difference between the laser oscillations of adjacent channels.

Botez, Dan↗

Diversity-lock phase demodulator

Synchronous diversity-lock phase demodulator for tracking and demodulating orthogonally polarized signals transmitted from satellites

SIGNAL TRANSMISSION↗