SEARCH · Engineering Papers
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Existing and future solid state nonvolatile memory technologies are described and evaluated in this report. Solid state memory technologies can offer size, speed, power, weight, and ruggedness advantages over conventional moving media storage technologoies such as disk or tape. This technology list is a broad sampling of past, present, emerging, and future solid state memory technologies.
Spintronic elements based on spin transfer torque have emerged with potential for on-chip memory, but they suffer from large energy dissipation due to the large current densities required. In contrast, an electric-field-driven magneto-electric storage element can operate with capacitive displacement charge and potentially reach 1-10 µJ cm -2 switching operation. In this paper, magneto-electric switching of a magnetoresistive element is shown, operating at or below 200 mV, with a pathway to get down to 100 mV. A combination of phase detuning is utilized via isovalent La substitution and thickness scaling in multiferroic BiFeO 3 to scale the switching energy density to ≈10 µJ cm -2 . This work provides a template to achieve attojoule-class nonvolatile memories.
In this paper, natural organic honey embedded with carbon nanotubes (CNTs) was studied as a resistive switching material for biodegradable nonvolatile memory in emerging neuromorphic systems. CNTs were dispersed in a honey-water solution with the concentration of 0.2 wt% CNT and 30 wt% honey. The final honey-CNT-water mixture was spin-coated and dried into a thin film sandwiched in between Cu bottom electrode and Al top electrode to form a honey-CNT based resistive switching memory (RSM). Surface morphology, electrical characteristics and current conduction mechanism were investigated. The results show that although CNTs formed agglomerations in the dried honey-CNT film, both switching speed and the stability in SET and RESET process of honey-CNT RSM were improved. The mechanism of current conduction in CNT is governed by Ohm’s law in low-resistance state and the low-voltage range in high-resistance state, but transits to the space charge limited conduction at high voltages approaching the SET voltage.
Nonvolatile memory NVDIMMs, available as Intel Optane, are less expensive than DRAM and bring large byte-addressable storage within reach to many applications. Evaluations on graph analytics have shown promising performance only when DRAM is used as a hardware cache (Memory mode). An open question is whether graph applications can exploit Optane and DRAM directly (AppDirect mode) and achieving better-than-DRAM average bandwidth and run times. We evaluate Optane as a volatile pool on two large-scale graph applications with very different computational patterns, Grappolo and Ripples. We show that AppDirect mode can deliver better-than-DRAM performance, by allocating data structures to Optane and DRAM according to their access characteristics, resulting in higher average memory bandwidth and lower average latency. Memory mode provides DRAM-competitive performance with capacity equal to persistent memory. We demonstrate occasional 4x improvement using the latest AppDirect option and frequently observe competitive performance between Optane AppDirect Memory modes and DRAM.
The availability of high density, radiation tolerant, nonvolatile memories is critical for space applications. Ferroelectric memories, when fabricated with radiation hardened complementary metal oxide semiconductors (CMOS), can be manufactured and packaged to provide high density replacements for Flash memory, which is not radiation tolerant. Previous work showed ferroelectric memory cells to be resistant to single event upsets and proton irradiation, and ferroelectric storage capacitors to be resistant to neutron exposure. In addition to radiation hardness, the fast programming times, virtually unlimited endurance, and low voltage, low power operation make ferroelectric memories ideal for space missions. Previously, a commercial double level metal 64-kilobit ferroelectric memory was presented. Although the capabilities of radiation hardened wafer fabrication facilities lag behind those of the most modern commercial wafer fabrication facilities, several paths to achieving radiation tolerant, dense ferroelectric memories are emerging. Both short and long term solutions are presented in this paper. Although worldwide major semiconductor companies are introducing commercial ferroelectric memories, funding limitations must be overcome to proceed with the development of high density, radiation tolerant ferroelectric memories.
Low-dimensional ferroelectrics, ferrielectrics, and antiferroelectrics are of urgent scientific interest due to their unusual polar, piezoelectric, electrocaloric, and pyroelectric properties. The strain engineering and strain control of the ferroelectric properties of layered two-dimensional van der Waals materials, such as CuInP 2 (S,Se) 6 monolayers, thin films, and nanoflakes, are of fundamental interest and especially promising for their advanced applications in nanoscale nonvolatile memories, energy conversion and storage, nano-coolers, and sensors. Here, we study the polar, piezoelectric, electrocaloric, and pyroelectric properties of thin strained films of a ferrielectric CuInP 2 S 6 covered by semiconducting electrodes and reveal an unusually strong effect of a mismatch strain on these properties. In particular, the sign of the mismatch strain and its magnitude determine the complicated behavior of piezoelectric, electrocaloric, and pyroelectric responses. The strain effect on these properties is opposite, i.e., “anomalous,” in comparison with many other ferroelectric films, for which the out-of-plane remanent polarization, piezoelectric, electrocaloric, and pyroelectric responses increase strongly for tensile strains and decrease or vanish for compressive strains.
Complex oxide-based ferroelectric tunnel junctions (FTJs) show excellent nonvolatile memory characteristics promising for emerging technology. However, integration of these epitaxially grown FTJs electrically with a silicon substrate remains challenging due to their incompatible lattice structures and poor electronic interfaces resulting from the direct synthesis techniques. Here, we present an epitaxial SrRuO 3 /PbZr 0.2 Ti 0.8 O 3 /SrRuO 3 FTJ integrated electrically with a doped silicon substrate after a layer transfer process. The tunnel currents of the FTJ on silicon show a large tunneling electroresistance (~1×10 5 %) effect, which is explained by a numerical FTJ model incorporating pinned dipoles at the interfaces. This proof of concept of the integration of functional oxide heterostructures with silicon opens a pathway to beyond-CMOS computing devices using unconventional materials.
To fully exploit the ferroelectric field effect transistor (FeFET) as compact embedded nonvolatile memory for various computing and storage applications, it is desirable to use a single FeFET (1T) as a unit cell and arrange the cells into an array. However, many write mechanisms for an 1T FeFET array reported in the literature are yet to be validated experimentally. In this work, we performed a comprehensive experimental characterization on the write operations in an 1T- NOR and 1T- AND array using n-channel bulk FeFETs. We discovered that: 1) the source/drain contact can only supply minority carriers (i.e., electrons) to the channel for polarization screening during the low- V TH state programming; 2) the body contact can not only supply majority carriers (i.e., holes) for efficient high- V TH state write, but also depletion charge for low- V TH state programming, though with lower efficiency; and 3) during the low/high- V TH programming, only the path that can supply negative/positive screening charges, respectively, need to respond, which necessitates the application of proper write biases on the corresponding terminal. Based on the understanding of these write mechanisms, we show the importance of localized body contact or column-wise body contact for the successful high- V TH state programming. We also show that the previously proposed C- AND write scheme fails to program the FeFET to the low- V TH state for our devices. Finally, we propose several write schemes for both 1T- AND and 1T- NOR arrays for various scenarios providing insights for choosing the appropriate write scheme, which will facilitate the adoption of 1T FeFET memory arrays for emerging applications.
A novel electric pulse-induced resistive change (EPIR) effect has been found in thin film colossal magnetoresistive (CMR) materials, and has shown promise for the development of resistive, nonvolatile memory. The EPIR effect is induced by the application of low voltage (< 4 V) and short duration (< 20 ns) electrical pulses across a thin film sample of a CMR material at room temperature and under no applied magnetic field. The pulse can directly either increase or decrease the resistance of the thin film sample depending on pulse polarity. The sample resistance change has been shown to be over two orders of magnitude, and is nonvolatile after pulsing. The sample resistance can also be changed through multiple levels - as many as 50 have been shown. Such a device can provide a way for the development of a new kind of nonvolatile multiple-valued memory with high density, fast write/read speed, low power-consumption, and potential high radiation-hardness.
A solid-state, resistance tailorable, programmable-once, binary, nonvolatile memory switch based on manganese oxide thin films is reported. MnO(x) exhibits irreversible memory switching from conducting (on) to insulating (off) state, with the off and on resistance ratio of greater than 10,000. The switching mechanism is current-triggered chemical transformation of a conductive MnO(2-Delta) to an insulating Mn2O3 state. The energy required for switching is of the order of 4-20 nJ/sq micron. The low switching energy, stability of the on and off states, and tailorability of the on state resistance make these microswitches well suited as programmable binary synapses in electronic associative memories based on neural network models.
Increasing the memory density and utilizing the unique characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes the characterization of a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determinethe amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. This paper presents measurements of an actual prototype memory cell. This prototype is not a complete implementation of a device, but instead, a prototype of the storage and retrieval portion of an actual device. The performance of this prototype is presented with the projected performance of the overall device. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.
Increasing the memory density and utilizing the dove1 characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used as a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.
The figure shows a prototype of a relatively inexpensive electronic monitoring apparatus that measures and records selected parameters of lightning-induced transient voltages on communication and power cables. The selected parameters, listed below, are those most relevant to the ability of lightning-induced transients to damage electronic equipment. This apparatus bridges a gap between some traditional transient-voltage recorders that record complete waveforms and other traditional transient-voltage recorders that record only peak values: By recording the most relevant parameters and only those parameters this apparatus yields more useful information than does a traditional peak-value (only) recorder while imposing much smaller data-storage and data-transmission burdens than does a traditional complete-waveform recorder. Also, relative to a complete-waveform recorder, this apparatus is more reliable and can be built at lower cost because it contains fewer electronic components. The transients generated by sources other than lightning tend to have frequency components well below 1 MHz. Most commercial transient recorders can detect and record such transients, but cannot respond rapidly enough for recording lightning-induced transient voltage peaks, which can rise from 10 to 90 percent of maximum amplitude in a fraction of a microsecond. Moreover, commercial transient recorders cannot rearm themselves rapidly enough to respond to the multiple transients that occur within milliseconds of each other on some lightning strikes. One transient recorder, designed for Kennedy Space Center earlier [ Fast Transient-Voltage Recorder (KSC- 11991), NASA Tech Briefs, Vol. 23, No. 10, page 6a (October 1999)], is capable of sampling transient voltages at peak values up to 50 V in four channels at a rate of 20 MHz. That recorder contains a trigger circuit that continuously compares the amplitudes of the signals on four channels to a preset triggering threshold. When a trigger signal is received, a volatile memory is filled with data for a total time of 200 ms. After the data are transferred to nonvolatile memory, the recorder rearms itself within 400 ms to enable recording of subsequent transients. Unfortunately, the recorded data must be retrieved through a serial communication link. Depending on the amount of data recorded, the memory can be filled before retrieval is completed. Although large amounts of data are recorded and retrieved, only a small part of the information (the selected parameters) is usually required. The present transient-voltage recorder provides the required information, without incurring the overhead associated with the recording, storage, and retrieval of complete transient-waveform data. In operation, this apparatus processes transient voltage waveforms in real time to extract and record the selected parameters. An analog-to-digital converter that operates at a speed of as much as 100 mega-samples per second is used to sample a transient waveform. A real-time comparator and peak detector are implemented by use of fast field-programmable gate arrays.
Resistance switching in metal–insulator–metal structures has been extensively studied in recent years for use as synaptic elements for neuromorphic computing and as nonvolatile memory elements. However, high switching power requirements, device variabilities, and considerable trade-offs between low operating voltages, high on/off ratios, and low leakage have limited their utility. Here, we have addressed these issues by demonstrating the use of ultraporous dielectrics as a pathway for high-performance resistive memory devices. Using a modified atomic layer deposition based technique known as sequential infiltration synthesis, which was developed originally for improving polymer properties such as enhanced etch resistance of electron-beam resists and for the creation of films for filtration and oleophilic applications, we are able to create ~15 nm thick ultraporous (pore size ~5 nm) oxide dielectrics with up to 73% porosity as the medium for filament formation. We show, using the Ag/Al 2 O 3 system, that the ultraporous films result in ultrahigh on/off ratio (>10 9 ) at ultralow switching voltages (~±600 mV) that are 10× smaller than those for the bulk case. In addition, the devices demonstrate fast switching, pulsed endurance up to 1 million cycles. and high temperature (125 °C) retention up to 10 4 s, making this approach highly promising for large-scale neuromorphic and memory applications. Additionally, this synthesis methodology provides a compatible, inexpensive route that is scalable and compatible with existing semiconductor nanofabrication methods and materials.
Integrated nonvolatile read-write memory with addressing using variable threshold field effect transistor including cell operation, channel shielding and circuit
This report documents the efforts and results of the fiscal year (FY) 2010 NASA Electronic Parts and Packaging Program (NEPP) task for nonvolatile memory (NVM) reliability. This year's focus was to measure latency (read, program, and erase) of NAND Flash memories and determine how these parameters drift with erase/program/read endurance cycling.
The potential of memristive devices for applications in nonvolatile memory and neuromorphic computing has sparked considerable interest, particularly in exploring memristive effects in two-dimensional (2D) magnetic materials. However, the progress in developing nonvolatile, magnetic field-free memristive devices using 2D magnets has been limited. In this work, we report an electrostatic-gating-induced nonvolatile memristive effect in CrI 3 -based tunnel junctions. The few-layer CrI 3 -based tunnel junction manifests notable hysteresis in its tunneling resistance as a function of gate voltage. We further engineered a nonvolatile memristor using the CrI 3 tunneling junction with low writing power and at zero magnetic field. We show that the hysteretic transport observed is not a result of trivial effects or inherent magnetic properties of CrI 3 . We propose a potential association between the memristive effect and the newly predicted ferroelectricity in CrI 3 via gating-induced Jahn–Teller distortion. Furthermore, our work illuminates the potential of 2D magnets in developing next-generation advanced computing technologies.
This publication contains the proceedings for the Non-Volatile Memory Technology Symposium 2000 that was held on November 15-16, 2000 in Arlington, Virginia. The proceedings contains a wide range of papers that cover the presentations of myriad advances in the nonvolatile memory technology during the recent past including memory cell design, simulations, radiation environment, and emerging memory technologies. The papers presented in the proceedings address the design challenges and applications and deals with newer, emerging memory technologies as well as related issues of radiation environment and die packaging.