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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Mapping entry invalidation

A memory access system may include a first memory address translator, a second memory address translator and a mapping entry invalidator. The first memory address translator translates a first virtual address in a first protocol of a memory access request to a second virtual address in a second protocol and tracks memory access request completions. The second memory address translator is to translate the second virtual address to a physical address of a memory. The mapping entry invalidator requests invalidation of a first mapping entry of the first mapping address translator requests invalidation of a second mapping entry of the second memory address translator corresponding to the first mapping entry following invalidation of the first mapping entry and based upon the tracked memory access request completions.

Walker, Shawn K.↗
DOE OSTI2021

Dynamic voltage and frequency scaling based on memory channel slack

A processing system scales power to memory and memory channels based on identifying causes of stalls of threads of a wavefront. If the cause is other than an outstanding memory request, the processing system throttles power to the memory to save power. If the stall is due to memory stalls for a subset of the memory channels servicing memory access requests for threads of a wavefront, the processing system adjusts power of the memory channels servicing memory access request for the wavefront based on the subset. By boosting power to the subset of channels, the processing system enables the wavefront to complete processing more quickly, resulting in increased processing speed. Conversely, by throttling power to the remainder of channels, the processing system saves power without affecting processing speed.

Das, Shomit N.↗
DOE OSTI2022

Shape memory embolectomy devices and systems

An embolectomy device comprised of an expansion unit and a support unit is disclosed. The expansion unit can be actuated in response to one or more external stimuli, and the support unit, located proximately to the expansion unit, provides a force to hold the expansion unit in place and to further induce the expansion unit's radial expansion. The radial expansion of the expansion unit causes the expansion unit to physically contact a blood clot, enabling the blood clot to be removed. In some embodiments, the expansion unit can be fabricated from a shape memory polymer foam. In some embodiments the support unit can be fabricated from any elastic material including, without limitation, shape memory alloys.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2020

Understanding the Impact of Memory Access Patterns in Intel Processors

Because of increasing complexity in the memory hierarchy, predicting the performance of a given application in a given processor is becoming more difficult. The problem is worsened by the fact that the hardware needed to deal with more complex memory traffic also affects energy consumption. Moreover, in a heterogeneous system with shared main memory, the memory traffic between the last level cache (LLC) and the memory creates contention between other processors and accelerator devices. For these reasons, it is important to investigate and understand the impact of different memory access patterns on the memory system. This study investigates the interplay between Intel processors' memory hierarchy and different memory access patterns in applications. The authors explore sequential streaming and strided memory access patterns with the objective of predicting LLC-dynamic random access memory (DRAM) traffic for a given application in given Intel architectures. Moreover, the impact of prefetching is also investigated in this study. Experiments with different Intel micro-architectures uncover mechanisms to predict LLC-DRAM traffic that can yield up to 99% accuracy for sequential streaming access patterns and up to 95% accuracy for strided access patterns.

Alaul haque monil, Mohammad↗
DOE OSTI2024

Dynamic Control of Sodium Cold Trap Purification Temperature Using LSTM System Identification

This study investigates the dynamic regulation of the sodium cold trap purification temperature at Argonne National Laboratory’s liquid sodium test facility, employing long short-term memory (LSTM) system identification techniques. The investigation introduces an innovative hybrid approach by integrating model predictive control (MPC) based on first principles dynamic models with a multi-step time–frequency LSTM model in predicting the temperature profiles of a sodium cold trap purification system. The long short-term memory–model predictive controller (LSTM-MPC) model employs a sliding window scheme to gather training samples for multi-step prediction, leveraging historical data to construct predictive models that capture the non-linearities of the complex system dynamics without explicitly modeling the underlying physical processes. The performance of the LSTM-MPC and MPC were evaluated through simulation experiments, where both models were assessed on their capacity to maintain the cold trap temperature within predefined set-points while minimizing deviations and overshoots. Results obtained show how the data-driven LSTM-MPC model demonstrates stability and adaptability. In contrast, the traditional MPC model exhibits irregularities, particularly evident as overshoots around set-point limits, which can potentially compromise its effectiveness over long prediction time intervals. The findings obtained offer valuable insights into integrating data-driven techniques for enhancing real-time monitoring systems.

LSTM-MPC↗
DOE OSTI2023

Memory instruction for memory tiers

Various embodiments provide for one or more processor instructions and memory instructions that enable a memory sub-system to copy, move, or swap data across (e.g., between) different memory tiers of the memory sub-system, where each of the memory tiers is associated with different memory locations (e.g., different physical memory locations) on one or more memory devices of the memory sub-system.

Roberts, David Andrew↗
DOE OSTI2025

UltraLiM: In-Memory Boolean Logic Architecture Using UltraRAM

Conventional computing architectures encounter ‘von Neumann’ and ‘memory wall’ bottlenecks which arise due to the back-and-forth data movement between the physically separate memory and processing units and the speed mismatch between them, respectively. These bottlenecks hurt both energy efficiency and the throughput of computing systems. To address these challenges, in-memory computing architectures have emerged as a promising alternative. They reduce the need for frequent data movement by executing different computing tasks inside the memory system. Here, we present UltraLiM, a logic-in-memory architecture using the UltraRAM-based memory system. UltraRAM holds the promise of developing a ‘universal memory’, overcoming the limitations of charge-based memories thanks to their non-volatile behavior with lower operating voltage. This work presents an in-memory computing architecture that integrates an UltraRAM-based memory array with a custom-designed peripheral circuitry. With this architecture, we can perform various in-memory Boolean logic operations (such as NOT, NAND, NOR, and XOR) in a single cycle. Leveraging the separate read-write paths in the UltraRAM-based memory array, we optimize read operations without encountering design conflicts. This optimization enhances the sense margin, enabling the use of simpler peripheral circuitry for in-memory logic operations.

Alam, Shamiul [University of Tennessee, Knoxville ↗
DOE OSTI2022

Register-Like Storage Block Used as Histograms, Cluster Buffers, and Hough Transform Accumulators for HEP Trigger Systems

In high energy physics experiment trigger systems, block memories are utilized for various purposes, especially in binned searching algorithms. In these algorithms, the storages are demanded to perform like a large set of registers. The writing and reading operation must be performed in single clock cycle and once an event is processed, the memory must be globally reset. These demands can be fulfilled with registers but the cost of using registers for large memory is unaffordable. Another common requirement is the boundary coverage feature during reading process. Additionally, when a memory bin is addressed, the stored contents in the addressed bin and its neighboring bin must be output simultaneously. In this paper, a register-like block storage design scheme is described, which allows updating memory locations in single clock cycle, reading two adjacent bins, and effectively refreshing entire memory within a single clock. The implementation and test results are presented.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

Quality of service for input/output memory management unit

A data processing system includes a memory, a group of input/output (I/O) devices, an input/output memory management unit (IOMMU). The IOMMU is connected to the memory and adapted to allocate a hardware resource from among a group of hardware resources to receive an address translation request for a memory access from an I/O device. The IOMMU detects address translation requests from the plurality of I/O devices. The IOMMU reorders the address translation requests such that an order of dispatching an address translation request is based on a policy associated with the I/O device that is requesting the memory access. The IOMMU selectively allocates a hardware resource to the input/output device, based on the policy that is associated with the I/O device in response to the reordering.

Basu, Arkaprava↗
DOE OSTI2022

Sharing tuples across independent coordination namespace systems

A system and method for federating a tuple storage database across multiple coordinated namespace (CNS) extended memory storage systems allowing the sharing of tuples and tuple data across independent systems. The method provides a federation service for multiple coordination namespace systems. The method retrieves a tuple from connected independent CNS systems wherein a local CNS Controller sends a read request to the local gatekeeper to retrieve a first tuple and creates a local pending remote record. The local gatekeeper at a requesting node sends a broadcast query to a plurality of remote gatekeepers for the tuple and Remote gatekeepers at remote nodes query in its local CNS for the tuple. The Local gatekeeper process at the requesting node receives results from a plurality of remote gatekeepers for the said tuple and selects one remote gatekeeper to receive the requested tuple and broadcasts a read for tuple data with selected gatekeeper.

Jacob, Philip↗
DOE OSTI2022

Interlinked tuples in coordination namespace

A system and method for supporting tuple record interlinking in one or more tuple space/coordinated namespace (CNS) extended memory storage systems. A system-wide CNS provides for efficient storing and communicating of data generated by local processes running at the nodes, and coordinated to generate a union/intersection of multiple CNS where tuple records are interlinked in multiple CNS hashtables, and/or share tuple data between two sets of processes that are part of different CNSs. Local node processes further generate multi-key tuples where two or more tuple records are interlinked within the same CNS hash table, thereby permitting a look up of the tuple data by either tuple name/keys. A CNS controller further provides a tuple iterator for a key-value storage in a CNS system that adds more links between tuples enables creation of iterator structures such as linked list or trees etc. of “different” tuples in a tuple database.

Jacob, Philip↗
DOE OSTI2025

Curvature Memory in Electrically Stimulated Lipid Membranes

Here, we demonstrate, using non-equilibrium molecular dynamics simulations, that lipid membrane capacitance varies with surface charge accumulation linked to membrane shape and curvature changes. Specifically, we show that lipid membranes exhibit a hysteretic response when exposed to oscillatory electric fields. The electromechanical coupling in these membranes leads to hysteretic buckling, in which the membrane can spontaneously buckle in one of two distinct directions along the electric field, even for the same ionic charge accumulation at the water–membrane interface. In this regard, these binary buckled membrane states suggest potential applications in neuromorphic computing. Their bistable nature, characterized by two distinct and stable configurations, could serve as a foundation for implementing memory storage systems and logic operations. Furthermore, we introduce a circuit model that captures these dynamic effects, offering insights into emergent memory effects in electrically stimulated lipid membranes. Finally, this work presents lipid bilayers as dynamic, adaptable elements and suggests a new platform for exploring energy storage, information processing, and memory encoding at the lipid membrane level.

59 BASIC BIOLOGICAL SCIENCES↗
DOE OSTI2024

Low Power, Radiation Resilient Synchronous Edge Processing for Remote Monitoring

Next-generation space remote sensing systems may be equipped with imaging arrays that sense data at a rate that outstrips the processing capability of any computing hardware that can operate within a satellite’s power budget. This project developed novel convolutional and recurrent neural networks to detect and estimate point-like events amid clutter, and investigated their efficient and accurate implementation on analog in-memory computing systems that are 10-1000× more energy-efficient than digital processors. This project leveraged two memory devices at different levels of technological maturity: a large-scale analog computing prototype using commercial SONOS charge-trap memory, and electrochemical memory (ECRAM) with intrinsic radiation hardness. We experimentally demonstrated end-to-end analog processing of our neural networks on SONOS and characterized the radiation response of both SONOS and ECRAM. We advanced the state-of-the-art in ECRAM precision and reliability, and developed co-design methods to enable accurate long-term operation of SONOS analog accelerators in space radiation environments.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2026

Memorial Pools Energy Efficiency Retrofits

The National September 11 Memorial & Museum completed a retrofit of the submergible LED lighting fixtures in its North and South Memorial Pools, located at the World Trade Center site in New York City. The two one-acre pools are illuminated nightly by custom LED fixtures set into their base, and the original lights — in place since 2011 — had begun reaching the end of their useful life, leaving sections of the pools dim or dark. Rather than fully replacing the fixtures, the project team worked with the original manufacturer, Acuity Brands, to retrofit and reuse existing components across all eight pool walls (34 fixtures per wall), reducing cost and waste. Fixtures were shipped in custom crates to Minnesota for retrofitting, then reinstalled onsite by Memorial & Museum staff and contractor ABM. The team addressed two key technical challenges during the project: early leakage in retrofitted fixtures, resolved by introducing vacuum-sealing and nitrogen-fill testing before shipment; and chord damage during transit, resolved with custom-designed shipping crates. All eight pool walls were successfully retrofitted and reinstalled by August 27, 2025, ahead of the 25th anniversary of the September 11, 2001 attacks. Sitewide electrical consumption in September 2025 reflected an approximate 7% reduction, contributing to the institution's broader net-zero and LEED Gold sustainability goals.

29 ENERGY PLANNING, POLICY, AND ECONOMY↗
DOE OSTI2023

Data migration schedule prediction using machine learning

Various embodiments provide for one or more processor instructions and memory instructions that enable a memory sub-system to predict a schedule for migrating data between memory devices, which can be part of a memory sub-system.

Roberts, David Andrew↗