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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4

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NASA NTRS1989

Test aspects of the JPL Viterbi decoder

The generation of test vectors and design-for-test aspects of the Jet Propulsion Laboratory (JPL) Very Large Scale Integration (VLSI) Viterbi decoder chip is discussed. Each processor integrated circuit (IC) contains over 20,000 gates. To achieve a high degree of testability, a scan architecture is employed. The logic has been partitioned so that very few test vectors are required to test the entire chip. In addition, since several blocks of logic are replicated numerous times on this chip, test vectors need only be generated for each block, rather than for the entire circuit. These unique blocks of logic have been identified and test sets generated for them. The approach employed for testing was to use pseudo-exhaustive test vectors whenever feasible. That is, each cone of logid is tested exhaustively. Using this approach, no detailed logic design or fault model is required. All faults which modify the function of a block of combinational logic are detected, such as all irredundant single and multiple stuck-at faults.

Breuer, M. A.↗

DOE OSTI2023

Human-Building Collaboration: Toward lighting enabled collaborative system design

The profession of lighting design is evolving as contemporary lighting systems increasingly rely on cutting-edge computational technologies, sensors, and IOT systems. This trend requires designers to incorporate ideas of automation, dynamic controls, and user-system interaction into their design logic. However, real-time lighting simulations are constrained by inherent limitations arising from the reductive assumptions inevitably introduced in simulated lighting environments. This raises the question of how can designers account for the discrepancies between simulated and real lighting environments, and how can collaboration between humans and autonomous lighting systems bridge this gap. To address this question, we propose a protocol for designing collaborative interactions between humans and systems. Furthermore, this protocol builds on the Human-Lighting System Interaction Framework and demonstrates how human and system intelligence can be combined to fine-tune lighting qualities in a given space. Our paper shows how interactive lighting systems can customize lighting based on user preferences in real-time and how global lighting configurations can be adjusted over time. Specifically, we demonstrate: a) Human-system collaboration assumptions and goals, as well as how the protocol can be integrated into digitally programmable lighting systems. b) Implementations of collaboration that reveal how system autonomy, performance, and user experience are improved over short and long-term timeframes. c) How lighting design can be enhanced beyond simulation-driven design optimization capacities. The associated affordances and limitations are discussed with respect to existing lighting simulation design frameworks.

autonomous systems↗

NASA NTRS1980

F100 multivariable control synthesis program: A review of full scale engine altitude tests

The benefits of linear quadratic regulator synthesis methods in designing a multivariable engine control capable of operating an engine throughout its flight envelope were demonstrated. The entire multivariable control synthesis program is reviewed with particular emphasis on engine tests conducted in the NASA Lewis propulsion systems laboratory altitude facility. The multivariable control has basically a proportional plus integral, model following structure with gains scheduled as functions of flight condition. The multivariable control logic design is described, along with control computer implementation aspects. Altitude tests demonstrated that the multivariable control logic could control an engine over a wide range of test conditions. Representative transient responses are presented to demonstrate engine behavior and the functioning of the control logic.

Lehtinen, B.↗

NASA NTRS2007

Assurance of Complex Electronics. What Path Do We Take?

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled in software, such as communication protocols. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of "software-like" bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and "bugs" can be detected earlier in the development cycle, thus creating a development process for CE that will be easily maintained and configurable based on the device used.

FROM↗

NASA NTRS2007

Software Process Assurance for Complex Electronics

Complex Electronics (CE) now perform tasks that were previously handled in software, such as communication protocols. Many methods used to develop software bare a close resemblance to CE development. Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. With CE devices obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that used standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques were used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that was more easily maintained, consistent and configurable based on the device used.

Plastow, Richard A.↗

NASA NTRS2007

Software Process Assurance for Complex Electronics (SPACE)

Complex Electronics (CE) are now programmed to perform tasks that were previously handled in software, such as communication protocols. Many of the methods used to develop software bare a close resemblance to CE development. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that looks at using standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques can be used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that will be more easily maintained, consistent and configurable based on the device used.

Plastow, Richard A.↗

DOE OSTI2020

SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators

Next generation systems, such as edge devices, will have to provide efficient processing of machine learning (ML) algorithms along several metrics, including energy, performance, area, and latency. However, the quickly evolving field of ML makes it extremely difficult to generate accelerators able to support a wide variety of algorithms. At the same time, designing accelerators in hardware description languages (HDLs) by hand is hard and time consuming, and does not allow quick exploration of the design space. This paper discusses the SODA synthesizer, an automated open source high-level ML framework-to-Verilog compiler targeting ML Application-Specific Integrated Circuits (ASICs) chiplets based on the LLVM infrastructure. The SODA synthesizers will allow implementing optimal designs by combining templated and fully tunable IPs and macros, and fully custom components generated through high-level synthesis. All these components will be provided through an extendable resource library, characterized with both commercial and open source logic design flows. Through a closed loop design space exploration engine, developers will be able to quickly explore their hardware designs along different dimension

Minutoli, Marco↗

NASA NTRS1982

LSI/VLSI design for testability analysis and general approach

The incorporation of testability characteristics into large scale digital design is not only necessary for, but also pertinent to effective device testing and enhancement of device reliability. There are at least three major DFT techniques, namely, the self checking, the LSSD, and the partitioning techniques, each of which can be incorporated into a logic design to achieve a specific set of testability and reliability requirements. Detailed analysis of the design theory, implementation, fault coverage, hardware requirements, application limitations, etc., of each of these techniques are also presented.

Lam, A. Y.↗

NASA NTRS2007

Filling the Assurance Gap on Complex Electronics

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled by software, such as communication protocols. For example, the James Webb Space Telescope will use Field Programmable Gate Arrays (FPGAs), which can have over a million logic gates, to send telemetry. System-on-chip (SoC) devices, another type of complex electronics, can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, mature software methodologies have been proposed, with slight modifications, to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and bugs can be detected earlier in the development cycle, thus creating a development process for CE that can be easily maintained and configurable based on the device used.

Plastow, Richard A.↗

NASA NTRS2013

Remote Memory Access Protocol Target Node Intellectual Property

The MagnetoSpheric Multiscale (MMS) mission had a requirement to use the Remote Memory Access Protocol (RMAP) over its SpaceWire network. At the time, no known intellectual property (IP) cores were available for purchase. Additionally, MMS preferred to implement the RMAP functionality with control over the low-level details of the design. For example, not all the RMAP standard functionality was needed, and it was desired to implement only the portions of the RMAP protocol that were needed. RMAP functionality had been previously implemented in commercial off-the-shelf (COTS) products, but the IP core was not available for purchase. The RMAP Target IP core is a VHDL (VHSIC Hardware Description Language description of a digital logic design suitable for implementation in an FPGA (field-programmable gate array) or ASIC (application-specific integrated circuit) that parses SpaceWire packets that conform to the RMAP standard. The RMAP packet protocol allows a network host to access and control a target device using address mapping. This capability allows SpaceWire devices to be managed in a standardized way that simplifies the hardware design of the device, as well as the development of the software that controls the device. The RMAP Target IP core has some features that are unique and not specified in the RMAP standard. One such feature is the ability to automatically abort transactions if the back-end logic does not respond to read/write requests within a predefined time. When a request times out, the RMAP Target IP core automatically retracts the request and returns a command response with an appropriate status in the response packet s header. Another such feature is the ability to control the SpaceWire node or router using RMAP transactions in the extended address range. This allows the SpaceWire network host to manage the SpaceWire network elements using RMAP packets, which reduces the number of protocols that the network host needs to support.

Haddad, Omar↗

NASA NTRS1994

Design document for the MOODS Data Management System (MDMS), version 1.0

The MOODS Data Management System (MDMS) provides access to the Master Oceanographic Observation Data Set (MOODS) which is maintained by the Naval Oceanographic Office (NAVOCEANO). The MDMS incorporates database technology in providing seamless access to parameter (temperature, salinity, soundspeed) vs. depth observational profile data. The MDMS is an interactive software application with a graphical user interface (GUI) that supports user control of MDMS functional capabilities. The purpose of this document is to define and describe the structural framework and logical design of the software components/units which are integrated into the major computer software configuration item (CSCI) identified as MDMS, Version 1.0. The preliminary design is based on functional specifications and requirements identified in the governing Statement of Work prepared by the Naval Oceanographic Office (NAVOCEANO) and distributed as a request for proposal by the National Aeronautics and Space Administration (NASA).

Source record↗

NASA NTRS2009

Economical Implementation of a Filter Engine in an FPGA

A logic design has been conceived for a field-programmable gate array (FPGA) that would implement a complex system of multiple digital state-space filters. The main innovative aspect of this design lies in providing for reuse of parts of the FPGA hardware to perform different parts of the filter computations at different times, in such a manner as to enable the timely performance of all required computations in the face of limitations on available FPGA hardware resources. The implementation of the digital state-space filter involves matrix vector multiplications, which, in the absence of the present innovation, would ordinarily necessitate some multiplexing of vector elements and/or routing of data flows along multiple paths. The design concept calls for implementing vector registers as shift registers to simplify operand access to multipliers and accumulators, obviating both multiplexing and routing of data along multiple paths. Each vector register would be reused for different parts of a calculation. Outputs would always be drawn from the same register, and inputs would always be loaded into the same register. A simple state machine would control each filter. The output of a given filter would be passed to the next filter, accompanied by a "valid" signal, which would start the state machine of the next filter. Multiple filter modules would share a multiplication/accumulation arithmetic unit. The filter computations would be timed by use of a clock having a frequency high enough, relative to the input and output data rate, to provide enough cycles for matrix and vector arithmetic operations. This design concept could prove beneficial in numerous applications in which digital filters are used and/or vectors are multiplied by coefficient matrices. Examples of such applications include general signal processing, filtering of signals in control systems, processing of geophysical measurements, and medical imaging. For these and other applications, it could be advantageous to combine compact FPGA digital filter implementations with other application-specific logic implementations on single integrated-circuit chips. An FPGA could readily be tailored to implement a variety of filters because the filter coefficients would be loaded into memory at startup.

Kowalski, James E.↗

NASA NTRS1984

Mod-5A wind turbine generator program design report. Volume 4: Drawings and specifications, book 4

The design, development and analysis of the 7.3 MW MOD-5A wind turbine generator are documented. There are four volumes. This volume contains the drawings and specifications that were developed in preparation for building the MOD-5A wind turbine generator. This volume contains 5 books of which this is the fourth, providing drawings 47A380128 through 47A387125. In addition to the parts listing and where-used list, the logic design of the controller software and the code listing of the controller software are provided. Also given are the aerodynamic profile coordinates.

Source record↗

NASA NTRS1977

Evaluation of structural design concepts for an arrow-wing supersonic cruise aircraft

An analytical study was performed to determine the best structural approach for design of primary wing and fuselage structure of a Mach 2.7 arrow wing supersonic cruise aircraft. Concepts were evaluated considering near term start of design. Emphasis was placed on the complex interactions between thermal stress, static aeroelasticity, flutter, fatigue and fail safe design, static and dynamic loads, and the effects of variations in structural arrangements, concepts and materials on these interactions. Results indicate that a hybrid wing structure incorporating low profile convex beaded and honeycomb sandwich surface panels of titanium alloy 6Al-4V were the most efficient. The substructure includes titanium alloy spar caps reinforced with boron polyimide composites. The fuselage shell consists of hat stiffened skin and frame construction of titanium alloy 6Al-4V. A summary of the study effort is presented, and a discussion of the overall logic, design philosophy and interaction between the analytical methods for supersonic cruise aircraft design are included.

Sakata, I. F.↗

NASA NTRS1975

Design study of structural concepts for an arrow-wing supersonic-cruise aircraft

An analytical study was performed to determine the best structural approach for design of primary wing and fuselage structure of a Mach number 2.7 arrow-wing supersonic cruise aircraft. Concepts were evaluated considering near-term start-of-design. Emphasis was placed on the complex interactions between thermal stress, static aeroelasticity, flutter, fatigue and fail-safe design, static and dynamic loads, and the effects of variations in structural arrangements, concepts and materials on these interactions. Results indicate that a hybrid wing structure incorporating low-profile convex-beaded and honeycomb sandwich surface panels of titanium alloy 6Al-4V were the most efficient. The substructure includes titanium alloy spar caps reinforced with Boron-polyimide composites. The fuselage shell is a closed-hat stiffened skin and frame construction of titanium alloy 6Al-4V. This paper presents an executive summary of the study effort, and includes a discussion of the overall study logic, design philosophy and interaction between the analytical methods for supersonic cruise aircraft design.

Sakata, I. F.↗

DOE OSTI2022

Practical guide to understanding goodness-of-fit metrics used in chemical state modeling of x-ray photoelectron spectroscopy data by synthetic line shapes using nylon as an example

Chemical state analysis of a sample surface through fitting bell-shaped curves to x-ray photoelectron spectroscopic polymer data is reviewed using nylon to introduce and discuss aspects of data analysis. Different strategies for modeling chemistry in nylon spectra are presented and in so doing, a case is made to include in published science the design logic and implementation in terms of line shapes and optimization parameter constraints between components in a peak model. Imperfections in line shape relative to the true shape for photoemission lines, when compensated for using constraints to optimization parameters, are shown to provide chemical state information about a sample that justify, for peak models constructed with these limitations, metrics for goodness-of-fit different from those expected for pulse-counted data.

Materials Science↗

DOE OSTI2024

5G Energy FRAME Report on 5G for Grid Use Case (Year 3 Final Report)

This report provides an extensive overview of the interrelationships among energy, communication, and computing—especially in the context of decarbonization goals, challenges, and opportunities. Technical examples enabled by 5G technologies and their performance are presented, discussed, based on the experiment performed at Pacific Northwest National Laboratory. This is the first use case focused on using 5G for the U.S. power grid and will be referred to as the 5G for Grid Use Case from here on. Specifically, this use case looks at the workflow, which integrates the performance data of a real-world 5G communication testbed and a grid transmission and distribution co-simulation platform. The cross-domain information flow and logic design are illustrated with a combination of power grid contingencies and events. Lastly, a summary of the project achievement and outcome is provided, along with a technology roadmap envisioned by the project team.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2026

Evaluation of Real-Time Mitigation Techniques forCyber Security in IEC 61850 / IEC 62351Substations

This paper presents the design logic and implementation aspects of three potential real-time mitigation techniques capable of countering GOOSE-based attacks: (i) IEC 62351-compliant message authentication code (MAC) scheme, (ii) a semantics-enforced rule- based intrusion detection system (IDS), and (iii) a hybrid approach integrating both MAC verification and Intrusion Detection System (IDS). A comparative evaluation of these real-time mitigation approaches is conducted using a cyber-physical system(CPS) security testbed. The results show that the hybrid integration significantly enhances mitigation capability. Furthermore, the processing delays of all three methods remain within the strict delivery requirements of GOOSE communication. The study also identifies limitations that none of the techniques can fully address, highlighting areas for future work.

Liu, Chen-Ching [Virginia Polytechnic Inst. and St↗