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At least 73 records · Page 4

All sources NASA NTRS DOE OSTI

DOE OSTI2024

A full-scope, high-fidelity simulator-based hardware-in-the-loop testbed for comprehensive nuclear power plant cybersecurity research

Nuclear power plant (NPP) cybersecurity research often relies on hardware-in-the-loop (HIL) testbeds that integrate real hardware components into simulated environments. These testbeds allow researchers to identify vulnerabilities, evaluate attack impacts, and test security measures in a controlled setting. Furthermore, previous HIL testbeds lacked fidelity to accurately represent real nuclear systems, limiting the scope of cybersecurity analysis. This study presents the creation of a HIL testbed, devised upon a full-scope, high-fidelity NPP simulator, to facilitate realistic and comprehensive cybersecurity research. To demonstrate its capabilities, the control logic for the steam generator water level was migrated from the simulator to an external programmable logic controller. As a practical application of the developed testbed, supply chain attack scenarios were simulated by injecting malicious code into the controller logic, and the effects of manipulating sensor inputs and control commands were observed. While this HIL testbed provides more detailed simulations, enhanced realism, and wider applicability compared to other options utilizing a less complex simulator, it is also more intricate and costly. For this reason, we include a detailed comparison with some alternative architectures to aid fellow researchers and practitioners in the selection of a suitable HIL architecture based on specific research objectives.

47 OTHER INSTRUMENTATION↗

DOE OSTI2026

Magnon confinement in epitaxial antiferromagnetic oxide heterostructures.

Magnons, the quanta of spin waves, have been extensively studied in a range of materials for spintronics, particularly for non-volatile logic-in-memory devices. Controlling magnons in conventional antiferromagnets and harnessing them in practical applications, however, remains a challenge. Here, we demonstrate highly efficient magnon transport in a LaFeO3/ BiFeO3/ LaFeO3 all-antiferromagnetic system, which can be controlled electrically, making it highly desirable for energy-efficient computation. Leveraging spin-orbit-driven spin-charge transduction, we demonstrate that this material architecture permits magnon confinement in ultrathin antiferromagnets, enhancing the output voltage generated by magnon transport by several orders of magnitude, which provides a pathway to enable magnetoelectric memory and logic functionalities. Additionally, the non-volatility of output voltage enables ultralowpower logic-in-memory processing, where magnonic devices can be efficiently reconfigured via electrically controlled magnon spin currents within magnetoelectric channels.

Husain, Sajid↗

DOE OSTI2025

A 28 nm multiply-accumulate ASIC architecture for on-chip data compression in MHz frame rate X-ray and electron pixel detectors

Modern X-ray detector systems urgently require compact, efficient, and fast data compression schemes to handle the transmission of big data from pixel arrays, enabling frame rates in the MHz regime. Here, in this work, a data compression ASIC that implements a streaming fixed-length lossy compression scheme is introduced and analyzed, proving the feasibility and benefits of on-chip compression. The compression scheme utilizes a vector matrix product logic, which performs a number of floating-point multiplications, additions, and accumulations. The logic is verified, synthesized, and shown to fit in the area resource available for the X-ray detector under study, which comprises 192 × 168 pixels each of 12-bit width, and having a total area of 20 mm× 20 mm, about 2 mm× 20 mm of which are available for the digital logic. Several system architectures, precisions, and compression ratios ranging from 100 to 250 were analyzed to pave the way for on-chip fixed-length compression (e.g., principal component analysis, singular value decomposition) and data reduction (e.g., azimuthal integration) for X-ray and electron detectors.

Data compression↗

DOE OSTI2026

Fault-tolerant resource comparison of qudit and qubit encodings for diagonal quadratic operators

Finite local Hilbert-space truncations arise naturally in quantum simulations of lattice field theories and motivate qudit encodings, but their fault-tolerant advantage over qubit encodings remains unclear. We compare the non-Clifford cost of implementing quadratic diagonal evolutions, exemplified by 𝑈 = 𝑒$^{−𝑖⁢𝑡⁢𝜙^2_𝑥}$ in a uniform field-amplitude discretization of a real scalar field, using either one logical 𝑑-level qudit or 𝑛 𝑏 = ⌈log 2⁡ 𝑑⌉ logical qubits. We analyze two standard settings: product-formula simulation and linear combination of unitaries (LCU) per block encoding, taking the resource metric to be the number of non-Clifford gates after synthesis into a discrete logical gate set. Because tight synthesis bounds for general single-qudit rotations are not known, we express the qudit constructions in terms of embedded two-level SU⁡(2) rotations and derive explicit finite-𝑑 break-even conditions for their synthesis cost; these serve as compiler targets for when qudit encodings can outperform the qubit baseline. Within the constructive models studied here, product-formula implementations would require an exponentially stronger per-primitive synthesis advantage for qudits to win asymptotically, while in the LCU setting the qubit encoding is asymptotically cheaper in 𝑑. Nevertheless, the finite-𝑑 threshold analysis identifies low-dimensional regions in which qudits can yield meaningful constant-factor savings, particularly for LCU-based implementations. As a secondary analysis of the LCU construction, we use an idealized negligible-overhead qubit-qudit code-switching model to give an absolute 𝑇-count comparison and reinterpret the savings as an allowable per-switch overhead budget.

Godwood, Samuel [Univ. of Liverpool (United Kingdo↗

DOE OSTI2024

Single-shot quantum error correction in intertwined toric codes

We construct a subsystem code in three dimensions that exhibits single-shot error correction in a user-friendly and transparent way. As this code is a subsystem version of coupled toric codes, we call it the intertwined toric code (ITC). Although previous codes share the property of single-shot error correction, the ITC is distinguished by its physically motivated origin, geometrically straightforward logical operators and errors, and a simple phase diagram. The code arises from three-dimensional (3D) stabilizer toric codes in a way that emphasizes the physical origin of the single-shot property. In particular, starting with two copies of the 3D toric code, we add check operators that provide for the confinement of pointlike excitations without condensing the loop excitations. Geometrically, the bare and dressed logical operators in the ITC derive from logical operators in the underlying toric codes, creating a clear relationship between errors and measurement outcomes. The syndromes of the ITC resemble the syndromes of the single-shot code by Kubica and Vasmer, allowing us to use their decoding schemes. We also extract the phase diagram corresponding to ITC and show that it contains the phases found in the Kubica-Vasmer code. Lastly, we suggest various connections to Walker-Wang models and measurement-based quantum computation.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

DOE OSTI2025

Fault-tolerant optical interconnects for neutral-atom arrays

We analyze the use of photonic links to enable large-scale fault-tolerant connectivity of locally error-corrected modules based on neutral atom arrays. Our approach makes use of recent theoretical results showing the robustness of surface codes to boundary noise and combines recent experimental advances in atom-array quantum computing with logical qubits with optical quantum networking techniques. We find the conditions for fault tolerance can be achieved with local two-qubit Rydberg gate and nonlocal Bell-pair errors below 1% and 10%, respectively, without requiring distillation or space-time overheads. Realizing the interconnects with a lens, a single optical cavity, or an array of cavities enables—with sufficient multiplexing—a Bell-pair generation rate in the 1–50 MHz range. When directly interfacing logical qubits, this rate translates to error-correction cycles in the 25–2000 kHz range, satisfying all requirements for fault tolerance and in the upper range fast enough for 100 kHz logical clock cycles. Published by the American Physical Society 2025

Sinclair, Josiah (ORCID:0000000215238295)↗

DOE OSTI2024

Maximum Switching Throughput Density Estimator

SAND2024-11125O The Maximum Switching Throughput Density Estimator software performs a simple analysis that estimates the maximum logic switching throughput density that’s achieved in various CMOS technology nodes on the International Roadmap for Devices and Systems. This software utilizes simple device models and optimization techniques, performing a simple sweep over a range of possible logic supply voltages, and analytically calculating the maximum switching frequency for the given logic voltage that meets the power density constraint. It does this by using simple models of power dissipation in conventional and fully adiabatic switching. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525.

Frank, Michael↗

DOE OSTI2024

Model of Inverter-Based Resources

Blackbox modelling for SC analysis is a possible solution. Accuracy can be acceptable even without having vendor control diagrams. Is an NDA required to share a vendor Blackbox model for SC analysis? Differences in VRT detection and injection logics. Angle rotation is not addressed in control logics of most vendors. Current limitation logic during unbalanced faults is not clear. Model IBR as a current source with shunt to improve convergence

IBRs, Model of IBRs, Short Circuit Analysis, Class↗

DOE OSTI2024

Integrate Latimer Controls' Solution into RTAC (CRADA Final Report, CRD-23-24672)

Latimer Controls, Inc. was awarded two vouchers under the Department of Energy's American-Made Solar Prize Round 6 to conduct collaborative research at a national laboratory. The National Renewable Energy Laboratory (NREL) was selected as a partner to assist Latimer Controls in the performance evaluation of its photovoltaic (PV) control software. This collaboration focuses on developing a hardware-in-the-loop (HIL) testbed at NREL, which will be used to test and validate the Latimer PV control technology in a realistic yet de-risked environment. Both Latimer and NREL teams will work together to analyze the collected test data, derive insights, and disseminate the scientific findings. Recent studies underscore the potential of solar energy as a zero-marginal-cost and zero-emission flexibility resource within the bulk power system, particularly when integrated with advanced control systems. To enhance the performance of such systems, Latimer Controls has developed leading-edge technologies, including machine learning (ML) algorithms and hierarchical inverter set-point allocation methods. These innovations are designed to estimate the operational headroom of large PV plants for grid integration and control. However, comprehensive validation under real-world conditions remains necessary. To address this gap, the concurrent CRADA project proposes the real-world application and validation of the Latimer Control solution within a HIL environment. Initially, the Latimer algorithm was developed and tested within MATLAB Simulink, a platform suitable for research-level simulations and iterative development. However, transitioning this technology to a real solar site as an industry-ready solution necessitates implementation in a format compatible with widely used solar power plant controllers. In this additional CRADA work, the MATLAB Simulink-based logic will be translated into Structured Text, a programming language compliant with IEC 61131 standards, which is commonly used for custom logic implementations in industry-leading programmable logic controllers (PLCs), such as the Schweitzer SEL real-time automation controller (RTAC). This transition will facilitate the deployment of the Latimer Control solution in real-world solar power plants, thereby advancing the technology towards commercialization.

14 SOLAR ENERGY↗

DOE OSTI2025

Terra-Populus v0.1: A Python Library for LandScan High-Definition Population Analysis and Modeling

The terra-populus library is designed for use by the LandScan HD technical team, offering a streamlined set of tools for generating and updating LandScan HD datasets from foundational building-level data, referred to as 'molecules,' provided by the building-level attribution team. This document serves as the primary technical documentation for terra-populus. Version 0.1 of the library includes the core modeling components necessary for LandScan HD production. It enables the generation of the LandScan HD Baseline dataset as well as corresponding confidence measures for the occupancy rates used. Parameters have been included for incorporating damaged building indicators and changes in population, to faciliate the creation of rapid updates for LandScan HD. Future iterations of terra-populus will introduce tools for creating a confidence index, and quantifying and propagating uncertainty, facilitating the creation of probabilistic LandScan HD outputs. This report provides an overview of the tools available in the library and the corresponding code implementations. One of the key advancements implemented in terra-populus is a redefinition of the atomic modeling unit for LandScan HD. Traditionally, the LandScan HD vector analytical framework has generated population estimates at the building sub-component (molecule) level. However, terra-populus adopts a building-level modeling approach. This shift is an operational decision aimed at aligning LandScan HD outputs with confidence measures, which are computed and validated at the building level (confidence measures are not included in this version of terra-populus, aside from those associated with the occupancy rates). Additional advancements to the LandScan HD modeling, as implemented by terra-populus, include a minimum population value parameter and an auto assignment of building floor counts. The population minimum value was implemented to prevent buildings and subsequent LandScan HD pixels that contained small values that may not rasterize in production. An 'auto' value has been included as a method for dealing with buildings lacking floor count information, where it is the average floor count of all other buildings with a residential building use type tag. The logic behind this is to remain consistent with the current logic employed for dealing with building use type null instances, where a null use type is defaulted to residential since it is the most common building type. The auto logic is intended to apply the most common building floor count of the most common type of buildings. The tools provided in terra-populus represent a significant step forward in improving the efficiency, reproducibility, and transparency of the LandScan HD modeling process. As the library evolves, it will continue to serve as a foundational resource for high-resolution population modeling.

96 KNOWLEDGE MANAGEMENT AND PRESERVATION↗

DOE OSTI2026

Digital Grid Twin–Direct Communication Scheme Test Bed for Assessing Relay-to-Relay Radio Antenna and Optical Fiber Performance and Misoperations

This study introduces a novel “Digital Grid Twin–Direct Communication Scheme” test bed. This advanced platform evaluates point-to-point communication between transmitter and receiver relays with optical fiber and radio omnidirectional antenna systems, implemented at the Advanced Protection lab in the Grid Research Innovation and Development Center at Oak Ridge National Laboratory. The increased diversity of energy sources has led to more protective relay misoperations. In North America, microgrid protection schemes now use point-to-point communication along distribution lines between relays to implement advanced logic in nonradial grids that include both high- and low-inertia generators. This trend challenges utilities to minimize misoperations while ensuring rapid fault clearance and accurate selectivity coordination between primary and backup relays. This study assesses relay-to-relay communication schemes by introducing an advanced testing platform based on a digital grid twin protection test bed using a synchronized time source system. The platform evaluates the communication system using radio antennas or optical fiber links by integrating protective relays that operate breakers within the digital twin and record relay events and communication signals. In the experiments, transmitter and receiver relays were configured with inverse time overcurrent and breaker trip detection logic to assess the total time of the communication protection schemes based on the sum of the relay protection element operating time, radio latency, propagation delay, baud rate delay, and relay processing time. These delays were derived from recorded relay events and communication signals from the interface of a real-time simulator set as a digital grid twin. The test bed successfully simulated various electrical faults along a distribution line while ensuring effective and reliable point-to-point communication between transmitter and receiver relays. The radio antenna communication system exhibited latency because of the radio. This latency depends on the baud rate setting and type of radio application; in general, the higher the baud rate, the lower the radio latency. The measured radio latency (for Mirrored Bits with an encryption card at 9,600 bps) was about 9–10 ms. Additionally, calculated propagation delay per mile for radio antennas and optical fiber was 5.36 µs/mi and 8.04 µs/mi, respectively. Optical fiber communication did not demonstrate radio latency. Instead, the protection element operating time depends mainly on the protection logic function set in the relay, and the relay processing time depends on the processing rate of the relay in samples per power system cycle.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2025

Investigating the Vulnerabilities of the Direct Transfer Trip Scheme for Network Protector Units in the Secondary Networks of Electric Power Distribution Grids

Network protector units (NPUs) are crucial parts of the protection of secondary networks to effectively isolate faults occurring on the primary feeders. When a fault occurs on the primary feeder, there is a path of the fault current going through the service transformers that causes a negative flow of current on the NPU connected to the faulted feeder. Conventionally, NPUs rely on the direction of current with respect to the voltage to detect faults and make a correct trip decision. However, the conventional NPU logic does not allow the reverse power flow caused by distributed energy resources installed on secondary networks. The communication-assisted direct transfer trip logic for NPUs can be used to address this challenge. However, the communication-assisted scheme is exposed to some vulnerabilities arising from the disruption or corruption of the communicated data that can endanger the reliable operation of NPUs. This paper evaluates the impact of the malfunction of the communication system on the operation of communication-assisted NPU logic. To this end, the impact of packet modification and denial-of-service cyberattacks on the communication-assisted scheme are evaluated. The evaluation was performed using a hardware-in-the-loop (HIL) co-simulation testbed that includes both real-time power system and communication network digital simulators. This paper evaluates the impact of the cyberattacks for different fault scenarios and provides a list of recommendations to improve the reliability of communication-assisted NPU protection.

direct transfer trip↗

DOE OSTI2024

The Tiny Median Filter: A Small Size, Flexible Arbitrary Percentile Finder Scheme Suitable for FPGA Implementation

This document reports the design, implementation and testing of a small silicon resource usage, very flexible arbitrary percentile finding scheme called the Tiny Median Filter. It can be used not only as a median filter in image processing with square filtering windows, but also for applications of any percentile filter or maximum or minimum finder with any size of data set as long as the number of bits of the data is finite. It opens possibilities for image processing tasks with non-square or irregular filter windows. In this scheme, data swapping or data bit manipulating are avoided and high functional efficiency of the logic components is applied to save silicon resources. Some logic functions are absorbed into other functions to further reduce the complexity. The combinational logic paths are designed to be sufficiently short so that the firmware can be compiled to the maximum operating frequency allowed by the block memories of the FPGA devices. The Tiny Median Filter receives, processes and output data in non-stop manner with no irregular timing which helps to simplify design of surrounding stages.

Wu, Jinyuan [Fermilab] (ORCID:0000000344329521)↗

DOE OSTI2025

Control System Upgrade for Battery State-of-Charge Indications

The Advanced Test Reactor (ATR) Complex at Idaho National Laboratory (INL) relies on Battery Backed Power (BBP) systems and Uninterruptible Power Supplies (UPS) to ensure continuous power supply to critical components. This project aims to enhance the reliability and functionality of the battery monitoring and control systems by updating the State-of-Charge (SOC) system, Programmable Logic Controller (PLC), and Human-Machine Interface (HMI) for the nuclear safety-related battery banks. The current system, while functional, has areas for improvement, particularly in recharging calculations and alarm functions. The project objectives include developing flow charts, programming the new PLC and HMI, conducting bench tests, and updating design documentation. Additionally, the project ensures compliance with safety standards, develops training materials, creates comprehensive documentation, and integrates seamlessly with existing ATR infrastructure. The new SOC system is designed to be scalable for future upgrades, improve efficiency, enhance data accuracy, implement redundancy features, and achieve project goals within budget constraints while considering environmental impact. The methodology involved familiarizing with BBP and UPS systems, collecting current readings, rescaling signals, learning ladder logic, and updating the HMI. The transition from SLC 5/03 PLC using RS Logix 500 to CompactLogix 5380 using Studio 5000 was a key step. Despite challenges in transferring outdated PLC ladder logic and HMI code, starting from scratch led to a more accurate and efficient monitoring system, contributing to improved safety and operational efficiency. The project is currently awaiting approval of the Engineering Calculation and Analysis Report (ECAR) before implementation.

42 - ENGINEERING↗

DOE OSTI2025

Unconventional compute methods and future challenges for superconducting digital computing

Superconducting digital computing (SDC) based on Josephson junctions (JJs) offers significant potential for enhancing compute throughput and reducing energy consumption compared to conventional room-temperature CMOS-based approaches. Current superconducting logic families exhibit diverse characteristics in clocking strategies, power management, and information encoding techniques. This paper reviews recent advancements in unconventional computing methods specifically designed for superconducting digital circuits, emphasizing temporal computing and pulse-train representations. Notable techniques include race logic (RL), temporal pulse train computing (U-SFQ), and temporal multipliers, each offering unique performance and area advantages suited to superconducting implementations. Additionally, this paper reviews innovations in superconducting coarse-grain reconfigurable architectures (CGRA), superconducting-specific on-chip communication architectures, cryogenic sensor interfaces, and quantum computing control electronics. Finally, we highlight research challenges that should be addressed to facilitate the widespread adoption of superconducting digital computing.

EDA tools↗

DOE OSTI2026

Analog-to-digital converter based on voltage-controlled superconducting devices

The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. Here, in this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.

Analog-to-digital converter↗

DOE OSTI2024

Low‐Volume Cores for Fabrication of Compact, Versatile, and Intelligent Soft Systems

Abstract This study introduces the low‐volume core (LVC) fabrication method, which enables the monolithic molding of compact, complex, versatile, and intelligent soft robotic systems. This method uses thin and flexible thermoplastic sheets to mold internal chambers in soft fluidic actuators, valves, and circuits. The LVC fabrication method creates low‐volume networks in soft actuators (LV‐net actuators) that can be made with compact and complex geometries, enabling both low actuation volume input and multi‐degree‐of‐freedom actuators. LVC fabrication can also be used for compact, completely soft, and monolithic logic components (valves with low‐volume core, also called as LV valves) to provide directional resistance as well as a switching mechanism that enables fluidic logic in soft systems. The compatibility of the fabrication methods for both soft actuators and valves facilitates the creation of compact, integrated, and versatile soft robotic systems with embodied intelligence. This study introduces two examples of such intelligent soft robotic systems that integrate both LV‐net actuators and LV valves to demonstrate capability for complex system fabrication.

Yu, Qifan↗

DOE OSTI2025

Introduction: Neuromorphic Materials

The explosive growth in data collection and the need to process it efficiently, as well as the desire to automate increasingly complex tasks in transportation, medical care, manufacturing, security and many other fields have motivated a growing interest in neuromorphic computing. Unlike the binary, transistorbased ON/OFF logic gates and separate logic and memory functionalities employed in digital computing, neuromorphic computing is inspired by animal brains that use interconnected synapses and neurons to perform processing, storage and transmission of information at the same location, while only consuming ~20 W or less of power. Motivated by the brain’s efficiency, adaptability, self-learning and resiliency qualities, neuromorphic computing can be broadly defined as an approach to processing and storing information using hardware and algorithms inspired by models of biological neural systems. Present research in neuromorphic computing encompasses approaches that vary significantly in their degree of neuro-inspiration, from systems that only incorporate features such as asynchronous, event-driven operation or use crossbar arrays of non-volatile memory (NVM) elements to accelerate deep neural networks (DNNs), to designs that embrace the extreme parallelism, sparsity, reconfigurability, adaptability, complexity and stochasticity observed in nervous systems. The term ‘neuromorphic’ computing is often credited to Carver Mead, who in the 1980s investigated Si-based analog electronics to replicate functions of the animal retina. Earlier important advances in this field include the work of Frank Rosenblatt, who proposed the concept of the perceptron, Bernard Widrow, who used this concept to build one of the first analog neural networks, the Adaline and many other researchers (see ref. 6 for an historical perspective on neuromorphic computing). With the recent increase in the use of artificial intelligence and large language models, and rising concerns over the associated energy costs, interest in neuromorphic hardware has expanded rapidly. According to some estimates, driven largely by the drastic growth in the training use of artificial intelligence (AI) models using the current computing architectures, the energy cost of computing is projected to reach the energy supply worldwide by 2045. Furthermore, while this is not a realistic outcome, it means that, if more efficient computing technologies are not developed -- soon -- the world will soon become one where demand for energy and market constraints limit the continued increase of societal access to AI and cloud services from data centers. Data centers used for training and use of these models consume hundreds of terawatt hours of electricity, already past 4% of the US electricity demand.

Circuits↗