Test on 2n2369, npn silicon epitaxial transistors manufactured by fairchild semiconductor
Electric resistivity of carbon resistor material for calculating static response characteristics of carbon bolometer element
N-P-N JUNCTION↗
SEARCH · Engineering Papers
Results for “JUNCTION TRANSISTOR”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Auger recombination in heavily doped shallow-emitter silicon p-n-junction solar cells, diodes, and transistors
A rigorous analytic evaluation of an emitter model that includes Auger recombination but excludes bandgap narrowing is presented. It is shown that such a model cannot explain the experimentally observed values of the open-circuit voltage in p-n-junction silicon solar cells. Thus physical mechanisms in addition to Auger recombination are responsible for the experimentally observed values of the open-circuit voltage in silicon solar cells and the common-emitter current gain in bipolar transistors.
Shibib, M. A.↗
Tunnel junction-enabled monolithically integrated GaN micro-light emitting transistor
GaN/InGaN microLEDs are a very promising technology for next-generation displays. Switching control transistors and their integration are key components in achieving high-performance, efficient displays. Monolithic integration of microLEDs with GaN switching devices provides an opportunity to control microLED output power with capacitive (voltage)-controlled rather than current-controlled schemes. This approach can greatly reduce system complexity for the driver circuit arrays while maintaining device opto-electronic performance. In this work, we demonstrate a 3-terminal GaN micro-light emitting transistor that combines a GaN/InGaN blue tunneling-based microLED with a GaN n-channel FET. Further, the integrated device exhibits excellent gate control, drain current control, and optical emission control. This work provides a promising pathway for future monolithic integration of GaN FETs with microLED to enable fast switching, high-efficiency microLED display and communication systems.
42 ENGINEERING↗
Heavily doped transparent-emitter regions in junction solar cells, diodes, and transistors
The paper presents an analytical treatment of transparent-emitter devices, particularly solar cells, that is more complete than previously available treatments. The proposed approach includes the effects of bandgap narrowing, Fermi-Dirac statistics, built-in field due to impurity profile, and a finite surface recombination velocity at the emitter surface. It is demonstrated that the transparent-emitter model can predict experimental values of Voc observed on n(plus)-p thin diffused junction silicon solar cells made on low-resistivity (0.1 ohm-cm) substrates. A test is included for the self-consistent validity of the transparent-emitter model. This test compares the calculated transit time of minority carriers across the emitter with the Auger-impact minority-carrier lifetime within the emitter region.
Shibib, M. A.↗
G(sup 4)FET Implementations of Some Logic Circuits
Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET
Mojarradi, Mohammad↗
Determination of lifetimes and recombination currents in p-n junction solar cells, diodes, and transistors
New methods are presented and illustrated that enable the accurate determination of the diffusion length of minority carriers in the narrow regions of a solar cell or a diode. Other methods now available are inaccurate for the desired case in which the width of the region is less than the diffusion length. Once the diffusion length is determined by the new methods, this result can be combined with measured dark I-V characteristics and with small-signal admittance characteristics to enable determination of the recombination currents in each quasi-neutral region of the cell - for example, in the emitter, low-doped base, and high-doped base regions of the BSF (back-surface-field) cell. This approach leads to values for the effective surface recombination velocity of the high-low junction forming the back-surface field of BSF cells or the high-low emitter junction of HLE cells. These methods are also applicable for measuring the minority-carrier lifetime in thin epitaxial layers grown on substrates with opposite conductivity type.
Neugroschel, A.↗
Effects of stress-induced band-gap widening and defects in GaAs junctions.
Compressive stress effect on band gap widening and diffusion current in GaAs junctions
JUNCTION TRANSISTOR↗
JANTX2N2369A transistor
Report describes effects of power and temperature overstress on National Semiconductor and Raytheon transistors. Good junction quality was maintained. Gain losses predominated. Other failures are reported.
Source record↗
A 32-bit Ultrafast Parallel Correlator using Resonant Tunneling Devices
An ultrafast 32-bit pipeline correlator has been implemented using resonant tunneling diodes (RTD) and hetero-junction bipolar transistors (HBT). The negative differential resistance (NDR) characteristics of RTD's is the basis of logic gates with the self-latching property that eliminates pipeline area and delay overheads which limit throughput in conventional technologies. The circuit topology also allows threshold logic functions such as minority/majority to be implemented in a compact manner resulting in reduction of the overall complexity and delay of arbitrary logic circuits. The parallel correlator is an essential component in code division multi-access (CDMA) transceivers used for the continuous calculation of correlation between an incoming data stream and a PN sequence. Simulation results show that a nano-pipelined correlator can provide and effective throughput of one 32-bit correlation every 100 picoseconds, using minimal hardware, with a power dissipation of 1.5 watts. RTD plus HBT based logic gates have been fabricated and the RTD plus HBT based correlator is compared with state of the art complementary metal oxide semiconductor (CMOS) implementations.
Kulkarni, Shriram↗
Cryogenic measurements of aerojet GaAs n-JFETs
The spectral noise characteristics of Aerojet gallium arsenide (GaAs) junction field effect transistors (JFET's) have been investigated down to liquid-helium temperatures. Noise characterization was performed with the field effect transistor (FET) in the floating-gate mode, in the grounded-gate mode to determine the lowest noise readings possible, and with an extrinsic silicon photodetector at various detector bias voltages to determine optimum operating conditions. The measurements indicate that the Aerojet GaAs JFET is a quiet and stable device at liquid helium temperatures. Hence, it can be considered a readout line driver or infrared detector preamplifier as well as a host of other cryogenic applications. Its noise performance is superior to silicon (Si) metal oxide semiconductor field effect transistor (MOSFET's) operating at liquid helium temperatures, and is equal to the best Si n channel junction field effect transistor (n-JFET's) operating at 300 K.
Goebel, John H.↗
Degradation of transistor performance due to passage of small-Coulomb high-voltage surges
High voltage pulse causing beta degradation and junction resistance drop in transistor
ELECTRIC PULSE↗
Increased junction lead inductance ballasts high-frequency transistors
Segmentation of transistor bonding stripes and the inherent inductance of individual leads provides ballast for even current distribution across the junction of a high-frequency transistor.
Gilbert, G. J.↗
Method for Providing Semiconductors Having Self-Aligned Ion Implant
A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500.degree. C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.
Neudeck, Philip G.↗
Method for Providing Semiconductors Having Self-Aligned Ion Implant
A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500.degree. C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.
Neudeck, Philip G.↗
Progress Towards Prolonged Deployment of SiC JFET-R ICs Into Previously Inaccessible Hostile Environments
This invited presentation describes demonstration of semiconductor integrated circuits (ICs) and ceramic packaging that are arguably the most environmentally durable transistor electronics ever demonstrated. SiC junction field effect transistor-resistor (JFET-R) ICs with two-level interconnect have successfully operated for over 1 year in 500 °C air-ambient [1], 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber [2], and radiation exposure through 7 Mrad(Si) total ionizing dose (TID) and 86 MeV-cm2/mg heavy ion strikes [3]. Furthermore, these ICs have also demonstrated operation from -190 °C to +812 °C (over 1000 °C T-span) without significant change in signal (input /output) or power supply voltages [4]. With modest adjustments, the SiC JFET-R fabrication process is compatible with semiconductor mass-production tools and materials. As an initial step towards this end, the processing that forms the SiC JFETs and resistors (without interconnect) for the NASA Glenn “Generation 12” design prototype JFET-R ICs was conducted at GE Research. Once the COVID-delayed IC interconnect and bond pad fabrication processing on these wafers is completed at NASA Glenn, the resulting chips will be packaged and oven-tested [5]. It is expected that further technology transfer to complete commercial production will lower investment and risk barriers to useful application deployment. For NASA, an initial high-value deployment is opening the Venus surface to extended missions for robotic scientific exploration.
Silicon Carbide↗
A dc model for power switching transistors suitable for computer-aided design and analysis
A model for bipolar junction power switching transistors whose parameters can be readily obtained by the circuit design engineer, and which can be conveniently incorporated into standard computer-based circuit analysis programs is presented. This formulation results from measurements which may be made with standard laboratory equipment. Measurement procedures, as well as a comparison between actual and computed results, are presented.
Wilson, P. M.↗
Fabrication of Tunnel Junctions For Direct Detector Arrays With Single-Electron Transistor Readout Using Electron-Beam Lithography
This paper will describe the fabrication of small aluminum tunnel junctions for applications in astronomy. Antenna-coupled superconducting tunnel junctions with integrated single-electron transistor readout have the potential for photon-counting sensitivity at sub-millimeter wavelengths. The junctions for the detector and single-electron transistor can be made with electron-beam lithography and a standard self-aligned double-angle deposition process. However, high yield and uniformity of the junctions is required for large-format detector arrays. This paper will describe how measurement and modification of the sensitivity ratio in the resist bilayer was used to greatly improve the reliability of forming devices with uniform, sub-micron size, low-leakage junctions.
Stevenson, T. R.↗
Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits
This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10 change in output characteristics for the remainder of 500C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.
Silicon Carbid↗