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Criteria applied to semiconductor materials and deposition processes for thick film, insulated gate field effect transistor fabrication
The contribution of more than one carrier to the conductivity in modulation-doped field effect transistors (MODFET) affects the resultant mobility and complicates the characterization of these devices. Mixed conduction arises from the population of several subbands in the two-dimensional electron gas (2DEG), as well as the presence of a parallel path outside the 2DEG. We characterized GaAs/AlGaAs MODFET structures with both delta and continuous doping in the barrier. Based on simultaneous Hall and conductivity analysis we conclude that the parallel conduction is taking place in the AlGaAs barrier, as indicated by the carrier freezeout and activation energy. Thus, simple Hall analysis of these structures may lead to erroneous conclusions, particularly for real-life device structures. The distribution of the 2D electrons between the various confined subbands depends on the doping profile. While for a continuously doped barrier the Shubnikov-de Haas analysis shows superposition of two frequencies for concentrations below 10(exp 12) cm(exp -2), for a delta doped structure the superposition is absent even at 50% larger concentrations. This result is confirmed by self-consistent analysis, which indicates that the concentration of the second subband hardly increases.
This viewgraph presentation provides an analysis of long-channel nanotube (NT) field effect transistors (FET) from NASA's Ames Research Center. The structure of such a transistor including the electrode contact, 1D junction, and the planar junction is outlined. Also mentioned are various characteristics of a nanotube tip-equipped scanning tunnel microscope (STM).
The temperature dependence of the gate current versus the gate voltage in complementary heterojunction field-effect transistors (CHFET's) is examined. An analysis indicates that the gate conduction is due to a combination of thermionic emission, thermionic-field emission, and conduction through a temperature-activated resistance. The thermionic-field emission is consistent with tunneling through the AlGaAs insulator. The activation energy of the resistance is consistent with the ionization energy associated with the DX center in the AlGaAs. Methods reducing the gate current are discussed.
Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures over the range of -190 C to +225 C in terms of its voltage/current characteristic curves. The test temperatures included +22, -50, -100, -150, -175, -190, +50, +100, +150, +175, +200, and +225 C. Limited thermal cycling testing was also performed on the device. These tests consisted of subjecting the transistor to a total of twelve thermal cycles between -190 C and +225 C. A temperature rate of change of 10 C/min and a soak time at the test temperature of 10 minutes were used throughout this work. Post-cycling measurements were also performed at selected temperatures. In addition, re-start capability at extreme temperatures, i.e. power switched on while the device was soaking for a period of 20 minutes at the test temperatures of -190 C and +225 C, was investigated.
Excellent dc and millimeter-wave performance is reported in In0.15Ga0.85As/Al0.15Ga0.85As pseudomorphic modulation-doped field effect transistors (MODFET's) with 0.25-micron-length gates. Extrinsic transconductances as high as 495 mS/mm at 300 K and unprecedented power performance in the 60-GHz range were observed. Although not yet optimized, excellent low noise characteristics, 0.9 dB, with an associated gain of 10.4 dB at 18 GHz, and a noise figure of 2.4 dB with an associated gain of 4.4 dB at 62 GHz were obtained. This is the best noise performance ever reported for a MODFET in this frequency range. These results clearly demonstrate the superiority of pseudomorphic MODFET structures in high-frequency applications.
A single-stage C-band superconductor/semiconductor hybrid field-effect transistor amplifier was designed, fabricated, and tested at 77 K. The large area (1 inch x 0.5 inches) high temperature superconducting Tl-Ba-Ca-Cu-O (TBCCO) thin film was rf magnetron sputtered onto a LaAlO3 substrate. The film had a transition temperature of about 92 K after it was patterned and etched. The amplifier showed a gain of 6 dB and a 3 dB bandwidth of 100 MHz centered at 7.9 GHz. An identical gold amplifier circuit was tested at 77 K, and these results are compared with those from the hybrid amplifier.
Differential drain resistance calculation for junction field effect transistors
A model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. The model is based on an existing model that incorporates partitioning of the ferroelectric layer to calculate the polarization within the ferroelectric material. The model incorporates several new aspects that are useful to the user. It takes into account the effect of a non-saturating gate voltage only partially polarizing the ferroelectric material based on the existing remnant polarization. The model also incorporates the decay of the remnant polarization based on the time history of the FFET. A gate pulse of a specific voltage; will not put the ferroelectric material into a single amount of polarization for that voltage, but instead vary with previous state of the material and the time since the last change to the gate voltage. The model also utilizes data from FFETs made from different types of ferroelectric materials to allow the user just to input the material being used and not recreate the entire model. The model also allows the user to input the quality of the ferroelectric material being used. The ferroelectric material quality can go from a theoretical perfect material with little loss and no decay to a less than perfect material with remnant losses and decay. This model is designed to be used by people who need to predict the external characteristics of a FFET before the time and expense of design and fabrication. It also allows the parametric evaluation of quality of the ferroelectric film on the overall performance of the transistor.
A method of making V-MOS field effect transistors is disclosed wherein a masking layer is first formed over a surface of a crystalline substrate. An aperture is then formed in the masking layer to expose the surface of the substrate. An anisotropic etchant is applied to the exposed surface so that a groove having a decreasing width within increasing depth is formed. However, the etch is not allowed to go to completion with the result that a partially formed V-shaped groove is formed. Ions are accelerated through the aperture for implantation in the crystalline substrate in the lower portion of the partially formed V-shaped groove. Thereafter, an anisotropic etchant is reapplied to the partially formed V-shaped groove, and the etch is allowed to go to completion.
Mathematical models of the common-source and common-gate amplifiers using metal-ferroelectric- semiconductor field effect transistors (MOSFETs) are developed in this paper. The models are compared against data collected with MOSFETs of varying channel lengths and widths, and circuit parameters such as biasing conditions are varied as well. Considerations are made for the capacitance formed by the ferroelectric layer present between the gate and substrate of the transistors. Comparisons between the modeled and measured data are presented in depth as well as differences and advantages as compared to the performance of each circuit using a MOSFET.
Silicon nitride and cermet resistors for binary counter metal insulator field effect transistor circuit
Extremely large current double interface GaAs/In(0.15)Ga(0.85)As/Al(0.15)Ga(0.85)As pseudomorphic modulation-doped field-effect transistors (MODFET's) grown by molecular beam epitaxy were achieved. The 1-micron gate devices studied have peak current levels (430 mA/mm at 300 K and 483mA/mm at 77 K) roughly one and a half to two times that found in single interface pseudomorphic MODFET's. These devices also retain high transconductances over a broad range of gate voltage, peaking at 312 mS/mm at 300 K and 362 mS/mm at 77 K. Excellent microwave performance is also obtained with a maximum frequency of oscillation (f-max) of 37 GHz and a current gain cut-off frequency of as high as 23 GHz at 300 K. An output power level of 14 dBm (1 dB gain compression) was obtained at 6 GHz for a 290-micron gate width. This double interface single quantum well MODFET may be of great importance in millimeter wave power amplifiers.
Low temperature semiconductor deposition techniques in fabricating thick film, insulated gate, field effect transistors
Considerable research has been performed by several organizations in the use of the Metal- Ferroelectric-Semiconductor Field-Effect Transistors (MFSFET) in memory circuits. However, research has been limited in expanding the use of the MFSFET to other electronic circuits. This research project investigates the modeling of a NAND gate constructed from MFSFETs. The NAND gate is one of the fundamental building blocks of digital electronic circuits. The first step in forming a NAND gate is to develop an inverter circuit. The inverter circuit was modeled similar to a standard CMOS inverter. A n-channel MFSFET with positive polarization was used for the n-channel transistor, and a n-channel MFSFET with negative polarization was used for the p-channel transistor. The MFSFETs were simulated by using a previously developed current model which utilized a partitioned ferroelectric layer. The inverter voltage transfer curve was obtained over a standard input of zero to five volts. Then a 2-input NAND gate was modeled similar to the inverter circuit. Voltage transfer curves were obtained for the NAND gate for various configurations of input voltages. The resultant data shows that it is feasible to construct a NAND gate with MFSFET transistors.
The purpose of this testing was to characterize the InterFET Corporation U309 for total dose response. This test shall serve as the radiation lot acceptance test (RLAT) for the lot date code (LDC) tested. The U309 is a discrete Junction Field Effect Transistor (JFET). High dose rate (HDR) irradiations were performed in this test so that the device susceptibility to Total Ionizing Dose (TID) could be determined.
Previous research investigated the modeling of a N Wga te constructed of Metal-Ferroelectric- Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. The NAND gate was modeled using n-channel MFSFETs with positive polarization for the standard CMOS n-channel transistors and n-channel MFSFETs with negative polarization for the standard CMOS p-channel transistors. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. During the low-to-high transition, the negatively polarized transistor pulls up the output voltage, and during the high-to-low transition, the positively polarized transistor pulls down the output voltage. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate. Extension of this technique to more complicated logic gates using MFSFETs will be studied.
Proton irradiation effects in MOS and junction field-effect transistors and integrated circuits