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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

GaN vertical-channel junction field-effect transistors with regrown p-GaN by metal organic chemical vapor deposition (MOCVD)

Fabricating a vertical-channel junction field-effect transistor includes forming an unintentionally doped GaN layer on a bulk GaN layer by metalorganic chemical vapor deposition, forming a Cr/SiO 2 hard mask on the unintentionally doped GaN layer, patterning a fin by electron beam lithography, defining the Cr and SiO 2 hard masks by reactive ion etching, improving a regrowth surface with inductively coupled plasma etching, removing hard mask residuals, regrowing a p-GaN layer, selectively etching the p-GaN layer, forming gate electrodes by electron beam evaporation, and forming source and drain electrodes by electron beam evaporation. The resulting vertical-channel junction field-effect transistor includes a doped GaN layer, an unintentionally doped GaN layer on the doped GaN layer, and a p-GaN regrowth layer on the unintentionally doped GaN layer. Portions of the p-GaN regrowth layer are separated by a vertical channel of the unintentionally doped GaN layer.

Zhao, Yuji↗
NASA NTRS1965

A Field-Effect Transistor (FET) model for ASAP

The derivation of the circuitry of a field effect transistor (FET) model, the procedure for adapting the model to automated statistical analysis program (ASAP), and the results of applying ASAP on this model are described.

Ming, L.↗
NASA NTRS2001

Electronic Model of a Ferroelectric Field Effect Transistor

A pair of electronic models has been developed of a Ferroelectric Field Effect transistor. These models can be used in standard electrical circuit simulation programs to simulate the main characteristics of the FFET. The models use the Schmitt trigger circuit as a basis for their design. One model uses bipolar junction transistors and one uses MOSFET's. Each model has the main characteristics of the FFET, which are the current hysterisis with different gate voltages and decay of the drain current when the gate voltage is off. The drain current from each model has similar values to an actual FFET that was measured experimentally. T'he input and o Output resistance in the models are also similar to that of the FFET. The models are valid for all frequencies below RF levels. No attempt was made to model the high frequency characteristics of the FFET. Each model can be used to design circuits using FFET's with standard electrical simulation packages. These circuits can be used in designing non-volatile memory circuits and logic circuits and is compatible with all SPICE based circuit analysis programs. The models consist of only standard electrical components, such as BJT's, MOSFET's, diodes, resistors, and capacitors. Each model is compared to the experimental data measured from an actual FFET.

MacLeod, Todd C.↗
NASA NTRS2009

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Phillips, Thomas A.↗
DOE OSTI2021

High performance ionic-liquid-gated air doped diamond field-effect transistors

Here we report successful fabrication of high performance ion-gated field-effect transistors (FETs) on hydrogenated diamond surface. Investigations on the hydrogen (H)-terminated diamond by Hall effect measurements shows Hall mobility as high as ~200 cm 2 V –1 s –1 . In addition we demonstrate a rapid fabrication scheme for achieving stable high performance devices useful for determining optimal growth and fabrication conditions. We achieved H-termination using hydrogen plasma treatment with a sheet resistivity as low as ~1.3 kΩ/sq. Conductivity through the FET channel is studied as a function of bias voltage on the liquid ion-gated electrode from –3.0 to 1.5 V. Stability of the H-terminated diamond surface was studied by varying the substrate temperature up to 350 °C. It was demonstrated that the sheet resistance and carrier densities remain stable over 3 weeks in ambient air atmosphere even at substrate temperatures up to 350 °C, whereas increasing temperature beyond this limit has effected hydrogenation. This study opens new avenues for carrying out fundamental research on diamond FET devices with ease of fabrication and high throughput.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
NASA NTRS2004

A Novel Metal-Ferroelectric-Semiconductor Field-Effect Transistor Memory Cell Design

The use of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor (MFSFET) in a resistive-load SRAM memory cell has been investigated A typical two-transistor resistive-load SRAM memory cell architecture is modified by replacing one of the NMOS transistors with an n-channel MFSFET. The gate of the MFSFET is connected to a polling voltage pulse instead of the other NMOS transistor drain. The polling voltage pulses are of sufficient magnitude to saturate the ferroelectric gate material and force the MFSFET into a particular logic state. The memory cell circuit is further modified by the addition of a PMOS transistor and a load resistor in order to improve the retention characteristics of the memory cell. The retention characteristics of both the "1" and "0" logic states are simulated. The simulations show that the MFSFET memory cell design can maintain both the "1" and "0" logic states for a long period of time.

Phillips, Thomas A.↗
DOE OSTI2020

Fabrication of field-effect transistors with transfer-free nanostructured carbon as semiconducting channel material

Carbon nanostructures as active channel material in field effect transistors (FETs) are appealing in microelectronics for their improved performance such as high speed and low energy dissipation. However, these devices require the incorporation of nanostructure transfer steps in the fabrication process flow, which makes difficult its application in large scale integration circuits. Here we present a novel method for the fabrication of FETs with nanostructured carbon in the channel with p-type semiconducting properties and intermediate drain-source current (IDS) on/off ratio. The method is based on the use of Ni nanoparticles in the source-drain gap region as seed material for the formation of carbon nanostructures in the FET channel. FETs without Ni nanoparticles in the channel showed no modulation of IDS as a function of gate voltage. The device fabrication process does not require any carbon nanostructure transfer steps since it directly forms carbon nanostructures electrically connected to the device's source and drain electrodes via electron-beam evaporation of carbon and conventional lithographic processes. Since all device fabrication steps are compatible with Si technology processes, they are capable of being further optimized following process development protocols practiced by the semiconductor industry.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
NASA NTRS1970

Current conduction in junction gate field effect transistors

The internal physical mechanism that governs the current conduction in junction-gate field effect transistors is studied. A numerical method of analyzing the devices with different length-to-width ratios and doping profiles is developed. This method takes into account the two dimensional character of the electric field and the field dependent mobility. Application of the method to various device models shows that the channel width and the carrier concentration in the conductive channel decrease with increasing drain-to-source voltage for conventional devices. It also shows larger differential drain conductances for shorter devices when the drift velocity is not saturated. The interaction of the source and the drain gives the carrier accumulation in the channel which leads to the space-charge-limited current flow. The important parameters for the space-charge-limited current flow are found to be the L/L sub DE ratio and the crossover voltage.

Kim, C.↗
DOE OSTI2020

Molybdenum Contacts to MoS 2 Field‐Effect Transistors: Schottky Barrier Extraction, Electrical Transport, and Low‐Frequency Noise

MoS 2 has great interest for nanoscale electronic devices, including transistors and sensors. Defect‐free structure, clean interface with the gate dielectric, and metals with suitable metal–semiconductor junctions are key for reliable devices. Molybdenum is shown as an excellent electrode for MoS 2 field‐effect transistors (FETs), but the correlation among device current, field‐effect mobility, and the low‐frequency noise (LFN) with number of atomic layers is not studied. Furthermore, the impact of Mo/MoS 2 Schottky barrier on electronic injection and scattering in the device needs to be understood. Herein, by studying the FETs with channels of different numbers of atomic‐layer thicknesses, it is shown that a molybdenum metal contact to MoS 2 provides reliable current injection with low Schottky barrier height, low contact resistance, low electron–phonon scattering, and negligible impurity scattering. The mobility and LFN are optimal at a channel thickness of ≈12 atomic layers, which is consistent with the “mobility maximum window” in MoS 2 transistors with prior studies using other contact metals.

Kwon, Jiseok↗
NASA NTRS2008

Ferroelectric Field-Effect Transistor Differential Amplifier Circuit Analysis

There has been considerable research investigating the Ferroelectric Field-Effect Transistor (FeFET) in memory circuits. However, very little research has been performed in applying the FeFET to analog circuits. This paper investigates the use of FeFETs in a common analog circuit, the differential amplifier. The two input Metal-Oxide-Semiconductor (MOS) transistors in a general MOS differential amplifier circuit are replaced with FeFETs. Resistors are used in place of the other three MOS transistors. The FeFET model used in the analysis has been previously reported and was based on experimental device data. Because of the FeFET hysteresis, the FeFET differential amplifier has four different operating modes depending on whether the FeFETs are positively or negatively polarized. The FeFET differential amplifier operation in the different modes was analyzed by calculating the amplifier voltage transfer and gain characteristics shown in figures 2 through 5. Comparisons were made between the FeFET differential amplifier and the standard MOS differential amplifier. Possible applications and benefits of the FeFET differential amplifier are discussed.

Phillips, Thomas A.↗
NASA NTRS1992

Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K

Noise and current-voltage characterization of complementary heterojunction field-effect transistor (CHFET) structures below 8 K are presented. It is shown that the CHFET exhibits normal transistor operation down to 6 K. Some of the details of the transistor operation, such as the gate-voltage dependence of the channel potential, are analyzed. The gate current is examined and is shown to be due to several mechanisms acting in parallel. These include field-emission and thermionic-field-emission, conduction through a temperature-activated resistance, and thermionic emission. The input referred noise for n-channel CHFETs is presented and discussed. The noise has the spectral dependence of 1/f noise, but does not exhibit the usual area dependence.

Cunningham, Thomas J.↗
DOE OSTI2021

Accumulation-Type Ohmic van der Waals Contacts to Nearly Intrinsic WSe 2 Nanosheet-Based Channels: Implications for Field-Effect Transistors

We report the fabrication of ohmic van der Waals (vdW) contacts to nearly intrinsic WSe 2 nanosheet-based channels in field-effect transistors (FETs) using degenerately p-doped MoS2 (p + -MoS2) as a contact metal. We demonstrate that accumulation-type ohmic contacts and the high device performance are achievable without electrostatically gating the drain/source contact regions despite the nearly intrinsic nature of WSe 2 . Back-gated WSe 2 FETs with p + -MoS 2 bottom contacts (which screen the back-gate electric field in the drain/source regions) exhibit linear output characteristics, a high on/off ratio of 10 8 , and a high two-terminal field-effect mobility up to ~200 cm2 V –1 s –1 at room temperature. Our theoretical modeling reveals that the p + -MoS 2 /WSe 2 vdW junction behaves like a metal/semiconductor ohmic contact signified by a vanishingly thin space-charge region of ~1 nm on the p + -MoS 2 side and a substantial accumulation layer of free holes on the WSe 2 side, which is further verified by additional temperature-dependent and dual-gated measurements of WSe 2 FETs. We attribute the formation of accumulation-type ohmic contacts free of a Schottky barrier to the near absence of Fermi-level pinning at the vdW interface and the work function of p + -MoS 2 being larger than the ionization energy of WSe 2 . This study represents an important step toward achieving low-resistance ohmic contacts to two-dimensional (2D) semiconductors by eliminating the Fermi-level pinning effects, which is expected to have significant implications for next-generation 2D semiconductor-based nanoelectronics.

36 MATERIALS SCIENCE↗
NASA NTRS1995

Mixed Carrier Conduction in Modulation-doped Field Effect Transistors

The contribution of more than one carrier to the conductivity in modulation-doped field effect transistors (MODFET) affects the resultant mobility and complicates the characterization of these devices. Mixed conduction arises from the population of several subbands in the two-dimensional electron gas (2DEG), as well as the presence of a parallel path outside the 2DEG. We characterized GaAs/AlGaAs MODFET structures with both delta and continuous doping in the barrier. Based on simultaneous Hall and conductivity analysis we conclude that the parallel conduction is taking place in the AlGaAs barrier, as indicated by the carrier freezeout and activation energy. Thus, simple Hall analysis of these structures may lead to erroneous conclusions, particularly for real-life device structures. The distribution of the 2D electrons between the various confined subbands depends on the doping profile. While for a continuously doped barrier the Shubnikov-de Haas analysis shows superposition of two frequencies for concentrations below 10(exp 12) cm(exp -2), for a delta doped structure the superposition is absent even at 50% larger concentrations. This result is confirmed by self-consistent analysis, which indicates that the concentration of the second subband hardly increases.

Schacham, S. E.↗