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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

Lattice-Matched Semiconductor Layers on Single Crystalline Sapphire Substrate

SiGe is an important semiconductor alloy for high-speed field effect transistors (FETs), high-temperature thermoelectric devices, photovoltaic solar cells, and photon detectors. The growth of SiGe layer is difficult because SiGe alloys have different lattice constants from those of the common Si wafers, which leads to a high density of defects, including dislocations, micro-twins, cracks, and delaminations. This innovation utilizes newly developed rhombohedral epitaxy of cubic semiconductors on trigonal substrates in order to solve the lattice mismatch problem of SiGe by using trigonal single crystals like sapphire (Al2O3) as substrate to give a unique growth-orientation to the SiGe layer, which is automatically controlled at the interface upon sapphire (0001). This technology is different from previous silicon on insulator (SOI) or SGOI (SiGe on insulator) technologies that use amorphous SiO2 as the growth plane. A cubic semiconductor crystal is a special case of a rhombohedron with the inter-planar angle, alpha = 90 deg. With a mathematical transformation, all rhombohedrons can be described by trigonal crystal lattice structures. Therefore, all cubic lattice constants and crystal planes (hkl) s can be transformed into those of trigonal crystal parameters. These unique alignments enable a new opportunity of perfect lattice matching conditions, which can eliminate misfit dislocations. Previously, these atomic alignments were thought to be impossible or very difficult. With the invention of a new x-ray diffraction measurement method here, growth of cubic semiconductors on trigonal crystals became possible. This epitaxy and lattice-matching condition can be applied not only to SiGe (111)/sapphire (0001) substrate relations, but also to other crystal structures and other materials, including similar crystal structures which have pointgroup rotational symmetries by 120 because the cubic (111) direction has 120 rotational symmetry. The use of slightly miscut (less than plus or minus 10 deg.) sapphire (0001) substrate can be used to improve epitaxial relationships better by providing attractive atomic steps in the epitaxial process.

Choi, Sang↗
NASA NTRS1992

Temperature independent quantum well FET with delta channel doping

A temperature independent device is presented which uses a quantum well structure and delta doping within the channel. The device requires a high delta doping concentration within the channel to achieve a constant Hall mobility and carrier concentration across the temperature range 300-1.4 K. Transistors were RF tested using on-wafer probing and a constant G sub max and F sub max were measured over the temperature range 300-70 K.

Young, P. G.↗
DOE OSTI2023

Strain Anisotropy Driven Spontaneous Formation of Nanoscrolls from 2D Janus Layers

2D Janus transition metal dichalcogenides (TMDs) have attracted attention due to their emergent properties arising from broken mirror symmetry and self‐driven polarization fields. While it has been proposed that their vdW superlattices hold the key to achieving superior properties in piezoelectricity and photovoltaic, available synthesis has ultimately limited their realization. Here, in this study, the first packed vdW nanoscrolls made from Janus TMDs through a simple one‐drop solution technique are reported. The results, including ab initio simulations, show that the Bohr radius difference between the top sulfur and the bottom selenium atoms within Janus ${M^S_{Se}}$ (M = Mo, W) results in a permanent compressive surface strain that acts as a nanoscroll formation catalyst after small liquid interaction. Unlike classical 2D layers, the surface strain in Janus TMDs can be engineered from compressive to tensile by placing larger Bohr radius atoms on top (${M_S^{Se}}$) to yield inverted C scrolls. Detailed microscopy studies offer the first insights into their morphology and readily formed Moiré lattices. In contrast, spectroscopy and FETs studies establish their excitonic and device properties and highlight significant differences compared to 2D flat Janus TMDs. These results introduce the first polar Janus TMD nanoscrolls and introduce inherent strain‐driven scrolling dynamics as a catalyst to create superlattices.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Elimination of the bias-stress effect in ligand-free quantum dot field-effect transistors

Field-effect transistors (FETs) made from colloidal quantum dot (QD) solids commonly suffer from current–voltage hysteresis caused by the bias-stress effect (BSE), which complicates fundamental studies of charge transport in QD solids and the use of QD FETs in electronics. Here, we show that the BSE can be eliminated in n-channel PbSe QD FETs by first removing the QD ligands with a dose of H 2 S gas and then infilling the QD films with alumina by atomic layer deposition (ALD). The H 2 S-treated, alumina-infilled FETs have stable, hysteresis-free device characteristics (total short-term stability), indefinite air stability (total long-term stability), and a high electron mobility of up to 14 cm 2 V −1 s −1 , making them attractive for QD circuitry and optoelectronic devices. The BSE-free devices are utilized to conclusively establish the dependence of the electron mobility on temperature and QD diameter. We demonstrate that the BSE in these devices is caused by both electron trapping at the QD surface and proton drift within the film. The H 2 S/alumina chemistry produces ligand-free PbSe/PbS/Al 2 O 3 interfaces that lack the traps that cause the electronic part of the BSE, while full alumina infilling stops the proton motion responsible for the ionic part of the BSE. In conclusion, our matrix engineering approach should aid efforts to eliminate the BSE, boost carrier mobilities, and improve charge transport in other types of nanocrystal solids.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2025

Quantitative characterization of ZrO2 gate dielectric interface with tellurium

Tellurium (Te) has recently emerged as a promising p-type semiconductor that can be processed at low temperatures, compatible with back end of line CMOS integration. Characterization of tellurium–dielectric interfaces is essential for further device advancements. Here, the interface quality of Te with ZrO2 gate dielectric is studied in a metal-oxide semiconductor capacitor structure. The interface trap density (Dit) is measured as a function of atomic layer deposition (ALD) temperature, without the use of a seed layer. Given the low thermal budget of Te, the ALD temperature is shown to be particularly important. The lowest Dit of 5 × 1012 states/cm2 eV is obtained at a low ALD process temperature of 120 °C. To further assess the impact of Dit on device performance, field-effect transistors (FETs) were fabricated. The subthreshold swing and effective hole mobility of the FETs were analyzed in relation to Dit, emphasizing the importance of a defect-minimized interface for enhancing Te transistor performance.

Byeon, Kyeong-Jae↗
NASA NTRS1973

P-channel silicone gate FET

Modified fabrication technique for P-channel MOSFET devices eliminates problems involving gate placement and gate overlap. Technique provides self-aligned gate, eliminating complexity of mask aligning. Devices produced by this process are considerably faster than conventional MOSFET's and process increases yield.

Ostis, S.↗
DOE OSTI2024

Statistical analysis of displacement damage in small devices from neutron and ion irradiation

Modern semiconductor devices, such as gate-all-around nanosheet field-effect transistors (GAA NS FETs), are smaller than displacement damage cascades from fission neutrons. In this regime, device failure may occur through low-probability single events, rather than by parametric degradation previously seen in larger devices. Here, we present a statistical model that predicts the probability of a damage event in a small device and the probability distribution of the magnitude, i.e., number of displacements within the device, from each event. The model is developed first for neutron irradiation and then for energetic ion irradiation. The model is consistent with results from recent experiments in which lithium-ion irradiation produced stepwise increases in subthreshold current in GAA NS FETs.

Wampler, W. R.↗
NASA NTRS1991

New dynamic FET logic and serial memory circuits for VLSI GaAs technology

The complexity of GaAs field effect transistor (FET) very large scale integration (VLSI) circuits is limited by the maximum power dissipation while the uniformity of the device parameters determines the functional yield. In this work, digital GaAs FET circuits are presented that eliminate the DC power dissipation and reduce the area to 50% of that of the conventional static circuits. Its larger tolerance to device parameter variations results in higher functional yield.

Eldin, A. G.↗
NASA NTRS2015

Performance Evaluation of an Automotive-Grade, High Speed Gate Driver for SiC FETs, Type UCC27531, Over a Wide Temperature Range

Silicon carbide (SiC) devices are becoming widely used in electronic power circuits as replacement for conventional silicon parts due to their attractive properties that include low on-state resistance, high temperature tolerance, and high frequency operation. These attributes have a significant impact by reducing system weight, saving board space, and conserving power. In this work, the performance of an automotive-grade high speed gate driver with potential use in controlling SiC FETs (field-Effect Transistors) in converters or motor control applications was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to assess performance and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

Transistor Gate Drive↗
NASA NTRS1985

1985 Annual Conference on Nuclear and Space Radiation Effects, 22nd, Monterey, CA, July 22-24, 1985, Proceedings

Basic mechanisms of radiation effects in structures and materials are discussed, taking into account the time dependence of interface state production, process dependent build-up of interface states in irradiated N-channel MOSFETs, bias annealing of radiation and bias induced positive charges in n- and p-type MOS capacitors, hole removal in thin-gate MOSFETs by tunneling, and activation energies of oxide charge recovery in SOS or SOI structures after an ionizing pulse. Other topics investigated are related to radiation effects in devices, radiation effects in integrated circuits, spacecraft charging and space radiation effects, single-event phenomena, hardness assurance and radiation sources, SGEMP/IEMP phenomena, EMP phenomena, and dosimetry and energy-dependent effects. Attention is given to a model of the plasma wake generated by a large object, gate charge collection and induced drain current in GaAs FETs, simulation of charge collection in a multilayer device, and time dependent dose enhancement effects on integrated circuit transient response mechanisms.

Jones, C. W.↗
NASA NTRS2009

Zinc Alloys for the Fabrication of Semiconductor Devices

ZnBeO and ZnCdSeO alloys have been disclosed as materials for the improvement in performance, function, and capability of semiconductor devices. The alloys can be used alone or in combination to form active photonic layers that can emit over a range of wavelength values. Materials with both larger and smaller band gaps would allow for the fabrication of semiconductor heterostructures that have increased function in the ultraviolet (UV) region of the spectrum. ZnO is a wide band-gap material possessing good radiation-resistance properties. It is desirable to modify the energy band gap of ZnO to smaller values than that for ZnO and to larger values than that for ZnO for use in semiconductor devices. A material with band gap energy larger than that of ZnO would allow for the emission at shorter wavelengths for LED (light emitting diode) and LD (laser diode) devices, while a material with band gap energy smaller than that of ZnO would allow for emission at longer wavelengths for LED and LD devices. The amount of Be in the ZnBeO alloy system can be varied to increase the energy bandgap of ZnO to values larger than that of ZnO. The amount of Cd and Se in the ZnCdSeO alloy system can be varied to decrease the energy band gap of ZnO to values smaller than that of ZnO. Each alloy formed can be undoped or can be p-type doped using selected dopant elements, or can be n-type doped using selected dopant elements. The layers and structures formed with both the ZnBeO and ZnCdSeO semiconductor alloys - including undoped, p-type-doped, and n-type-doped types - can be used for fabricating photonic and electronic semiconductor devices for use in photonic and electronic applications. These devices can be used in LEDs, LDs, FETs (field effect transistors), PN junctions, PIN junctions, Schottky barrier diodes, UV detectors and transmitters, and transistors and transparent transistors. They also can be used in applications for lightemitting display, backlighting for displays, UV and visible transmitters and detectors, high-frequency radar, biomedical imaging, chemical compound identification, molecular identification and structure, gas sensors, imaging systems, and for the fundamental studies of atoms, molecules, gases, vapors, and solids.

Ryu, Yungryel↗
NASA NTRS2008

Efficient G(sup 4)FET-Based Logic Circuits

A total of 81 optimal logic circuits based on four-gate field-effect transistors (G(sup 4)4FETs) have been designed to implement all Boolean functions of up to three variables. The purpose of this development was to lend credence to the expectation that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. A G(sup 4)FET a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET) superimposed in a single silicon island and can therefore be regarded as two transistors sharing the same body. A G(sup 4)FET can also be regarded as a single device having four gates: two side junction-based gates, a top MOS gate, and a back gate activated by biasing of a silicon-on-insulator substrate. Each of these gates can be used to control the conduction characteristics of the transistor; this possibility creates new options for designing analog, radio-frequency, mixed-signal, and digital circuitry. One such option is to design a G(sup 4)FET to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. Optimal NOT-majority-gate, G(sup 4)FET-based logic-circuit designs were obtained in a comparative study that also included formulation of functionally equivalent logic circuits based on NOR and NAND gates implemented by use of conventional transistors. In the study, the problem of finding the optimal design for each logic function and each transistor type was solved as an integer-programming optimization problem. Considering all 81 non-equivalent Boolean functions included in the study, it was found that in 63% of the cases, fewer logic gates (and, hence, fewer transistors) would be needed in the G(sup 4)FET-based implementations.

Vatan, Farrokh↗
NASA NTRS1975

Theoretical transducer properties of piezoelectric insulator FET transducers

An oriented piezoelectric film incorporated in the insulator region of a silicon insulated-gate field-effect transistor (FET) results in a sensitive high-frequency strain transducer. Theory governing the transducer properties of the piezoelectric insulator FET transducer is presented. Equations are developed which relate the drain current of the device to induced polarizations of the piezoelectric layer. The highest frequency of surface strains to which the FET transducer can respond is determined by the FET frequency response - ultimately by the channel transit time. This frequency can extend to the GHz range. The low-frequency response to applied strain is determined by the dielectric relaxation frequency of the piezoelectric layer.

Greeneich, E. W.↗
NASA NTRS1981

Cryogenic switched MOSFET characterization

Both p channel and n channel enhancement mode MOSFETs can be readily switched on and off at temperatures as low as 2.8 K so that switch sampled readout of a VLWIR Ge:Ga focal plane is electronically possible. Noise levels as low as 100 rms electrons per sample (independent of sample rate) can be achieved using existing p channel MOSFETs, at overall rates up to 30,000 samples/second per multiplexed channel (e.g., 32 detectors at a rate of almost 1,000 frames/second). Run of the mill devices, including very low power dissipation n channel FETs would still permit noise levels of the order of 500 electrons/sample.

Source record↗
NASA NTRS2009

Universal programmable logic gate and routing method

An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.

Fijany, Amir↗
NASA NTRS1988

Noise-margin limitations on gallium-arsenide VLSI

Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield. Projection of VLSI complexity based on these factors indicates that logic chips of 15,000 gates are feasible with the most promising static circuits if a maximum power dissipation of 5 W per chip is assumed. While lower power per gate and therefore more gates per chip can be obtained by using a popular E/D FET circuit, yields are shown to be small when practical device parameter tolerances are applied. Further improvements in materials, devices, and circuits wil be needed to extend circuit complexity to the range currently dominated by silicon.

Long, Stephen I.↗
DOE OSTI2024

β-Ga2O3-Based Heterostructures and Heterojunctions for Power Electronics: A Review of the Recent Advances

During the past decade, Gallium Oxide (Ga2O3) has attracted intensive research interest as an ultra-wide-bandgap (UWBG) semiconductor due to its unique characteristics, such as a large bandgap of 4.5–4.9 eV, a high critical electric field of ~8 MV/cm, and a high Baliga’s figure of merit (BFOM). Unipolar β-Ga2O3 devices such as Schottky barrier diodes (SBDs) and field-effect transistors (FETs) have been demonstrated. Recently, there has been growing attention toward developing β-Ga2O3-based heterostructures and heterojunctions, which is mainly driven by the lack of p-type doping and the exploration of multidimensional device architectures to enhance power electronics’ performance. This paper will review the most recent advances in β-Ga2O3 heterostructures and heterojunctions for power electronics, including NiOx/β-Ga2O3, β-(AlxGa1−x)2O3/β-Ga2O3, and β-Ga2O3 heterojunctions/heterostructures with other wide- and ultra-wide-bandgap materials and the integration of two-dimensional (2D) materials with β-Ga2O3. Discussions of the deposition, fabrication, and operating principles of these heterostructures and heterojunctions and the associated device performance will be provided. This comprehensive review will serve as a critical reference for researchers engaged in materials science, wide- and ultra-wide-bandgap semiconductors, and power electronics and benefits the future study and development of β-Ga2O3-based heterostructures and heterojunctions and associated power electronics.

Herath Mudiyanselage, Dinusha (ORCID:0000000186119↗
NASA NTRS1979

Velocity overshoot effect on a short-gate microwave MESFET

The device parameters of short-gate GaAs and InP FETs have been found to be dependent on the nonequilibrium velocity overshoot phenomenon. Both saturation velocity and critical field are found to be larger for shorter gates. The v-E characteristics of Pucel et al. (1975) are modified. The cutoff frequency and other parameters for GaAs, InP, and Si are given as a function of gate length and bias. The cutoff frequency of InP MESFETs with a doping density of 10 to the 17th per cu cm is only 20% higher than those of equivalent GaAs MESFETs at 300 K. Comparison with other work is also presented.

Wang, Y.-C.↗