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At least 73 records · Page 4

ADC Nonlinearity Correction for the Majorana Demonstrator

Imperfections in analog-to-digital conversion cannot be ignored when signal digitization requirements demand both wide dynamic range and high resolution, as is the case for the MAJORANA DEMONSTRATOR 76 Ge neutrinoless double beta decay search. Enabling the experiment's high-resolution spectral analysis and efficient pulse shape discrimination required careful measurement and correction of ADC nonlinearites. Here, a simple measurement protocol was developed that did not require sophisticated equipment or lengthy data taking campaigns. A slope-dependent hysteresis was observed and characterized. A correction applied to digitized waveforms prior to signal processing reduced the differential and integral nonlinearites by an order of magnitude, eliminating these as dominant contributions to the systematic energy uncertainty at the double-beta decay Q value.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 µm\textsuperscript{2} in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e\textsuperscript{-} and a total dispersion of $\sim$100e\textsuperscript{-} The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4\% – 75.4\% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm\textsuperscript{2} staying within the experimental constraints.

Parpillon, Benjamin↗

Smart Pixels: In-pixel AI for on-sensor data filtering

We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 $\mu$m$^2$ in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e$^-$ and a total dispersion of $\sim$100e$^-$ The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4% - 75.4% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm$^2$ staying within the experimental constraints.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Signal propagation in reversible digital mechanics

Digital mechanics explores information processing through binary, mechanical circuits. This work demonstrates a flexural, mechanical integrated circuit (m-IC) that achieves reversible, non-reciprocal signal propagation through integrated AND logic and memory. Our approach exploits sequential bistable transitions with symmetric energy wells, tunable stiffness, impedance matching, and AND gate non-linearity, to enable signal propagation, repeatability, and reversibility. We present a generalized model of logic kinematics and energetics, validated experimentally, to study energy flows, quantify energetic limits, and identify operating regimes for reversible logic. Macro-scale experiments confirm propagation dynamics, and new fabrication methods extend the architecture to micro-scale devices. By achieving controlled, reversible signal transmission across interconnected logic and memory, this work establishes a scalable platform for robust mechanical computing and adaptive sensing.

Johnson, Hilary A. [Lawrence Livermore National La↗

Multi-channel front-end ASIC for a 3D position-sensitive detector

Arrays of 3D position-sensitive detectors (3DPSD), operating at room temperature and using cadmium zinc telluride (CZT) and thallium bromide (TIBr) sensors, are suitable for gamma-ray spectrometry in many applications. One detector configuration, the 3D position-sensitive Virtual Frisch-Grid detector (VFG), is particularly advantageous for integrating into large area arrays. The signals generated inside each detector of the array are captured with the anode, cathode and four pads that enable the reconstruction of the position and energy of the ionizing interaction by measurements of amplitude and timing of the signals. For these applications, a low-noise front-end ASIC has been developed, capable of processing bipolar signals (needed because of AC-coupling of certain electrodes). The ASIC can be coupled to an ADC in order to form a compound “waveform digitizer” capable of post-processing the analog signals and determining amplitude and timing information. This paper describes a 32-channel front-end ASIC that is suitable for reading out a 3 × 3 or 4 × 4 element matrix in the VFG configuration. Each channel is composed of a low-noise charge amplifier with an adaptive continuous reset feedback circuit suitable for both positive and negative charge, a first order shaper and a single-to-differential converter output stage. Voltage and current references are all internally generated by 10-bit DACs and the chip is fully controllable with the I 2 C communication protocol. The readout channel response has been verified using the implemented injection circuit. Linear behavior up to ~75 ke ± with the gain of ~80 mV/fC, and up to ~200 ke ± with the gain of ~30 mV/fC was demonstrated. In conclusion, the first test result waveforms using a 137 Cs radioactive source on a 5 × 5 × 12 mm 3 TIBr crystal are reported.

47 OTHER INSTRUMENTATION↗

Machine-Protection System for the PIP-II Linear Accelerator: Architecture and Data Processing Schemes

PIP-II at Fermilab features a brand-new, 800 MeV leading-edge Linear Accelerator (Linac) that will enable the Fermilab complex to deliver more than a megawatt of beam power to the Long Base-line Neutrino Facility (LBNF), requiring a robust Machine Protection System (MPS) to prevent beam-induced damage to delicate cryomodules and vacuum components. Signals in various accelerator components, in both analog and digital format, are collected and processed to assest the operating conditions of the accelerator. In the situation a potential damage is foreseen, the beam permit signal will be drop. A critical element of this system is the fast Analog Machine Protection System, a high-bandwidth platform designed for real-time beam loss monitoring. The system utilizes a modular, FPGA-based architecture to digitize signals from beam-sensing devices, such as AC Current Transformers (ACCTs), non-invasive Ring Pickups (RPUs) and beam scrapers. To eliminate both high frequency as well as 60 Hz noise that might be picked up in the industrial environment, data processing schemes beyond regular digital filtering are planned and implemented.

Wu, Jinyuan [Fermilab] (ORCID:0000000344329521)↗

Investigation of a digitizer for the plastic scintillation detectors of time-of-flight mass measurements

A CAEN DT5742 digitizer has been investigated to process the fast signals from the photomultiplier tubes of the time-of-flight detectors for fast ion beams. A test setup consisting of two plastic scintillation detectors and a pulsed laser source provided signals which were recorded by the digitizer and systematically analyzed with different algorithms to derive the amplitude, rise time and arrival time of the detection signal. To obtain the best amplitude and time resolutions, various optimization techniques including peak fitting and signal smoothing, interpolation improvement, and time-walk correction by amplitude and rise time have been performed and compared in detail. Here we compared the time resolutions obtained by three digital algorithms of leading-edge, zero-crossing constant-fraction (ZC-CFD) and direct constant-fraction discriminations. Finally, we found that the best time-of-flight resolution between two PMTs can be achieved as 12 ps by the method using sample minimum for peak location and using the time-walk-resistant ZC-CFD with 4-point interpolation for timing.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Counting multiple X-rays per pulse with an avalanche photodiode detector

Avalanche photodiode detectors (APDs) at X-ray synchrotrons are typically limited to recording at most one photon per synchrotron pulse. Digitizing the APD amplifier outputs enables signal processing to accurately measure a mean count rate of at least four photons per pulse based on initial synchrotron measurements. Higher rates are readily achievable. This method allows APDs to be utilized for time-resolved measurements at much higher intensities than before.

Powers, Liam T. (ORCID:000900047481248X)↗

Electronic Bottleneck Suppression in Next‐Generation Networks with Integrated Photonic Digital‐to‐Analog Converters

Digital‐to‐analog converters (DAC) are indispensable functional units in signal processing instrumentation and wide‐band telecommunication links for both civil and military applications. As photonic systems are capable of high data throughput and low latency, an increasingly found system limitation stems from the required domain crossing such as digital to analog and electronic to optical. A photonic DAC implementation, in contrast, enables a seamless signal conversion with respect to both energy efficiency and short signal delay, often requiring bulky discrete optical components and electric–optic transformation, hence introducing inefficiencies. Herein, a novel coherent parallel photonic DAC concept along with a 4‐bit experimental prototype capable of performing this DAC without optic–electric–optic domain crossing is introduced. This new paradigm guarantees a linear intensity weighting among bits when operating at high sampling rates (50 GHz), featuring an exceptional sampling efficiency (> 100 GS ) and small footprint (≈1 mm 2 ) in an 8‐bit implementation. Importantly, this photonic DAC enables seamless interfaces of next‐generation data processing hardware with high relevance in data centers, task‐specific compute accelerators such as neuromorphic engines, and network edge processing applications.

Meng, Jiawei↗

In-pixel AI for lossy data compression at source for X-ray detectors

Integrating neural networks for data compression directly in the Read-Out Integrated Circuits (ROICs), i.e. the pixelated front-end, would result in a significant reduction in off-chip data transfer, overcoming the I/O bottleneck. Our ROIC test chip (AI-In-Pixel-65) is designed in a 65 nm Low Power CMOS process for the readout of pixelated X-ray detectors. Each pixel consists of an analog front-end for signal processing and a 10b analog-to-digital converter operating at 100KSPS. Here, we compare two non-reconfigurable techniques, Principal Component Analysis (PCA) and an AutoEncoder (AE) as lossy data compression engines implemented within the pixelated area. The PCA algorithm achieves 50$×$ compression, adds one clock cycle latency, and results in a 21% increase in the pixel area. The AE achieves 70$×$ compression, adds 30 clock cycle latency, and results in a similar area increase.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

A Schottky Tune Meter for the Fermilab Mu2E Delivery Ring

The Mu2E experiment will measure the ratio of the rate of the neutrinoless, coherent conversion of muons into electrons as a measure of Charged Lepton Flavor Violation. As part of the Mu2E experiment, a proton storage ring, called the Delivery Ring, will utilize resonant extraction to slow-spill protons to the experiment. To regulate and optimize the Delivery Ring resonant extraction process, a fast tune measurement scheme will be required. This Mu2E tune meter will measure the average tune and the tune spectrum, in multiple time slices, through the entire resonant extraction cycle of nominally 43 msec. The Mu2E tune meter system utilizes vertical and horizontal 21.4 MHz Schottky detector resonant pickups, taken from the decommissioned Tevatron, high-gain amplifiers and digital down-conversion FPGA logic for its signal processing. This paper will present the design of this Schottky tune meter as well as tune measurements from the Mu2E delivery ring.

43 PARTICLE ACCELERATORS↗

The VMM3a ASIC

The VMM3a is a custom low-noise Application Specific Integrated Circuit. It is intended to be used in the front end readout electronics of both the Micromegas and sTGC detectors of the ATLAS New Small Wheels upgrade project at CERN. It is fabricated in the 130 nm GlobalFoundries 8RF-DM process. Here, the 64 channels with highly configurable parameters, although designed for a specific project, can meet the processing needs of signals from various detector types in several other applications. In this note, the VMM3a, which is the production version of the VMM family, will be presented along with the features incorporated and its performance.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

A pixel detector ROIC with a 3-bit, 40 Msps synchronous ADC per pixel for HL LHC

The prototype Fermi Compact Muon Solenoid (CMS) Pixel (FCP130), manufactured in a 130 nm process, is a readout integrated circuit (ROIC) designed for the High Luminosity upgrade of the Large Hadron Collider. It employs a synchronous analog to digital converter (ADC) for the front-end design, with signal processing and data conversion within a single bunch crossing of 25 ns. It is therefore capable of accurately detecting hits occurring in consecutive bunch crossings, without off-time registration of events, making it particularly suitable for the inner most layers of the vertex detector. The ROIC consists of a matrix of 48 × 160 pixels, each 100 × 30 μm2 in size. Each pixel contains a charge sensitive preamplifier with self-biasing leakage current compensation, eight auto-zero comparators and a Gray code encoder for a 3-bit flash-type ADC. The total power consumption is approximately 24 μW per pixel. The measured noise at the output of all the hit comparators across the ROIC is < 80 e- with threshold dispersion < 110 e-RMS, which allows an in-time threshold setting of ~ 1000 e-.

43 PARTICLE ACCELERATORS↗

In-Pixel Readout IC with compact in-pixel ADC for Pixel detectors at HL LHC

The prototype Smart Pixel concept test chip (SP28), designed in a CMOS 28 nm bulk process, is a proof of concept readout integrated circuit (ROIC) designed for a future Phase III High Luminosity upgrade of the Large Hadron Collider. It employs a synchronous analog to digital converter (ADC) for the front-end design, with signal processing and data conversion within a single bunch crossing of 25 ns. It is therefore capable of accurately detecting hits occurring in consecutive bunch crossings, without off-time registration of events and pileup insensitivity, making it particularly suitable for the inner most layers of the vertex detector. The ROIC consists of a matrix of 32 × 16 pixels, each 25 × 25 µm 2 in size. Each pixel contains a charge sensitive preamplifer with leakage current compensation, three auto-zero comparators for a 2-bit fash-type ADC. The total power consumption is approximately 5 µW per pixel. The measured noise at the output of all the hit comparators across the ROIC is < 90 e- with threshold dispersion < 45 e-RMS, which allows an in-time threshold setting of ≈ 475 e-.

Parpillon, Benjamin↗

Integration of Decentralized Graph-Based Multi-Agent Reinforcement Learning with Digital Twin for Traffic Signal Optimization

Machine learning (ML) methods, particularly Reinforcement Learning (RL), have gained widespread attention for optimizing traffic signal control in intelligent transportation systems. However, existing ML approaches often exhibit limitations in scalability and adaptability, particularly within large traffic networks. This paper introduces an innovative solution by integrating decentralized graph-based multi-agent reinforcement learning (DGMARL) with a Digital Twin to enhance traffic signal optimization, targeting the reduction of traffic congestion and network-wide fuel consumption associated with vehicle stops and stop delays. In this approach, DGMARL agents are employed to learn traffic state patterns and make informed decisions regarding traffic signal control. The integration with a Digital Twin module further facilitates this process by simulating and replicating the real-time asymmetric traffic behaviors of a complex traffic network. The evaluation of this proposed methodology utilized PTV-Vissim, a traffic simulation software, which also serves as the simulation engine for the Digital Twin. The study focused on the Martin Luther King (MLK) Smart Corridor in Chattanooga, Tennessee, USA, by considering symmetric and asymmetric road layouts and traffic conditions. Comparative analysis against an actuated signal control baseline approach revealed significant improvements. Experiment results demonstrate a remarkable 55.38% reduction in Eco_PI, a developed performance measure capturing the cumulative impact of stops and penalized stop delays on fuel consumption, over a 24 h scenario. In a PM-peak-hour scenario, the average reduction in Eco_PI reached 38.94%, indicating the substantial improvement achieved in optimizing traffic flow and reducing fuel consumption during high-demand periods. These findings underscore the effectiveness of the integrated DGMARL and Digital Twin approach in optimizing traffic signals, contributing to a more sustainable and efficient traffic management system.

42 ENGINEERING↗

Integration of Decentralized Graph-Based Multi-Agent Reinforcement Learning with Digital Twin for Traffic Signal Optimization

Machine learning (ML) methods, particularly Reinforcement Learning (RL), have gained widespread attention for optimizing traffic signal control in intelligent transportation systems. However, existing ML approaches often exhibit limitations in scalability and adaptability, particularly within large traffic networks. This paper introduces an innovative solution by integrating decentralized graph-based multi-agent reinforcement learning (DGMARL) with a Digital Twin to enhance traffic signal optimization, targeting the reduction of traffic congestion and network-wide fuel consumption associated with vehicle stops and stop delays. In this approach, DGMARL agents are employed to learn traffic state patterns and make informed decisions regarding traffic signal control. The integration with a Digital Twin module further facilitates this process by simulating and replicating the real-time asymmetric traffic behaviors of a complex traffic network. The evaluation of this proposed methodology utilized PTV-Vissim, a traffic simulation software, which also serves as the simulation engine for the Digital Twin. The study focused on the Martin Luther King (MLK) Smart Corridor in Chattanooga, Tennessee, USA, by considering symmetric and asymmetric road layouts and traffic conditions. Comparative analysis against an actuated signal control baseline approach revealed significant improvements. Experiment results demonstrate a remarkable 55.38% reduction in Eco_PI, a developed performance measure capturing the cumulative impact of stops and penalized stop delays on fuel consumption, over a 24 h scenario. In a PM-peak-hour scenario, the average reduction in Eco_PI reached 38.94%, indicating the substantial improvement achieved in optimizing traffic flow and reducing fuel consumption during high-demand periods. These findings underscore the effectiveness of the integrated DGMARL and Digital Twin approach in optimizing traffic signals, contributing to a more sustainable and efficient traffic management system.

actuated signal control↗

System and method for high dynamic range waveform digitization

Diverse applications from particle physics experiments to lidar are driving cost and current reduction in giga-hertz sampling rate high-resolution data conversion. Multiple imagers captures a single pixel of data and require processing at very high speed. High-bandwidth high-rate signal sampling, analog-to-digital conversion, and transfer of large amounts of data to a digital data acquisition block are required in such systems. Dynamic range, power consumption, and transfer of high-speed, high-bit width data are key implementation challenges. Data acquisition architectures optimized for specific requirements of such systems may facilitate system implementation and reduce overall system cost.

Mostafanezhad, Isar↗

Performance of 8 × 8 × 32 and 10 × 10 × 32 mm 3 CdZnTe position-sensitive virtual Frisch-grid detectors for high-energy gamma ray cameras

CdZnTe (CZT) crystals with thicknesses up to 20 mm and diameters up to 75 mm have become available from Redlen Technologies, Inc. for making large-volume gamma-ray detectors. The modified growth and optimized annealing conditions allowed Redlen to minimize the dark current and improve the uniformity of CZT crystals. Two detector designs, pixelated (H3D) and position-sensitive virtual Frisch-grid (VFG), have greatly benefitted from the availability of such big crystals. Encouraging results from testing of 40×40×15 mm 3 pixelated detectors were recently reported by the University of Michigan. In this work, we evaluated the spectroscopic properties of 8×8×32 and 10×10×32 mm 3 crystals configured as position-sensitive VFG detectors. Both digitized waveforms and an analog ASIC were used to read and process the signals from the detectors and test their spectral- and spatial-resolution. The VFG design provides the flexibility to scale-up the dimensions of the detectors for the desired efficiency, while the position information allows for correcting the detectors' response non-uniformity caused by crystal defects and devices geometry, thereby reducing the instrument cost and making them more feasible for emerging applications in gamma-ray astronomy, nonproliferation, portal screening and nuclear safeguards, where large detector arrays are often required.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗