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Digital controllers, one using a special-purpose computer and the other using a combination of digital and analog techniques, are designed around /1/ computers that simulate the transfer function and interface with the system, and /2/ analog and digital circuits, converters, amplifiers, constant multipliers, and delay lines that form a digital filter.
Digital computer-aided electric logic circuit analysis and design bibliography
The invention herein disclosed is a digital circuit which emulates a synchro signal in a synchro-resolver follower system for precise control of shaft position and rotation at very low rotational rates. The subject invention replaces the synchro and drive motor in a synchroresolver follower system with a digital and analog synchro emulation circuit for generating the resolver control signal. The synchro emulation circuit includes amplitude modulation means to provide relatively high frequency resolver excitation signals for accurate resolver response even with very low shaft rotation rates.
The invention disclosed is a digital circuit which emulates a synchro signal in a synchro-resolver follower system for precise control of shaft position and rotation at very low rotational rates. The invention replaces the synchro and drive motor in a synchro-resolver follower system with a digital and analog synchro emulation circuit for generating the resolver control signal. The synchro emulation circuit includes amplitude modulation means to provide relatively high frequency resolver excitation signals for accurate resolver response even with very low shaft rotation rates.
Achieving brain-like efficiency in computing requires a co-design between the development of neural algorithms, brain-inspired circuit design, and careful consideration of how to use emerging devices. The recognition that leveraging device-level noise as a source of controlled stochasticity represents an exciting prospect of achieving brain-like capabilities in probabilistic neural algorithms, but the reality of integrating stochastic devices with deterministic devices in an already-challenging neuromorphic circuit design process is formidable. Here, we explore how the brain combines different signaling modalities into its neural circuits as well as consider the implications of more tightly integrated stochastic, analog, and digital circuits. Further, by acknowledging that a fully CMOS implementation is the appropriate baseline, we conclude that if mixing modalities is going to be successful for neuromorphic computing, it will be critical that device choices consider strengths and limitations at the overall circuit level.
We have developed a range of techniques useful for constructing analog and digital circuits for operation in a liquid Helium environment (4.2K), using commercially available low power components. The challenges encountered in designing cryogenic electronics include finding components that can function usefully in the cold and possess low enough power dissipation so as not to heat the systems they are designed to measure. From design, test, and integration perspectives it is useful for components to operate similarly at room and cryogenic temperatures; however this is not a necessity. Some of the circuits presented here have been used successfully in the MUSTANG and in the GISMO camera to build a complete digital to analog multiplexer (which will be referred to as the Cryogenic Address Driver board). Many of the circuit elements described are of a more general nature rather than specific to the Cryogenic Address Driver board, and were studied as a part of a more comprehensive approach to addressing a larger set of cryogenic electronic needs.
The design concept and characteristics of a self-contained microprocessor-based Global Positioning System time transfer receiver is described. A prototype of this unit is currently in the test phase. It employs two-bit digital baseband correlation rather than analog IF correlation of the signals with the reference code. The correlator, numerically controlled oscillators and code generator are implemented in a special-purpose digital signal processor. The time is recovered in the digital code tracking loop, and final corrections are applied in the control processor. Other features of this design are: (1) drift-free digital mechanization; (2) high reliability of digital circuits; (3) flexible control capability of the microprocessor; and (4) potential for a high degree of digital VLSI chip development leading to compact, low-cost units.
The main problem facing current CAD tools for VLSIs is the large amount of memory required when dealing with large systems, primarily due to the circuit representation used by most current tools. This paper discusses an approach for hierarchical switch-level simulation of digital circuits. The approach exploits the hierarchy to reduce the memory requirements of the simulation, allowing the simulation of circuits that are too large to simulate at one flat level. The approach has been implemented in a hierarchical switch-level simulator, CHAMP, which runs on a SUN workstation. The program performs mixed mode simulation: parts of the circuit can be simulated faster at a behavioral level by supplying a high level software description. CHAMP allows assignable delays, and bidirectional signal flow inside circuit blocks that are represented as transistor networks as well as across the boundaries of higher level blocks. CHAMP is also unique in that it simulates directly from the hierarchical circuit description without flattening to a single level.
The Space Power and Propulsion Test Engineering Branch at NASA Glenn Research center has the important duty of controlling electronic test engineering services. These services include test planning and early assessment of Space projects, management and/or technical support required to safely and effectively prepare the article and facility for testing, operation of test facilities, and validation/delivery of data to customer. The Space Electronic Test Engineering Branch is assigned electronic test engineering responsibility for the GRC Space Simulation, Microgravity, Cryogenic, and Combustion Test Facilities. While working with the Space Power and Propulsion Test Engineering Branch I am working on several different assignments. My primary assignment deals with an electrical hardware unit known as Sunny Boy. Sunny Boy is a DC load Bank that is designed for solar arrays in which it is used to convert DC power form the solar arrays into AC power at 60 hertz to pump back into the electricity grid. However, there are some researchers who decided that they would like to use the Sunny Boy unit in a space simulation as a DC load bank for a space shuttle or even the International Space Station hardware. In order to do so I must create a communication link between a computer and the Sunny Boy unit so that I can preset a few of the limits (such power, set & constant voltage levels) that Sunny Boy will need to operate using the applied DC load. Apart from this assignment I am also working on a hi-tech circuit that I need to have built at a researcher s request. This is a high voltage analog to digital circuit that will be used to record data from space ion propulsion rocket booster tests. The problem that makes building this circuit so difficult is that it contains high voltage we must find a way to lower the voltage signal before the data is transferred into the computer to be read. The solution to this problem was to transport the signal using infrared light which will lower the voltage signal down low enough so that it is harmless to a computer. Along with my involvement in the Space Power and Propulsion Test Engineering Branch, I am obligated to assist all other members of the branch in their work. This will help me to strengthen and extend my knowledge of Electrical Engineering.
A new VOR (VHF omni-range) goniometer design which promises to improve the reliability and maintainability of the VOR ground station is described. The heart of the new concept is the use of two digital phase shifters to produce the rotating figure-of-eight pattern of conventional VOR. Using digital circuits, the goniometer adjustments and calibration reduce to timing adjustments of binary signals. A common clock used for timing the digital phase shifters also synchronizes the 30 Hz modulation of the 9.96 kHz reference.
NASA Lewis Research Center's Space Communications Division has been investigating high-speed digital filters that can operate at a higher speed than those in current use for a digital modulator and demodulator (modem). Using the Canonical Signed Digits (CSD) number representation for filter coefficients is a very effective way to increase the filter's speed while reducing complexity in the digital filter hardware design. This approach is a good alternative to using an expensive parallel-processing design technique or custom, application-specific integrated circuits. Such integrated circuits may not be suitable for applications that require filter speeds faster than what application-specific integrated circuits digital signal processors can offer for a dedicated channel. When a communication channel is a dedicated, multiplication process--a costly, time-consuming process--it can be greatly simplified by a replacement of the filter coefficients with CSD numbers. A computer code written with the MATLAB software package runs the program and generates CSD-represented filter coefficients that are based on minimizing minimum mean square errors. Also, the Alta Group of Cadence's Signal Processing Workstation is used to simulate and analyze the CSD filter responses. The impulse response of the root-raised cosine filter that is used as a base model is defined. From this filter, a set of coefficients is sampled and stored in a file. For the all coefficients, the optimal CSD number for each coefficient is searched on the basis of the minimum-mean-square-errors criterion. Because the distribution of CSD numbers is not uniform, quantization errors tend to be bigger for coefficients greater than 1/2. To offset errors that occur in a region of coefficients between 1/2 to 1 and to better represent fractions with CSD numbers, an extra nonzero digit is allowed for any coefficients exceeding 1/2. This will greatly improve frequency response as well as intersymbol interference at the receiver. The frequency response of a set of collected CSD-represented filter coefficients was compared with the same filter that was conventionally implemented. Analyses show CSD-implemented filters perform as well as conventional filters. Comparison of eye diagrams and bit-error-rate curves between CSD filters and traditionally implemented filters are almost indistinguishable. However, filter complexity was reduced from almost 3.5 to 1 for CSD filters. Complete computer simulation results are available. In the near future, work will focus on building actual working digital filter hardware in a field programmable gate array (FPGA).
Preliminary results indicate that the new front end automatic gain control (AGC) combination perform satisfactorily. Side by side bench tests with Trimble 10A and Texas Instruments 9900 LORAN-C receivers have proven that the proper time differences are being obtained. Further optimization of the AGC circuit will occur as software to track all of the stations in a LORAN-C chain is developed. The AGC circuit was designed to sample up to six separate LORAN-C stations. Along with expanded station tracking software, a more sophisticated search routine is also under development. A printed circuit board for the AGC is planned and will be enclosed with the RF front end in a sealed enclosure to reduce interference from the other digital circuits of the microcomputer.
Doppler-radar instrument measures small deflections or vibrations of reflecting surface. Acting as interferometric micrometer, instrument includes combination of analog and digital circuits measuring change in phase of radar return due to movement of reflecting surface along signal-propagation path. Includes homodyne Doppler-radar transceiver and digital signal-processing circuitry to measure change in phase shift as target deflects.
There is provided a digitally controlled first order hold circuit and waveform synthesizer for digitally controlling the representation of a function over an approximation interval. In accordance with the operation of the invention, the first order hold circuit and waveform generator receives a digital data input signal which contains initial condition data, up/down data, and slope data for the approximation interval. The initial condition data is loaded into an up/down counter which is incremented using counting data at a rate depending on the value of the slope data and in a direction depending on the value of the up-down data. In order to minimize delays arising from data acquistion, two frequency synthesizer circuits are provided such that one frequency synthesizer provides counting data while the other frequency synthesizer receives slope data. During alternating intervals, the other frequency synthesizer circuit provides counting data while the other circuit receives slope data. In addition, long length data input signals covering a plurality of approximation intervals are provided to reduce the demands on a main system central processing unit.
Application Specific Integrated Circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way which facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as framework of software modules, templates and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation. Templates provide a starting point for both while toolbox functions minimize the code required. Once a test bench has been coded to optimize a particular circuit, it is also used to verify the final design. The combination of test bench and cost function can then serve as a template for similar circuits or be re-used to migrate the design to different processes by re-running it with the new process specific device models. The system has been used in the design of time to digital converters for laser ranging and time-of-flight mass spectrometry to optimize analog, mixed signal and digital circuits such as charge sensitive amplifiers, comparators, delay elements, radiation tolerant dual interlocked (DICE) flip-flops and two of three voter gates.
The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification.
Accurate fault models are required to conduct the experiments defined in validation methodologies for highly reliable fault-tolerant computers (e.g., computers with a probability of failure of 10 to the -9 for a 10-hour mission). Described is a technique by which a researcher can evaluate the capability of the pin-level stuck-at fault model to simulate true error behavior symptoms in very large scale integrated (VLSI) digital circuits. The technique is based on a statistical comparison of the error behavior resulting from faults applied at the pin-level of and internal to a VLSI circuit. As an example of an application of the technique, the error behavior of a microprocessor simulation subjected to internal stuck-at faults is compared with the error behavior which results from pin-level stuck-at faults. The error behavior is characterized by the time between errors and the duration of errors. Based on this example data, the pin-level stuck-at fault model is found to deliver less than ideal performance. However, with respect to the class of faults which cause a system crash, the pin-level, stuck-at fault model is found to provide a good modeling capability.
A digitally programmable current-mode analog fuzzy membership function circuit (MFC) has been designed, simulated and fabricated in a 0.5 micro-m CMOS technology.