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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 73 records · Page 4
All sourcesNASA NTRSDOE OSTI
NASA NTRS1989

A VLSI chip set for real time vector quantization of image sequences

The architecture and implementation of a VLSI chip set that vector quantizes (VQ) image sequences in real time is described. The chip set forms a programmable Single-Instruction, Multiple-Data (SIMD) machine which can implement various vector quantization encoding structures. Its VQ codebook may contain unlimited number of codevectors, N, having dimension up to K = 64. Under a weighted least squared error criterion, the engine locates at video rates the best code vector in full-searched or large tree searched VQ codebooks. The ability to manipulate tree structured codebooks, coupled with parallelism and pipelining, permits searches in as short as O (log N) cycles. A full codebook search results in O(N) performance, compared to O(KN) for a Single-Instruction, Single-Data (SISD) machine. With this VLSI chip set, an entire video code can be built on a single board that permits realtime experimentation with very large codebooks.

Baker, Richard L.↗
NASA NTRS1989

Read disturb errors in a CMOS static RAM chip

Results are reported from an extensive investigation into pattern-sensitive soft errors (read disturb errors) in the TCC244 CMOS static RAM chip. The TCC244, also known as the SA2838, is a radiation-hard single-event-upset-resistant 4 x 256 memory chip. This device is being used by the Jet Propulsion Laboratory in the Galileo and Magellan spacecraft, which will have encounters with Jupiter and Venus, respectively. Two aspects of the part's design are shown to result in the occurrence of read disturb errors: the transparence of the signal path from the address pins to the array of cells, and the large resistance in the Vdd and Vss lines of the cells in the center of the array. Probe measurements taken during a read disturb failure illustrate how address skews and the data pattern in the chip combine to produce a bit flip. A capacitive charge pump formed by the individual cell capacitances and the resistance in the supply lines pumps down both the internal cell voltage and the local supply voltage until a bit flip occurs.

Wood, Steven H.↗
NASA NTRS1990

Using advanced microelectronic test chips to qualify ASIC's for space

Qualification procedures for complex integrated circuits are being developed under a U.S. government program known as Qualified Manufacturing Lines (QML). This effort is focused on circuits designed by IC manufacturers and has not addressed application specific IC's (ASIC's) designed at system houses. The qualification procedures described here are intended to be responsive to the needs of system houses who design their own ASIC's and have them fabricated at Silicon foundries. A particular focus of this presentation will be the use of the TID (total Ionizing Dose) Chip to evaluate CMOS foundry processes and to provide parameters for circuit simulators. This chip is under development as a standard chip for qualifying the total dose aspects of ASIC's. The benefits of standardization are that the results will be well understood and easy to interpret. Data is presented and compared for 1.6 micron and 3.0 micron CMOS. The data shows that 1.6 micron CMOS is significantly harder than 3.0 micron CMOS. Two failure modes are explored: (1) the radiation-induced degradation of timing delays; and (2) radiation-induced leakage currents.

Buehler, M. G.↗
NASA NTRS1994

Smart vision chips: An overview

This viewgraph presentation presents four working analog VLSI vision chips: (1) time-derivative retina, (2) zero-crossing chip, (3) resistive fuse, and (4) figure-ground chip; work in progress on computing motion and neuromorphic systems; and conceptual and practical lessons learned.

Koch, Christof↗
NASA NTRS2000

A Boundary Scan Test Vehicle for Direct Chip Attach Testing

To facilitate the new faster, better and cheaper spacecraft designs, smaller more mass efficient avionics and instruments are using higher density electronic packaging technologies such as direct chip attach (DCA). For space flight applications, these technologies need to have demonstrated reliability and reasonably well defined fabrication and assembly processes before they will be accepted as baseline designs in new missions. As electronics shrink in size, not only can repair be more difficult, but 49 probing" circuitry can be very risky and it becomes increasingly more difficult to identify the specific source of a problem. To test and monitor these new technologies, the Direct Chip Attach Task, under NASA's Electronic Parts and Packaging Program (NEPP), chose the test methodology of boundary scan testing. The boundary scan methodology was developed for interconnect integrity and functional testing at hard to access electrical nodes. With boundary scan testing, active devices are used and failures can be identified to the specific device and lead. This technology permits the incorporation of "built in test" into almost any circuit and thus gives detailed test access to the highly integrated electronic assemblies. This presentation will describe boundary scan, discuss the development of the boundary scan test vehicle for DCA and current plans for testing of direct chip attach configurations.

Parsons, Heather A.↗
NASA NTRS2001

Performance of High-Speed PWM Control Chips at Cryogenic Temperatures

The operation of power electronic systems at cryogenic temperatures is anticipated in many NASA space missions such as planetary exploration and deep space probes. In addition to surviving the space hostile environment, electronics capable of low temperature operation would contribute to improving circuit performance, increasing system efficiency, and reducing development and launch costs. As part of the NASA Glenn Low Temperature Electronics Program, several commercial high-speed Pulse Width Modulation (PWM) chips have been characterized in terms of their performance as a function of temperature in the range of 25 to -196 C (liquid nitrogen). These chips ranged in their electrical characteristics, modes of control, packaging options, and applications. The experimental procedures along with the experimental data obtained on the investigated chips are presented and discussed.

Elbuluk, Malik E.↗
NASA NTRS2001

Treatment and Analysis of a Paint Chip from "Water Lilies": A Fire Damaged Monet

A museum fire in 1958 severely damaged a Monet 'Water Lilies' (1916-1926) painting that was on display. The surface of the painting is very dark with areas of blistering and charring. Over the years, traditional techniques have been found to be ineffective at removal of the soot and char from the surface. The painting, which is now in the care of the New York University (NYU) Conservation Center of the Institute of Fine Arts, was the subject of a study to determine if atomic oxygen treatment could remove the soot and char without damaging the fragile painting underneath. For test purposes, a small chip of paint was removed from the edge of the painting by a conservator at NYU and supplied to NASA Glenn Research Center for atomic oxygen treatment and analysis. The diffuse spectral reflectance, at three locations on the paint chip, was monitored at intervals during the atomic oxygen treatment process. Photo documentation of the chip during treatment was also performed. The color contrast was calculated from the spectral reflectance data as a function of treatment duration. Results of the testing indicated that the contrast improved as a result of the treatment, and the differentiation of colors on the surface was significantly improved. Soot and char could be removed without visibly affecting the gross surface features such as impasto areas. These results indicate the feasibility for the treatment of the 'Water Lilies' painting.

Miller, Sharon K. R.↗
NASA NTRS1999

Camera-on-a-Chip

Jet Propulsion Laboratory's research on a second generation, solid-state image sensor technology has resulted in the Complementary Metal- Oxide Semiconductor Active Pixel Sensor (CMOS), establishing an alternative to the Charged Coupled Device (CCD). Photobit Corporation, the leading supplier of CMOS image sensors, has commercialized two products of their own based on this technology: the PB-100 and PB-300. These devices are cameras on a chip, combining all camera functions. CMOS "active-pixel" digital image sensors offer several advantages over CCDs, a technology used in video and still-camera applications for 30 years. The CMOS sensors draw less energy, they use the same manufacturing platform as most microprocessors and memory chips, and they allow on-chip programming of frame size, exposure, and other parameters.

Source record↗
NASA NTRS2003

Science Issues Associated with the Use of a Microfluidic Chip Designed Specifically for Protein Crystallization

The Iterative Biological Crystallization team in partnership with Caliper Technologies has produced a prototype microfluidic chip for batch crystallization that has been designed and tested. The chip is designed for the mixing and dispensing of up to five solutions with possible variation of the recipe being delivered to two growth wells. Developments that have led to the successful on-chip crystallization of a few model proteins have required investigative insight into many different areas, including fluid mixing dynamics, surface treatments, quantification and fidelity of reagent delivery. This presentation will encompass the ongoing studies and data accumulated toward these efforts.

Holmes, Anna M.↗
NASA NTRS2004

COTS Ceramic Chip Capacitors: An Evaluation of the Parts and Assurance Methodologies

Commercial-Off-The-Shelf (COTS) multilayer ceramic chip capacitors (MLCCs) are continually evolving to reduce physical size and increase volumetric efficiency. Designers of high reliability aerospace and military systems are attracted to these attributes of COTS MLCCs and would like to take advantage of them while maintaining the high standards for long-term reliable operation they are accustomed io when selecting military qualified established reliability (MIL-ER) MLCCs. However, MIL-ER MLCCs are not available in the full range of small chip sizes with high capacitance as found in today's COTS MLCCs. The objectives for this evaluation were to assess the long-term performance of small case size COTS MLCCs and to identify effective, lower-cost product assurance methodologies. Fifteen (15) lots of COTS X7R dielectric MLCCs from four (4) different manufacturers and two (2) MIL-ER BX dielectric MLCCs from two (2) of the same manufacturers were evaluated. Both 0805 and 0402 chip sizes were included. Several voltage ratings were tested ranging from a high of 50 volts to a low of 6.3 volts. The evaluation consisted of a comprehensive screening and qualification test program based upon MIL-PRF-55681 (i.e., voltage conditioning, thermal shock, moisture resistance, 2000-hour life test, etc.). In addition, several lot characterization tests were performed including Destructive Physical Analysis (DPA), Highly Accelerated Life Test (HALT) and Dielectric Voltage Breakdown Strength. The data analysis included a comparison of the 2000-hour life test results (used as a metric for long-term performance) relative to the screening and characterization test results. Results of this analysis indicate that the long-term life performance of COTS MLCCs is variable -- some lots perform well, some lots perform poorly. DPA and HALT were found to be promising lot characterization tests to identify substandard COTS MLCC lots prior to conducting more expensive screening and qualification tests. The results indicate that lot- specific screening and qualification are still recommended for high reliability applications. One significant and concerning observation is that MIL- type voltage conditioning (100 hours at twice rated voltage, 125 C) was not an effective screen in removing infant mortality parts for the particular lots of COTS MLCCs evaluated.

Brusse, Jay A.↗
NASA NTRS2004

Microtechnology in Space: NASA's Lab-on-a-Chip Applications Development Program

NASA's Marshall Space Flight Center (MSFC) Lab on a Chip Application Development LOCAD) team has worked with microfluidic technology for the past few years in an effort to support NASA's Mission. In that time, such microfluidic based Lab-on-a-Chip (LOC) systems have become common technology in clinical and diagnostic laboratories. The approach is most attractive due to its highly miniaturized platform and ability to perform reagent handling (i-e., dilution, mixing, separation) and diagnostics for multiple reactions in an integrated fashion. LOCAD, along with Caliper Life Sciences has successfully developed the first LOC device for macromolecular crystallization using a workstation acquired specifically for designing custom chips, the Caliper 42. LOCAD uses this, along with a novel MSFC-designed and built workstation for microfluidic development. The team has a cadre of LOC devices that can be used to perform initial feasibility testing to determine the efficacy of the LOC approach for a specific application. Once applicability has been established, the LOCAD team, along with the Army's Aviation and Missile Command microfabrication facility, can then begin to custom design and fabricate a device per the user's specifications. This presentation will highlight the LOCAD team's proven and unique expertise that has been utilized to provide end to end capabilities associated with applying microfluidics for applications that include robotic life detection instrumentation, crew health monitoring and microbial and environmental monitoring for human Exploration.

Monaco, Lisa↗
NASA NTRS1995

CMOS Image Sensors: Electronic Camera On A Chip

Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

Space Microelectronics Image Sensors APS Digital I↗
NASA NTRS1994

Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip

A computer module is disclosed in which a stack of glued together IC memory chips is structurally integrated with a microprocessor chip. The memory provided by the stack is dedicated to the microprocessor chip. The microprocessor and its memory stack may be connected either by glue and/or by solder bumps. The solder bumps can perform three functions--electrical interconnection, mechanical connection, and heat transfer. The electrical connections in some versions are provided by wire bonding.

Carson, John C.↗
NASA NTRS2006

Time of flight system on a chip

A CMOS time-of-flight TOF system-on-a-chip SoC for precise time interval measurement with low power consumption and high counting rate has been developed. The analog and digital TOF chip may include two Constant Fraction Discriminators CFDs and a Time-to-Digital Converter TDC. The CFDs can interface to start and stop anodes through two preamplifiers and perform signal processing for time walk compensation (110). The TDC digitizes the time difference with reference to an off-chip precise external clock (114). One TOF output is an 11-bit digital word and a valid event trigger output indicating a valid event on the 11-bit output bus (116).

Paschalidis, Nicholas P.↗
NASA NTRS2008

Microstructure Evolution in Cut Metal Chips of Ti-6Al-4V

The microstructural evolution following metal cutting was investigated within metal chips of Ti-6Al-4V. Metal cutting was used to impose a high strain rate on the order of approx.10(exp 5)/s within the primary shear zone as the metal was removed from the workpiece. The initial microstructure of the parent material (PM) was composed of a bi-modal microstructure with coarse prior beta grains and equiaxed primary alpha located at the boundaries. After metal cutting, the microstructure of the metal chips showed coarsening of the equiaxed primary alpha grains and beta lamellar. These metallographic findings suggest that the metal chips experienced high temperatures which remained below the beta transus temperature.

Dong, L.↗
NASA NTRS2007

Improved On-Chip Measurement of Delay in an FPGA or ASIC

An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

Chen, Yuan↗
NASA NTRS2007

Microrectenna: A Terahertz Antenna and Rectifier on a Chip

A microrectenna that would operate at a frequency of 2.5 THz has been designed and partially fabricated. The circuit is intended to be a prototype of an extremely compact device that could be used to convert radio-beamed power to DC to drive microdevices (see Figure 1). The microrectenna (see Figure 2) circuit consists of an antenna, a diode rectifier and a DC output port. The antenna consists of a twin slot array in a conducting ground plane (denoted the antenna ground plane) over an enclosed quarter-wavelength-thick resonant cavity (denoted the reflecting ground plane). The circuit also contains a planar high-frequency low-parasitic Schottky-barrier diode, a low-impedance microstrip transmission line, capacitors, and contact beam leads. The entire 3-D circuit is fabricated monolithically from a single GaAs wafer. The resonant cavity renders the slot radiation pattern unidirectional with a half-power beam width of about 65. A unique metal mesh on the rear of the wafer forms the backplate for the cavity but allows the GaAs to be wet etched from the rear surface of the twin slot antennas and ground plane. The beam leads protrude past the edge of the chip and are used both to mount the microrectenna and to make the DC electrical connection with external circuitry. The antenna ground plane and the components on top of it are formed on a 2- m thick GaAs membrane that is grown in the initial wafer MBE (molecular beam epitaxy) process. The side walls of the antenna cavity are not metal coated and, hence, would cause some loss of power; however, the relatively high permittivity (epsilon=13) of the GaAs keeps the cavity modes well confined, without the usual surface-wave losses associated with thick dielectric substrates. The Schottky-barrier diode has the usual submicron dimensions associated with THz operation and is formed in a mesa process above the antenna ground plane. The diode is connected at the midpoint of a microstrip transmission line, which is formed on 1- m-thick SiO (permittivity of 5) laid down on top of the GaAs membrane. The twin slots are fed in phase by this structure. To prevent radio-frequency (RF) leakage past the slot antennas, low-loss capacitors are integrated into the microstrip transmission line at the edges of the slots. The DC current- carrying lines extend from the outer edges of the capacitors, widen approaching the edges of the chip, and continue past the edges of the chip to become the beam leads used in tacking down the devices. The structure provides a self-contained RF to DC converter that works in the THz range.

Siegel, Peter↗
NASA NTRS2012

A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

Suarez, George↗