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A new CMOS active pixel image sensor is reported. The sensor uses a 2.0mue double-poly, double-metal foundry CMOS process and is realized as a 28 x 28 array of 40 mue x 40 mue pixels. The Sensor features TTL compatible voltages, low noise and large dynamic range, and will be useful in machine vision and smart sensor applications.
Si photonics has made rapid progress in research and commercialization in the past two decades. While it started with electronic–photonic integration on Si to overcome the interconnect bottleneck in data communications, Si photonics has now greatly expanded into optical sensing, light detection and ranging (LiDAR), optical computing, and microwave/RF photonics applications. From an applied physics point of view, this perspective discusses novel materials and integration schemes of active Si photonics devices for a broad range of applications in data communications, spectrally extended complementary metal–oxide–semiconductor (CMOS) image sensing, as well as 3D imaging for LiDAR systems. We also present a brief outlook of future synergy between Si photonic integrated circuits and Si CMOS image sensors toward ultrahigh capacity optical I/O, ultrafast imaging systems, and ultrahigh sensitivity lab-on-chip molecular biosensing.
Column-parallel analog-to-digital converters (ADCs) for imagers involve simultaneous operation of many ADCs. Single-slope ADCs are well adapted to this use because of their simplicity. Each ADC contains a comparator, comparing its input signal level to an increasing reference signal (ramp). When the ramp is equal to the input, the comparator triggers a latch that captures an encoded counter value (code). Knowing the captured code, the ramp value and hence the input signal are determined. In a column-parallel ADC, each column contains only the comparator and the latches; the ramp and code generation are shared. In conventional latch or flip-flop circuits, there is an input stage that tracks the input signal, and this stage consumes switching current every time the input changes. With many columns, many bits, and high code rates, this switching current can be substantial. It will also generate noise that may corrupt the analog signals. A latch was designed that does not track the input, and consumes power only at the instant of latching the data value. The circuit consists of two S-R (set-reset) latches, gated by the comparator. One is set by high data values and the other by low data values. The latches are cross-coupled so that the first one to set blocks the other. In order that the input data not need an inversion, which would consume power, the two latches are made in complementary polarity. This requires complementary gates from the comparator, instead of complementary data values, but the comparator only triggers once per conversion, and usually has complementary outputs to begin with. An efficient CMOS (complementary metal oxide semiconductor) implementation of this circuit is shown in the figure, where C is the comparator output, D is the data (code), and Q0 and Q1 are the outputs indicating the capture of a zero or one value. The latch for Q0 has a negative-true set signal and output, and is implemented using OR-AND-INVERT logic, while the latch for Q1 uses positive- true signals and is implemented using AND-OR-INVERT logic. In this implementation, both latches are cleared when the comparator is reset. Two redundant transistors are removed from the reset side of each latch, making for a compact layout. CMOS imagers with column-parallel ADCs have demonstrated high performance for remote sensing applications. With this latch circuit, the power consumption and noise can be further reduced. This innovation can be used in CMOS imagers and very-low-power electronics
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A multiple-step reset process and circuit for resetting a voltage stored on a photodiode of an imaging device. A first stage of the reset occurs while a source and a drain of a pixel source-follower transistor are held at ground potential and the photodiode and a gate of the pixel source-follower transistor are charged to an initial reset voltage having potential less that of a supply voltage. A second stage of the reset occurs after the initial reset voltage is stored on the photodiode and the gate of the pixel source-follower transistor and the source and drain voltages of the pixel source-follower transistor are released from ground potential thereby allowing the source and drain voltages of the pixel source-follower transistor to assume ordinary values above ground potential and resulting in a capacitive feed-through effect that increases the voltage on the photodiode to a value greater than the initial reset voltage.
A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.
Design and characterization of a high-performance multi-acuity, multi-window dynamicaly reconfigurable vision (DRV) CMOS imager for real-time staring vision systems is presented.
Dark current degradation, origins, and annealing behavior after x-ray irradiation are studied in a P-type, hole collecting, backside-illuminated image sensor currently being developed at STMicroelectronics and based on deep-trenched photo-MOS pixels. Different biasing conditions during irradiation, i.e. grounded or biased and sequenced, are compared. The dark current increase with total ionizing dose (TID) and the dark current annealing behavior seem to be driven by the backside interface between the P-epitaxy of the pixels and the ONO stack. Despite still being under development, this pixel architecture already exhibits both very good electro-optical performance and a better radiation hardness than pinned photodiode-based CMOS Image sensors that benefit from the same advanced CIS processing technologies. At high total dose range, the photogate challenges custom Radiation-Hardened-by-Design photodiodes by exhibiting a comparable radiation tolerance while bringing new features such as high-resolution or Correlated Double Sampling.
Jet Propulsion Laboratory's research on a second generation, solid-state image sensor technology has resulted in the Complementary Metal- Oxide Semiconductor Active Pixel Sensor (CMOS), establishing an alternative to the Charged Coupled Device (CCD). Photobit Corporation, the leading supplier of CMOS image sensors, has commercialized two products of their own based on this technology: the PB-100 and PB-300. These devices are cameras on a chip, combining all camera functions. CMOS "active-pixel" digital image sensors offer several advantages over CCDs, a technology used in video and still-camera applications for 30 years. The CMOS sensors draw less energy, they use the same manufacturing platform as most microprocessors and memory chips, and they allow on-chip programming of frame size, exposure, and other parameters.
This study focuses on displacement damage induced dark current and Random Telegraph Signal (RTS) in STMicroelectronics P-Type photogate, a device moving away from the 4T Pinned-Photodiode, with a sensitive volume exclusively made of boron-doped P-type epitaxy, and collecting holes instead of electrons. Results show a typical trend for the shape of dark current and RTS degradation in CMOS Image Sensors with the exception that the measured generation rates seem 2 times smaller than typical literature values in irradiated silicon. Different hypothesis on the origin of this discrepancy are explored.
A family of CMOS-based active pixel image sensors (APS) that are inherently compatible with the integration of on-chip signal processing circuitry is reported.
In this study, we introduce the concept and construction of an innovative Digital Miniature Cathode Ray Magnetometer designed for the precise detection of magnetic fields. This device addresses several limitations inherent to magnetic probes such as D.C. offset, nonlinearity, temperature drift, sensor aging, and the need for frequent recalibration, while capable of operating in a wide range of magnetic fields. The core principle of this device involves the utilization of a charged particle beam as the sensitivity medium. The system leverages the interaction of an electron beam with a scintillator material, which then emits visible light that is captured by an imager. The emitted scintillation light is captured by a CMOS sensor. This sensor not only records the scintillation light but also accurately determines the position of the electron beam, providing invaluable spatial information crucial for magnetic field mapping. The key innovation lies in the combination of electron beam projection, CMOS imager scintillation-based detection, and digital image signal processing. By employing this synergy, the magnetometer achieves remarkable accuracy, sensitivity and dynamic range. The precise position registration enabled by the CMOS sensor further enhances the device’s utility in capturing complex magnetic field patterns, allowing for 2D field mapping. In this work, the optimization of the probe’s performance is tailored for applications related to the characterization of insertion devices in light sources, including undulators.
The Skipper CCD-in-CMOS Parallel Read-Out Circuit V2 (SPROCKET2) is designed to enable high frame rate readout of Skipper CCD-in-CMOS image sensors. The SPROCKET2 pixel is fabricated in a 65 nm CMOS process and occupies a 60$\mu$m $\times$ 60$\mu$m footprint. SPROCKET2 is intended to be heterogeneously integrated with a pixelated Skipper CCD-in-CMOS sensor, such that one readout pixel is connected to a multiplexed array of 16 active image sensor pixels, to match their spatial geometry. Our design benefits from the Skipper CCD-in-CMOS sensor's non-destructive readout capability to achieve exceptionally low noise through multi-sampling and averaging while optimizing for total power consumption. The pixel readout utilizes correlated double sampling to minimize 1/f noise and includes "pile-up" of ten successive samples in the analog domain before digitizing at a rate of 66.7 ksps. Measurement results of in-pixel serial SAR ADC show DNL and INL of ~0. 44 LSB and 0.58 LBS respectively. A large area array of 20,000 SPROCKET2 ADC pixels (multiplexed 1:16 to 320,000 sensor pixels) is currently under test. By reading out data over a 10 Gbps optical link, this pixel design enables a frame rate of $\sim$ 4 kfps for large sensing areas with minimal sensing deadtime. In the highest gain mode, the pixelated ADC has an input-referred resolution of 10$\mu$V with a simulated power consumption of 50$\mu$W. The pixel operates with constant current draw to minimize power-rail crosstalk.
The Skipper CCD-in-CMOS Parallel Read-Out Circuit (SPROCKET) is a mixed-signal front-end design for the readout of Skipper CCD-in-CMOS image sensors. SPROCKET is fabricated in a 65 nm CMOS process and each pixel occupies a 50$\mu$m $\times$ 50$\mu$m footprint. SPROCKET is intended to be heterogeneously integrated with a Skipper-in-CMOS sensor array, such that one readout pixel is connected to a multiplexed array of nine Skipper-in-CMOS pixels to enable massively parallel readout. The front-end includes a variable gain preamplifier, a correlated double sampling circuit, and a 10-bit serial successive approximation register (SAR) ADC. The circuit achieves a sample rate of 100 ksps with 0.48 $\mathrm{e^-_{rms}}$ equivalent noise at the input to the ADC. SPROCKET achieves a maximum dynamic range of 9,000 $e^-$ at the lowest gain setting (or 900 $e^-$ at the lowest noise setting). The circuit operates at 100 Kelvin with a power consumption of 40 $\mu W$ per pixel. A SPROCKET test chip was submitted in September 2022, and test results will be presented at the conference.
In the 1990s, a Jet Propulsion Laboratory team led by Eric Fossum researched ways of improving complementary metal-oxide semiconductor (CMOS) image sensors in order to miniaturize cameras on spacecraft while maintaining scientific image quality. Fossum s team founded a company to commercialize the resulting CMOS active pixel sensor. Now called the Aptina Imaging Corporation, based in San Jose, California, the company has shipped over 1 billion sensors for use in applications such as digital cameras, camera phones, Web cameras, and automotive cameras. Today, one of every three cell phone cameras on the planet feature Aptina s sensor technology.
Recent research results regarding the investigation of CMOS active pixel image sensors (APS) are reported. An investigation of various designs for the pixel, including photogate devices of various geometries and photodiode devices has been performed. Opto-electronic performance including intra-pixel photoresponse maps taken using a focused laser scanning apparatus are presented. Several imaging arrays have also been investigated. A 128 x 128 image sensor has been fabricated and characterized. Both p-well and n-well implementations have been explored. The demonstrated arrays use 2 micron CMOS design rules and have a 40 x 40 micron pixel pitch.
Here we present an optics-free CMOS image sensor that incorporates a novel time-gated dual-photodiode pixel design to allow filter- and lens-less image acquisition of near-infrared-excited (NIR-excited) upconverting nanoparticles. Recent biomedical advances have highlighted the benefits of NIR excitation, but NIR interaction with silicon has remained a challenge, even with high-performance optical blocking filters. Using a secondary diode and a dual-photodiode design, this sensor is able to remove the 100s of mV of NIR background on pixels and bring it down to single-digit mV level, nearing its noise floor of 2.2 mV rms, not achievable with any optical filter. Non-linear effects of background cancellation using the diode pair has been mitigated using an initial one-time pixel-level curve fitting and calibration in a post-processing setting. This imager comprises a highly linear 11 fF metal-oxide-metal (MOM) capacitor and includes integrated angle-selective gratings to reject oblique light and enhance sharpness. Each pixel also includes two distinct correlated double sampling schemes, to remove low frequency flicker noise and systematic offset in the datapath. We demonstrate the performance of this imager using pulsed NIR-excited upconverting nanoparticles on standard United-States-Air-Force (USAF) resolution targets and achieve an SNR of 15 dB, while keeping NIR background below 6 mV. This 36-by-80-pixel array measures only 2.3 mm by 4.8 mm and can be thinned down to 25 µm, allowing it to become surgically compatible with intraoperative instruments and equipment, while remaining optics-free.
A method for implementation of back-illuminated CMOS or CCD imagers. An oxide layer buried between silicon wafer and device silicon is provided. The oxide layer forms a passivation layer in the imaging structure. A device layer and interlayer dielectric are formed, and the silicon wafer is removed to expose the oxide layer.