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This paper gives the status of theoretical and experimental efforts at JPL in the development of environmentally robust (radiation hard and radiation tolerant), ultra-low power, high performance CMOS active pixel sensor (APS) imagers for star tracker/imager applications.
A proposed hybrid ultraviolet (UV) image sensor would comprise a planar membrane array of face-up AlGaN/GaN photodiodes integrated with a complementary metal oxide/semiconductor (CMOS) readout-circuit chip. Each pixel in the hybrid image sensor would contain a UV photodiode on the AlGaN/GaN membrane, metal oxide/semiconductor field-effect transistor (MOSFET) readout circuitry on the CMOS chip underneath the photodiode, and a metal via connection between the photodiode and the readout circuitry (see figure). The proposed sensor design would offer all the advantages of comparable prior CMOS active-pixel sensors and AlGaN UV detectors while overcoming some of the limitations of prior (AlGaN/sapphire)/CMOS hybrid image sensors that have been designed and fabricated according to the methodology of flip-chip integration. AlGaN is a nearly ideal UV-detector material because its bandgap is wide and adjustable and it offers the potential to attain extremely low dark current. Integration of AlGaN with CMOS is necessary because at present there are no practical means of realizing readout circuitry in the AlGaN/GaN material system, whereas the means of realizing readout circuitry in CMOS are well established. In one variant of the flip-chip approach to integration, an AlGaN chip on a sapphire substrate is inverted (flipped) and then bump-bonded to a CMOS readout circuit chip; this variant results in poor quantum efficiency. In another variant of the flip-chip approach, an AlGaN chip on a crystalline AlN substrate would be bonded to a CMOS readout circuit chip; this variant is expected to result in narrow spectral response, which would be undesirable in many applications. Two other major disadvantages of flip-chip integration are large pixel size (a consequence of the need to devote sufficient area to each bump bond) and severe restriction on the photodetector structure. The membrane array of AlGaN/GaN photodiodes and the CMOS readout circuit for the proposed image sensor would be fabricated separately.
A high-performance computational imager based on integration of CMOS active pixel imager array with on-chip signal processing and control via a new column-parallel architecture is presented.
This presentation gives the status of theoretical and experimental efforts at JPL, in the development of environmentally robust (rad hard and rad tolerant), ultra-low power, high performance cmos active pixel sensor (aps) imagers for star tracker/imager applications.
We present architecture, process design and results from test pixels of a new Active Pixel Sensor (APS) imager implemented in 0.8 um SOI-CMOS technology.
An integrated CMOS semiconductor imaging device having two modes of operation that can be performed simultaneously to produce an output image and provide information of a brightest or darkest pixel in the image.
The NASA Electronic Parts and Packaging (NEPP) Program Sensor Technology Commercial Sensor Survey task is geared toward benefiting future NASA space missions with low-cost, short-duty-cycle, visible-wavelength imaging needs. Such applications could include imaging for educational outreach purposes or short surveys of spacecraft, planetary, or lunar surfaces. Under the task, inexpensive, low-power, commercial grade CMOS sensors were surveyed in fiscal year 2007 (FY07), and three sensors were selected and tested for total ionizing dose (TID) and displacement damage dose (DDD) tolerance in fiscal year 2008 (FY08). The selected sensors had to meet selection criteria chosen to support small, low-mass cameras that produce good resolution color images. The commercial CMOS sensors tested under the task in FY08 showed very promising response to typical outreach and survey camera TID and DDD levels. In fiscal year 2009 (FY09), the survey was broadened to include two additional, similar sensor products. This compendium provides results for all radiation testing performed on the Micron and OmniVision sensors that were selected for radiation tolerance testing in FY08 and FY09.
Vision sensors like CMOS and CCD cameras are often used for in-process monitoring of melt pools in laser-based additive and welding processes, but they require transferring large amounts of data and computational processing resources. Event-based neuromorphic imagery, on the other hand, detects only the change in pixel intensity, thus potentially reducing the data amount and latency. With an event imager, this study develops a framework for melt pool condition classification, including image construction, time scale selection, optimal pixel selection, and sparse classification, to achieve a highly memory-efficient scheme. These are based on sparse sensing techniques with singular value decomposition (SVD) and QR pivoting, the two fundamental matrix transformations for linear dimensionality reduction. The framework is then validated by classifying a controlled experiment by exciting various mode shapes of liquid gallium pools of varying depths (3, 6, and 8 mm). At 200 pixels, the classifier can reach overall accuracy of 75%, while at 2000 pixels (0.013% of the total possible pixels), the accuracy is nearly 90% (89.86%). At the same number of pixels, random selection can only achieve 46% and 67%, respectively. The memory savings of the sparsely sampled event data compared to a conventional imager is about 500 times. In addition to performance, implementation and limitations of the framework are also discussed.
A high resolution CMOS imaging system especially suitable for use in a periscope head. The imaging system includes a sensor head for scene acquisition, and a control apparatus inclusive of distributed processors and software for device-control, data handling, and display. The sensor head encloses a combination of wide field-of-view CMOS imagers and narrow field-of-view CMOS imagers. Each bank of imagers is controlled by a dedicated processing module in order to handle information flow and image analysis of the outputs of the camera system. The imaging system also includes automated or manually controlled display system and software for providing an interactive graphical user interface (GUI) that displays a full 360-degree field of view and allows the user or automated ATR system to select regions for higher resolution inspection.
This paper describes the technology, design features and reliability characterization methodology of a CMOS Active Pixel Sensor. Both overall chip reliability and pixel reliability are projected for the imagers.
A semiconductor imaging system preferably having an active pixel sensor array compatible with a CMOS fabrication process. Color-filtering elements such as polymer filters and wavelength-converting phosphors can be integrated with the image sensor.
This paper presents a new technique for implementing a low-power CMOS imager with simultaneous on-chip computation of the difference and sum of two successive frames.
This paper presents a new technique for implementing a low-power CMOS imager with simultaneous on-chip computation of the difference and summ of two successive frames.
CMOS active pixel sensors (APS) allow the flexibility of placing signal processing circuitry on the imaging focal plane. The multiresolution CMOS APS can perform block averaging on-chip to eliminate the off-chip software intensive image processing. This 128 x 128 APS array can be read out at any user-defined resolution by configuring a set of digital shift registers. The resolution frame rate is 30 Hz with higher rates for all other image resolutions.
An image sensor includes pixels formed on a semiconductor substrate. Each pixel includes a photoactive region in the semiconductor substrate, a sense node, and a power supply node. A first electrode is disposed near a surface of the semiconductor substrate. A bias signal on the first electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the sense node. A second electrode is disposed near the surface of the semiconductor substrate. A bias signal on the second electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the power supply node. The image sensor includes a controller that causes bias signals to be provided to the electrodes so that photocharges generated in the photoactive region are accumulated in the photoactive region during a pixel integration period, the accumulated photocharges are transferred to the sense node during a charge transfer period, and photocharges generated in the photoactive region are transferred to the power supply node during a third period without passing through the sense node. The imager can operate at high shutter speeds with simultaneous integration of pixels in the array. High quality images can be produced free from motion artifacts. High quantum efficiency, good blooming control, low dark current, low noise and low image lag can be obtained.
AstroPix is a high-voltage CMOS (HV-CMOS) monolithic active pixel sensor originally developed to enable precision gamma-ray imaging and spectroscopy in the medium-energy regime (~100 keV–100 MeV) based on the groundwork laid by ATLASpix and MuPix. It features a 500 μm pixel pitch, in-pixel amplification and digitization, and low power consumption (~3-4 mW/cm2), making it scalable for large-area, multilayer telescope detector planes. The detectors have a designed dynamic range of 25 keV to 700 keV. With these features, AstroPix meets the requirements of future space-based high-energy telescopes and the imaging layers of the Barrel Imaging Calorimeter (BIC) in the Electron-Proton/Ion Collider (ePIC) detector at the future Electron-Ion Collider (EIC). For the space-based payload, AstroPix is being integrated into sounding rocket and balloon payloads to demonstrate the technical readiness of the devices. For BIC, AstroPix-based imaging layers interleaved within the lead/scintillating-fiber (Pb/SciFi) sampling calorimeter provide granular shower imaging, enabling key performance features such as electron/pion or gamma/neutral pion separation. As part of the ongoing detector R&D efforts, we have been testing various AstroPix_v3 configurations: the single chip, a quad-chip assembly, a three-layer stack of quad chips, and a 9-chip module that represents the smallest prototype unit of the BIC imaging layer. This presentation will highlight recent performance test results from these AstroPix detector configurations.
This report surveys different technologies and approaches to realize sensors for image warping. The goal is to study the feasibility, technical aspects, and limitations of making an electronic camera with special geometries which implements certain transformations for image warping. This work was inspired by the research done by Dr. Juday at NASA Johnson Space Center on image warping. The study has looked into different solid-state technologies to fabricate image sensors. It is found that among the available technologies, CMOS is preferred over CCD technology. CMOS provides more flexibility to design different functions into the sensor, is more widely available, and is a lower cost solution. By using an architecture with row and column decoders one has the added flexibility of addressing the pixels at random, or read out only part of the image.
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