Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “Arrays”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 73 records · Page 4

Automated Array Assembly, Phase 2. Low-cost Solar Array Project, Task 4

Work was done to verify the technological readiness of a select process sequence with respect to satisfying the Low Cost Solar Array Project objectives of meeting the designated goals of $.50 per peak watt in 1986 (1975 dollars). The sequence examined consisted of: (1) 3 inches diameter as-sawn Czochralski grown 1:0:0 silicon, (2) texture etching, (3) ion implanting, (4) laser annealing, (5) screen printing of ohmic contacts and (6) sprayed anti-reflective coatings. High volume production projections were made on the selected process sequence. Automated processing and movement of hardware at high rates were conceptualized to satisfy the PROJECT's 500 MW/yr capability. A production plan was formulated with flow diagrams integrating the various processes in the cell fabrication sequence.

Lopez, M.↗

Array Automated Assembly Task Low Cost Silicon Solar Array Project, Phase 2

Progress in the development of solar cells and module process steps for low-cost solar arrays is reported. Specific topics covered include: (1) a system to automatically measure solar cell electrical performance parameters; (2) automation of wafer surface preparation, printing, and plating; (3) laser inspection of mechanical defects of solar cells; and (4) a silicon antireflection coating system. Two solar cell process steps, laser trimming and holing automation and spray-on dopant junction formation, are described.

Rhee, S. S.↗

Electron lithography STAR design guidelines. Part 3: The mosaic transistor array applied to custom microprocessors. Part 4: Stores logic arrays, SLAs implemented with clocked CMOS

The Mosaic Transistor Array is an extension of the STAR system developed by NASA which has dedicated field cells designed to be specifically used in semicustom microprocessor applications. The Sandia radiation hard bulk CMOS process is utilized in order to satisfy the requirements of space flights. A design philosophy is developed which utilizes the strengths and recognizes the weaknesses of the Sandia process. A style of circuitry is developed which incorporates the low power and high drive capability of CMOS. In addition the density achieved is better than that for classic CMOS, although not as good as for NMOS. The basic logic functions for a data path are designed with compatible interface to the STAR grid system. In this manner either random logic or PLA type structures can be utilized for the control logic.

Trotter, J. D.↗

Channel assignments and array gain bounds for the Ka-band array feed compensation system

The performance of a real-time digital combining system for use with array feeds was considered previously. The purpose of the combining operation is to recover signal to noise ratio (SNR) losses due to antenna deformations and atmospheric effects. Previously, arbitrary signal powers and noise variances were assumed, but no attempt was made to match the receiver channels to the available signal powers. It is shown that for any signal power and noise variance distribution, a best channel assignment exists that maximizes the combined SNR in the limit of vanishingly small combining losses. This limit can be approached in practice by observing sufficiently many samples. Specific signal power and noise variance distributions are considered, and it is shown that even relatively noisy channels can be used effectively to recover SNR losses resulting from signals diverted out of a high-quality channel by antenna deformations.

Vilnrotter, V. A.↗

Development of Hybrid Sensor Arrays for Sensor Arrays for Simultaneous Measurement of Pressure and Shear Stress Distribution

This document reports on the progress in developing hybrid sensors for the simultaneous measurement of pressure and shear stress. The key feature for the success of the proposed hybrid sensor array is the ability to deposit Cu-Ni alloy with proper composition (55 - 45) on a silicon wafer to form a strain gage. This alloy strain gage replaces the normally used Si strain gages in MEMS, which are highly nonlinear and temperature dependent. The copper nickel, with proper composition (55 - 45), was successfully deposited on a silicon wafer with a few trials during this period of the project. Pictures of the Cu-Ni alloy strain gage and the x-ray spectra indicating the composition are shown. The planned tests are also reviewed.

Source record↗