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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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So far, the most sensitive heterodyne receivers in the millimeter-wave and submillimeter-wave frequency ranges have used the mixing response of the quasiparticle currents in SIS tunnel junctions.
This presentation discusses the effects of ionizing radiation on single event transients (SETs) in circuits. The exposure of integrated circuits to ionizing radiation changes electrical parameters. The total ionizing dose effect is observed in both complementary metal-oxide-semiconductor (CMOS) and bipolar circuits. In bipolar circuits, transistors exhibit grain degradation, while in CMOS circuits, transistors exhibit threshold voltage shifts. Changes in electrical parameters can cause changes in single event upset(SEU)/SET rates. Depending on the effect, the rates may increase or decrease. Therefore, measures taken for SEU/SET mitigation might work at the beginning of a mission but not at the end following TID exposure. The effect of TID on SET rates should be considered if SETs cannot be tolerated.
Efficient onboard data compression can reduce the data volume from hyperspectral imagers on NASA and DoD spacecraft in order to return as much imagery as possible through constrained downlink channels. Lossless compression is important for signature extraction, object recognition, and feature classification capabilities. To provide onboard data compression, a hardware implementation of a lossless hyperspectral compression algorithm was developed using a field programmable gate array (FPGA). The underlying algorithm is the Fast Lossless (FL) compression algorithm reported in Fast Lossless Compression of Multispectral- Image Data (NPO-42517), NASA Tech Briefs, Vol. 30, No. 8 (August 2006), p. 26 with the modification reported in Lossless, Multi-Spectral Data Comressor for Improved Compression for Pushbroom-Type Instruments (NPO-45473), NASA Tech Briefs, Vol. 32, No. 7 (July 2008) p. 63, which provides improved compression performance for data from pushbroom-type imagers. An FPGA implementation of the unmodified FL algorithm was previously developed and reported in Fast and Adaptive Lossless Onboard Hyperspectral Data Compression System (NPO-46867), NASA Tech Briefs, Vol. 36, No. 5 (May 2012) p. 42. The essence of the FL algorithm is adaptive linear predictive compression using the sign algorithm for filter adaption. The FL compressor achieves a combination of low complexity and compression effectiveness that exceeds that of stateof- the-art techniques currently in use. The modification changes the predictor structure to tolerate differences in sensitivity of different detector elements, as occurs in pushbroom-type imagers, which are suitable for spacecraft use. The FPGA implementation offers a low-cost, flexible solution compared to traditional ASIC (application specific integrated circuit) and can be integrated as an intellectual property (IP) for part of, e.g., a design that manages the instrument interface. The FPGA implementation was benchmarked on the Xilinx Virtex IV LX25 device, and ported to a Xilinx prototype board. The current implementation has a critical path of 29.5 ns, which dictated a clock speed of 33 MHz. The critical path delay is end-to-end measurement between the uncompressed input data and the output compression data stream. The implementation compresses one sample every clock cycle, which results in a speed of 33 Msample/s. The implementation has a rather low device use of the Xilinx Virtex IV LX25, making the total power consumption of the implementation about 1.27 W.
New power control technologies, such as smart power (SP) and power integrated circuits (PICs), are being developed to decrease cost and increase performance of photovoltaic power arrays.
The GEO-CAPE mission described in NASA's Earth Science and Applications Decadal Survey requires high spatial, temporal, and spectral resolution measurements to monitor and characterize the rapidly changing chemistry of the troposphere over North and South Americas. High-frame-rate focal plane arrays (FPAs) with many pixels are needed to enable such measurements. A high-throughput digital detector readout integrated circuit (ROIC) that meets the GEO-CAPE FPA needs has been developed, fabricated, and tested. The ROIC is based on an innovative charge integrating, fast, high-precision analog-to-digital circuit that is built into each pixel. The 128×128-pixel ROIC digitizes all 16,384 pixels simultaneously at frame rates up to 16 kHz to provide a completely digital output on a single integrated circuit at an unprecedented rate of 262 million pixels per second. The approach eliminates the need for off focal plane electronics, greatly reducing volume, mass, and power compared to conventional FPA implementations. A focal plane based on this ROIC will require less than 2 W of power on a 1×1-cm integrated circuit. The ROIC is fabricated of silicon using CMOS technology. It is designed to be indium bump bonded to a variety of detector materials including silicon PIN diodes, indium antimonide (InSb), indium gallium arsenide (In- GaAs), and mercury cadmium telluride (HgCdTe) detector arrays to provide coverage over a broad spectral range in the infrared, visible, and ultraviolet spectral ranges.
Thermal, life, and mechanical environment effects on solid integrated circuits of diffused silicon
Thin film capacitor research and development - deposition of materials for capacitor dielectrics, and materials compatibility with integrated circuits
As integrated circuits continue to scale toward the atomic limit, bottom-up processes, such as epitaxial growth, have come to feature prominently in their fabrication. At the same time, chemistry has developed highly tunable molecular semiconductors that can perform the functions of ultimately scaled circuit components. Hybrid techniques that integrate programmable structures comprising molecular components into devices however are sorely lacking. Here we demonstrate a wafer-scale process that directs the localization of a conductive polymer, M w = 20 kg mol –1 polyaniline, from dilute solutions into 50 nm vertical nanogap device architectures using electric-field-driven self-assembly. The resulting metal–polymer–metal junctions were characterized by electron microscopy, Raman spectroscopy and transport measurements demonstrating that our technique is highly selective, assembling conductive polymers only in electrically activated nanogaps. Our results represent a step toward scalable hybrid nanoelectronics that seamlessly integrate established lithographic top-down fabrication with bottom-up synthesized molecular functional circuit components.
This paper describes total ionizing dose (TID) test results performed at JPL. Bipolar and BiCMOS device samples were tested exhibiting significant degradation and failures at different irradiation levels. Linear technology which is susceptible to low-dose dependency (ELDRS) exhibited greater damage for devices tested under zero bias condition.
Here we show that the integrable Lindblad superoperators found recently can be used to build integrable nonunitary quantum circuits with two-site gates by demonstrating that the R(SIC) matrices are completely positive and trace preserving. Using the bond-site transformation, we obtain the corresponding integrable nonunitary quantum circuits with three-site gates. When restricted to the diagonals of the density matrix, these quantum models reduce to integrable classical cellular automata. This approach may pave the way for a systematic construction of circuits.
Improved nondestructive test methods using infrared radiation and radioisotope tracers for seal defects and integrated circuit quality control
Evaluation and testing of suitability of using integrated circuits in Saturn IB and launch vehicle data adapter
Small lots of special-purpose integrated circuits are fabricated from standard transitor arrays. Folded linear order of cells minimzes interconnection length and puts cell in juxtaposition. Cell-placement technique is carried out via computer program.
Signal conditioner was designed which can condition dc signals over range of + or - volts. It is lighter, has lower initial and maintenance costs, and higher reliability than conventional discrete circuit designs. System incorporates linear integrated circuits in conjunction with hybrid, thin film circuit technology to achieve high degree of circuit miniaturization.
Gyrator circuit is especially useful in integrated circuits for such purposes as simulating inductors with capacitors. Circuit is adaptable to semifloating and full floating configurations. It has excellent response, low power consumption, and high energy storage capacity.
Neither external bias nor energy-storage components required. Three-terminal semiconductor switching circuit features high switching speed, extremely high turnoff safe operating area (area in current-vs-voltage plane), moderately low forward ("on"-state) voltage drop, and efficient utilization of silicon in design of components. Includes gate-turn-off thyristor (GTO) and low-voltage (low-on-resistance) field-effect transistor (FET-1) connected in series to form cascode pair. Made of commercially available, discrete components, as hybrid circuit package or as monolithic integrated circuit.
An overview of the growth and characterization of epitaxial insulators on semiconductors is presented. The potential applications include semiconductor-on-insulator structures, three-dimensional and/or high-density integrated circuits, optoelectronic applications such as integrated waveguides and improved gate insulators. The growth and physical characterization of epitaxial fluorides on semiconductors are discussed. Consideration is also given to the epitaxial overgrowth of epitaxial metal layers with CaF2 as well as to the formation of a novel superlattice of Ca particles in epitaxial CaF2.
Packaging system houses and connects control circuitry mounted on circuit boards within shoulder, upper section, and lower section of seven-degree-of-freedom robot arm. Has modular design that incorporates surface-mount technology, multilayer circuit boards, large-scale integrated circuits, and multi-layer flat cables between sections for compactness. Three sections of robot arm contain circuit modules in form of stardardized circuit boards. Each module contains two printed-circuit cards, one of each face.