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At least 703 records · Page 39

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NASA NTRS1975

Optimum quantisers for a Gaussian input probability density and for the magnitude-error distortion measure

The parameters of non-uniform and uniform quantizers up to ten bits of quantization, optimum for a Gaussian input probability and for the magnitude-error distortion criterion are computed. Optimum quantizers must be understood as quantizers with minimum distortion. The numerical method used for the optimization converges relatively rapidly. The comparison between optimum non-uniform quantizers and optimum uniform quantizers is made.

Demaret, J. C.↗

DOE OSTI2023

Digital encoding algorithm for pixelated detectors

A detector for imaging and efficiently digitizing a spatial distribution of photon flux includes pixel circuits that compressively encode pixel values generated by integrated analog to digital converters (ADCs). On-pixel digital compression circuits (DCCs) implement compression to increase continuous frame rate by reducing the number of bits per pixel while keeping quantization error below Poisson noise. Several mapping algorithms for photon-counting and charge-integrating detectors and compact digital logic implementations are presented.

Hammer, Michael P.↗

NASA NTRS1977

Theoretical and subjective bit assignments in transform picture

It is shown that all combinations of symmetrical input distributions with difference distortion measures give a bit assignment rule identical to the well-known rule for a Gaussian input distribution with mean-square error. Published work is examined to show that the bit assignment rule is useful for transforms of full pictures, but subjective bit assignments for transform picture coding using small block sizes are significantly different from the theoretical bit assignment rule. An intuitive explanation is based on subjective design experience, and a subjectively obtained bit assignment rule is given.

Jones, H. W., Jr.↗

NASA NTRS1995

Image data compression having minimum perceptual error

A method for performing image compression that eliminates redundant and invisible image components is described. The image compression uses a Discrete Cosine Transform (DCT) and each DCT coefficient yielded by the transform is quantized by an entry in a quantization matrix which determines the perceived image quality and the bit rate of the image being compressed. The present invention adapts or customizes the quantization matrix to the image being compressed. The quantization matrix comprises visual masking by luminance and contrast techniques and by an error pooling technique all resulting in a minimum perceptual error for any given bit rate, or minimum bit rate for a given perceptual error.

Watson, Andrew B.↗

DOE OSTI2022

Active readout-error mitigation

Mitigating errors is a significant challenge for near-term quantum computers. One of the most important sources of errors is related to the readout of the quantum state into a classical bit stream. A variety of techniques have been proposed to mitigate these errors with post-hoc corrections. Here, we propose a complementary scheme to actively reduce readout errors on a shot-by-shot basis by encoding single qubits, immediately prior to readout, into multiqubit states. The computational resources of our technique are independent of the circuit depth and are compatible with the error rates and connectivity of many current devices. We analyze the potential of our approach using two types of error-correcting codes, and, as a proof of principle, we demonstrate an 80% improvement in readout error on the IBMQ Mumbai quantum computer.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2022

Experimental demonstration of continuous quantum error correction

The storage and processing of quantum information are susceptible to external noise, resulting in computational errors. A powerful method to suppress these effects is quantum error correction. Typically, quantum error correction is executed in discrete rounds, using entangling gates and projective measurement on ancillary qubits to complete each round of error correction. Here we use direct parity measurements to implement a continuous quantum bit-flip correction code in a resource-efficient manner, eliminating entangling gates, ancillary qubits, and their associated errors. An FPGA controller actively corrects errors as they are detected, achieving an average bit-flip detection efficiency of up to 91%. Furthermore, the protocol increases the relaxation time of the protected logical qubit by a factor of 2.7 over the relaxation times of the bare comprising qubits. Our results showcase resource-efficient stabilizer measurements in a multi-qubit architecture and demonstrate how continuous error correction codes can address challenges in realizing a fault-tolerant system.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

NASA NTRS1971

A comparison of orthogonal transformations for digital speech processing.

Discrete forms of the Fourier, Hadamard, and Karhunen-Loeve transforms are examined for their capacity to reduce the bit rate necessary to transmit speech signals. To rate their effectiveness in accomplishing this goal the quantizing error (or noise) resulting for each transformation method at various bit rates is computed and compared with that for conventional companded PCM processing. Based on this comparison, it is found that Karhunen-Loeve provides a reduction in bit rate of 13.5 kbits/s, Fourier 10 kbits/s, and Hadamard 7.5 kbits/s as compared with the bit rate required for companded PCM. These bit-rate reductions are shown to be somewhat independent of the transmission bit rate.

Campanella, S. J.↗

NASA NTRS1989

High rate concatenated coding systems using bandwidth efficient trellis inner codes

High-rate concatenated coding systems with bandwidth-efficient trellis inner codes and Reed-Solomon (RS) outer codes are investigated for application in high-speed satellite communication systems. Two concatenated coding schemes are proposed. In one the inner code is decoded with soft-decision Viterbi decoding, and the outer RS code performs error-correction-only decoding (decoding without side information). In the other, the inner code is decoded with a modified Viterbi algorithm, which produces reliability information along with the decoded output. In this algorithm, path metrics are used to estimate the entire information sequence, whereas branch metrics are used to provide reliability information on the decoded sequence. This information is used to erase unreliable bits in the decoded output. An errors-and-erasures RS decoder is then used for the outer code. The two schemes have been proposed for high-speed data communication on NASA satellite channels. The rates considered are at least double those used in current NASA systems, and the results indicate that high system reliability can still be achieved.

Deng, Robert H.↗

NASA NTRS1985

Encoding Scheme Reduces Hardware Requirements

Shift register time-shared in proposed error-correcting code for tape-storage systems. Error-correcting code logic for blocks of 256-bit data words implemented by 14-stage-time-shared shift register, two 4,096bit RAM's and logic gates. Encoding and decoding logic implement generator polynomial that defines error-correcting code, and error correction based on algorithm also implemented by logic.

Sasnowitz, H.↗

NASA NTRS1995

Reducing Truncation Error In Integer Processing

Improved method of rounding off (truncation of least-significant bits) in integer processing of data devised. Provides for reduction, to extremely low value, of numerical bias otherwise generated by accumulation of truncation errors from many arithmetic operations. Devised for use in integer signal processing, in which rescaling and truncation usually performed to reduce number of bits, which typically builds up in sequence of operations. Essence of method to alternate direction of roundoff (plus, then minus) on alternate occurrences of truncated values contributing to bias.

Thomas, J. Brooks↗

NASA NTRS1974

Input-output, expandable-parity network

Large-scale integrated circuit generates and checks parity of four eight-bit registers. In addition, circuit will indicate by output signal whether parity error exists. Circuit can also generate or check parity of words up to 32 bits. This is done by making appropriate internal wiring connections on the large-scale integrated chip.

Mckevitt, J. F., III↗

NASA NTRS2010

Scaled CMOS Technology Reliability Users Guide

The desire to assess the reliability of emerging scaled microelectronics technologies through faster reliability trials and more accurate acceleration models is the precursor for further research and experimentation in this relevant field. The effect of semiconductor scaling on microelectronics product reliability is an important aspect to the high reliability application user. From the perspective of a customer or user, who in many cases must deal with very limited, if any, manufacturer's reliability data to assess the product for a highly-reliable application, product-level testing is critical in the characterization and reliability assessment of advanced nanometer semiconductor scaling effects on microelectronics reliability. A methodology on how to accomplish this and techniques for deriving the expected product-level reliability on commercial memory products are provided.Competing mechanism theory and the multiple failure mechanism model are applied to the experimental results of scaled SDRAM products. Accelerated stress testing at multiple conditions is applied at the product level of several scaled memory products to assess the performance degradation and product reliability. Acceleration models are derived for each case. For several scaled SDRAM products, retention time degradation is studied and two distinct soft error populations are observed with each technology generation: early breakdown, characterized by randomly distributed weak bits with Weibull slope (beta)=1, and a main population breakdown with an increasing failure rate. Retention time soft error rates are calculated and a multiple failure mechanism acceleration model with parameters is derived for each technology. Defect densities are calculated and reflect a decreasing trend in the percentage of random defective bits for each successive product generation. A normalized soft error failure rate of the memory data retention time in FIT/Gb and FIT/cm2 for several scaled SDRAM generations is presented revealing a power relationship. General models describing the soft error rates across scaled product generations are presented. The analysis methodology may be applied to other scaled microelectronic products and their key parameters.

Microelectronics Reliability↗

DOE OSTI2021

Experimental decoy-state Bennett-Brassard 1984 quantum key distribution through a turbulent channel

In free-space quantum key distribution (QKD) in turbulent conditions, scattering and beam wandering cause intensity fluctuations which decrease the detected signal-to-noise ratio. This effect can be mitigated by rejecting received bits when the channel's transmittance is below a threshold. Thus, the overall error rate is reduced and the secure key rate increases despite the deletion of bits. In this work, we implement recently proposed selection methods focusing on the prefixed-threshold real-time selection (P-RTS) where a cutoff can be chosen prior to data collection and independently of the transmittance distribution. We perform finite-size decoy-state Bennett-Brassard 1984 QKD in a laboratory setting where we simulate the atmospheric turbulence using an acousto-optical modulator. We show that P-RTS can yield considerably higher secure key rates for a wide range of the atmospheric channel parameters. In addition, we evaluate the performance of the P-RTS method for a realistically finite sample size. We demonstrate that a near-optimal selection threshold can be predetermined even with imperfect knowledge of the channel transmittance distribution parameters.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

NASA NTRS2011

Reconfigurable Microwave Phase Delay Element for Frequency Reference and Phase-Shifter Applications

A technique was developed to provide a reconfigurable high-precision micro - wave electrical phase delay for resonators and phase shifters. The invention employs multiple branches of transmission lines with open-ended or ground-ended terminations as configurable bits or digits. This technique minimizes the errors due to limited precision of switching devices. In addition, the proposed linear analytical approach significantly produces a much simpler design than that of other prior inventions at the time of this reporting. Microwave components such as filters, phase delay elements, or resonators require a method that can accurately adjust their frequency responses. Most tuning techniques offer very wide frequency tuning range; however, it is often difficult and expensive to tune their response in a very narrow operating frequency, especially when the tuning element reaches its minimum discrete step due to fabrication tolerances. The problem becomes worse as the operating frequency is in mm-wave frequency range (>26 GHz). The electrical tuning sensitivity of a microwave line is dependent on the position of the tuning element with respect to the reference termination. By placing this tuning element away from this reference with the main transmission line connecting the two elements together the sensitivity of the tuning element can change significantly. This concept can be used in the system that requires multiple tuning sensitivities. In this case, multiple tuning branches are superimposed in the main transmission line. The proposed invention allows the transmission-line electrical length to be accurately programmed using switching elements that have limited accuracy. The invention consists of multiple branches of transmission lines connected to discrete switching devices with open-ended terminations. They are used as discrete tuning elements. These elements are connected to the main microwave transmission line and are separated by a well-defined electrical degree spacing. Each branch is programmed to have different electrical degree sensitivity, such as a combination of discrete steps in each branch, which results in a reflective line with a unique effective phase response. To reduce the number of switching devices, it is desirable to program the devices in binary configuration where each branch represents one bit in the base-2 number system. This invention allows the transmission line electrical length to be tuned precisely with customizable sensitivity based on the known sensitivity of the base tuning circuit. The tuning resolution is dependent on the distance among tuning branches.

Hsieh, Wen-Ting↗

DOE OSTI2025

Traceable random numbers from a non-local quantum advantage

The unpredictability of random numbers is fundamental to both digital security and applications that fairly distribute resources. However, existing random number generators have limitations—the generation processes cannot be fully traced, audited and certified to be unpredictable. The algorithmic steps used in pseudorandom number generators are auditable, but they cannot guarantee that their outputs were a priori unpredictable given knowledge of the initial seed. Device-independent quantum random number generators can ensure that the source of randomness was unknown beforehand, but the steps used to extract the randomness are vulnerable to tampering. Here we demonstrate a fully traceable random number generation protocol based on device-independent techniques. Our protocol extracts randomness from unpredictable non-local quantum correlations, and uses distributed intertwined hash chains to cryptographically trace and verify the extraction process. This protocol forms the basis for a public traceable and certifiable quantum randomness beacon that we have launched. Over the first 40 days of operation, we completed the protocol 7,434 out of 7,454 attempts—a success rate of 99.7%. Each time the protocol succeeded, the beacon emitted a pulse of 512 bits of traceable randomness. The bits are certified to be uniform with error multiplied by actual success probability bounded by 2−64. Further, the generation of certifiable and traceable randomness represents a public service that operates with an entanglement-derived advantage over comparable classical approaches.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS1975

System applications of the fault tolerant memory

Conventional memory technologies currently employed in aerospace applications contribute at least fifty percent to system unreliability (where the system includes CPU, I/O and memory). A fault tolerant memory performs both error correction and memory replacement at the bit plane level. To determine the effects of system design of using a fault tolerant memory in space applications, analysis was performed to determine tradeable hardware configurations that meet the reliability goals of each program. The candidate configurations, which included redundant elements of the computer system with both conventional and fault tolerant memories, were then traded in terms of selection criteria of cost, weight, volume, and power. These trade studies demonstrated that a fault tolerant memory provided significant advantages in terms of cost, weight, and volume. The memory selected for this analysis was a recently developed five fault tolerant memory.

Murphy, L. J.↗

NASA NTRS1983

Rounding Technique for High-Speed Digital Signal Processing

Arithmetic technique facilitates high-speed rounding of 2's complement binary data. Conventional rounding of 2's complement numbers presents problems in high-speed digital circuits. Proposed technique consists of truncating K + 1 bits then attaching bit in least significant position. Mean output error is zero, eliminating introducing voltage offset at input.

Wechsler, E. R.↗

NASA NTRS1991

Digital visual communications using a Perceptual Components Architecture

The next era of space exploration will generate extraordinary volumes of image data, and management of this image data is beyond current technical capabilities. We propose a strategy for coding visual information that exploits the known properties of early human vision. This Perceptual Components Architecture codes images and image sequences in terms of discrete samples from limited bands of color, spatial frequency, orientation, and temporal frequency. This spatiotemporal pyramid offers efficiency (low bit rate), variable resolution, device independence, error-tolerance, and extensibility.

Watson, Andrew B.↗