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The current status of semiconductor, magnetic, and optical memory technologies is described. Projections based on these research activities planned for the shot term are presented. Conceptual designs of specific memory buffer pplications employing bipola, CMOS, GaAs, and Magnetic Bubble devices are discussed.
An apparatus for processing multidimensional data with strong spatial characteristics, such as raw image data, characterized by a large number of parallel data streams in an ordered array is described. It comprises a large number (e.g., 16,384 in a 128 x 128 array) of parallel processing elements operating simultaneously and independently on single bit slices of a corresponding array of incoming data streams under control of a single set of instructions. Each of the processing elements comprises a bidirectional data bus in communication with a register for storing single bit slices together with a random access memory unit and associated circuitry, including a binary counter/shift register device, for performing logical and arithmetical computations on the bit slices, and an I/O unit for interfacing the bidirectional data bus with the data stream source. The massively parallel processor architecture enables very high speed processing of large amounts of ordered parallel data, including spatial translation by shifting or sliding of bits vertically or horizontally to neighboring processing elements.
The development of an advanced space flight computer for real time embedded deep space applications which embodies the lessons learned on Galileo and modern computer technology is described. The requirements are listed and the design implementation that meets those requirements is described. The development of SPACE-16 (Spaceborne Advanced Computing Engine) (where 16 designates the databus width) was initiated to support the MM2 (Marine Mark 2) project. The computer is based on a radiation hardened emulation of a modern 32 bit microprocessor and its family of support devices including a high performance floating point accelerator. Additional custom devices which include a coprocessor to improve input/output capabilities, a memory interface chip, and an additional support chip that provide management of all fault tolerant features, are described. Detailed supporting analyses and rationale which justifies specific design and architectural decisions are provided. The six chip types were designed and fabricated. Testing and evaluation of a brass/board was initiated.
Time exposure photography, sometimes coupled with strobe illumination, is an accepted method for motion analysis that bypasses frame by frame analysis and resynthesis of data. Garden variety video cameras can now exploit this technique using a unique frame buffer that is a non-integrating memory that compares incoming data with that already stored. The device continuously outputs an analog video signal of the stored contents which can then be redigitized and analyzed using conventional equipment. Historically, photographic time exposures have been used to record the displacement envelope of harmonically oscillating structures to show mode shape. Mode shape analysis is crucial, for example, in aeroelastic testing of wind tunnel models. Aerodynamic, inertial, and elastic forces can couple together leading to catastrophic failure of a poorly designed aircraft. This paper will explore the usefulness of the peak store device as a videometric tool and in particular discuss methods for analyzing a targeted vibrating plate using the 'peak store' in conjunction with calibration methods familiar to the close-range videometry community. Results for the first three normal modes will be presented.
Features of flash memories: Flash memories are non-volatile; that is they do not require power to retain the information in its memory. They can be erased and written to while the device is still in the circuit.
Not until recently, Xilinx has developed a new field programmable gate array (FPGA) device family, Virtex-I1 Pro. In this single device, not only dies it have density logic cells (3K to125K), gigabit connectivity, on chip memory, digital clock management, but also it can have up to four IBM PowerPC 405 Processor hard cores, running up to 400MHz and 633 Mbps. To utilize this cutting edge device in space applications, a few Single Event Upset (SEU) mitigation techniques need to be implemented to a design for the device. At Jet Propulsion Laboratory (JPL), we have successfully demonstrated the feasibility of running multiple processors running in a lock step fashion to accomplish SEU mitigation and fault tolerance.
Disclosed is a method to passively measure and calculate the strength of turbulence via the index of refraction structure constant Cn2 from video imagery gathered by an imaging device, such as a video camera. Processing may occur with any type computing device utilizing a processor executing machine executable code stored on memory. This method significantly simplifies instrumentation requirements, reduces cost, and provides rapid data output. This method combines an angle of arrival methodology, which provides scale factors, with a new spatial/temporal frequency domain method. As part of the development process, video imagery from high speed cameras was collected and analyzed. The data was decimated to video rates such that statistics could be computed and used to confirm that this passive method accurately characterizes the atmospheric turbulence. Cn2 accuracy from this method compared well with scintillometer data through two full orders of magnitude and more capability is expected beyond this verification.
Antiferromagnetically (AFM) coupled skyrmions offer potential advantages for spintronic devices, including reduced dipolar fields that may enable smaller skyrmion sizes and a reduction of the skyrmion Hall effect. However, the topological stability of AFM-coupled skyrmions subjected to dramatic spin deformation through low-temperature cycling has not been investigated. We report the discovery of a topological spin memory effect for AFM-coupled skyrmion pairs in [Co/Gd/Pt](10) multilayered films. Photoemission electron microscopy imaging shows that bubble skyrmions in the multilayer that are stable at room temperature evolve into complex in-plane spin textures as the temperature is lowered and reform completely when the sample is warmed back up. Simulations demonstrate that Dzyaloshinskii-Moriya interactions play a key role in this spin memory effect, and furthermore reveal that the topological charge is preserved throughout the dramatic spin texture rearrangement and recovery. These results highlight a key aspect of topological protection-the preservation of the topological properties under continuous deformation-and also provide a promising avenue for information encryption and recovery.
Computation in biological neural circuits arises from the interplay of nonlinear temporal responses and spatially distributed dynamic network interactions. Replicating this richness in hardware has remained challenging, as most neuromorphic devices emulate only isolated neuron- or synapse-like functions. Here we introduce an integrated neuromorphic computing platform in which both nonlinear spatiotemporal processing and programmable memory are realized within a single perovskite nickelate material system. By engineering symmetric and asymmetric hydrogenated NdNiO 3 junction devices on the same wafer, we combine ultrafast, proton-mediated transient dynamics with stable multilevel resistance states. Networks of symmetric NdNiO 3 junctions exhibit emergent spatial interactions mediated by proton redistribution, while each node simultaneously provides short-term temporal memory, enabling nanosecond-scale operation with an energy cost of ~0.2 nJ per input. When interfaced with asymmetric output units serving as reconfigurable long-term weights, these networks allow both feature transformation and linear classification in the same material system. Leveraging these emergent interactions, the platform enables real-time pattern recognition and achieves high accuracy in spoken digit classification and early seizure detection, outperforming temporal-only or uncoupled architectures. These results position protonic nickelates as a compact, energy-efficient, CMOS-compatible platform that integrates processing and memory for scalable intelligent hardware.
A novel, unobtrusive and wearable, multiparameter ambulatory physiologic monitoring system for space and terrestrial applications, termed LifeGuard, is presented. The core element is a wearable monitor, the crew physiologic observation device (CPOD), that provides the capability to continuously record two standard electrocardiogram leads, respiration rate via impedance plethysmography, heart rate, hemoglobin oxygen saturation, ambient or body temperature, three axes of acceleration, and blood pressure. These parameters can be digitally recorded with high fidelity over a 9-h period with precise time stamps and user-defined event markers. Data can be continuously streamed to a base station using a built-in Bluetooth RF link or stored in 32 MB of on-board flash memory and downloaded to a personal computer using a serial port. The device is powered by two AAA batteries. The design, laboratory, and field testing of the wearable monitors are described.
The Midwestern astronomical data reduction and analysis facility (MADRAF) PDS microdensitometer which was the first astronomical PDS which was provided with a Motorola 6800 microprocessor control/interface and will be interfaced to a 32-bit instruction computer operating in a multiuser environment is outlined. Command and response handshaking are handled on an RS 232 serial line while data transfer occurs on a dedicated Direct Memory Access line. This set of conditions necessitated the creation of a specialized device for the system. The general outline of this software is discussed. The availability of an extraordinarily powerful computer opened the possibility of a user operating program of great versatility with diverse data destinations and formats, automatic documentation, and an extensive set of utilities which facilitate operations.
Recently, scientists and engineers have investigated the advantages of smart materials and structures by including actuators in material systems for controlling and altering the response of structural environments. Applications of these materials systems include vibration suppression/isolation, precision positioning, damage detection and tunable devices. Some of the embedded materials being investigated for accomplishing these tasks include piezoelectric ceramics, shape memory alloys, and fiber optics. These materials have some benefits and some shortcomings; each is being studied for use in active material design in the SPICES (Synthesis and Processing of Intelligent Cost Effective Structures) Consortium. The focus of this paper concerns the manufacturing aspects of smart structures by incorporating piezoelectric ceramics, shape memory alloys and fiber optics in a reinforced thermoset matrix via resin transfer molding (RTM).
Specifications were developed for a memory system to be used as the storage media for camera detectors on the large space telescope (LST) satellite. Detectors with limited internal storage time such as intensities charge coupled devices and silicon intensified targets are implied. The general characteristics are reported of different approaches to the memory system with comparisons made within the guidelines set forth for the LST application. Priority ordering of comparisons is on the basis of cost, reliability, power, and physical characteristics. Specific rationales are provided for the rejection of unsuitable memory technologies. A recommended technology was selected and used to establish specifications for a breadboard memory. Procurement scheduling is provided for delivery of system breadboards in 1976, prototypes in 1978, and space qualified units in 1980.
Topological spin/polarization structures in ferroic materials continue to draw great attention as a result of their fascinating physical behaviors and promising applications in the field of high-density nonvolatile memories as well as future energy-efficient nanoelectronic and spintronic devices. Such developments have been made, in part, based on recent advances in theoretical calculations, the synthesis of high-quality thin films, and the characterization of their emergent phenomena and exotic phases. Herein, progress over the last decade in the study of topological structures in ferroic thin films and heterostructures is explored, including the observation of topological structures and control of their structures and emergent physical phenomena through epitaxial strain, layer thickness, electric, magnetic fields, etc. First, the evolution of topological spin structures (e.g., magnetic skyrmions) and associated functionalities (e.g., topological Hall effect) in magnetic thin films and heterostructures is discussed. Then, the exotic polar topologies (e.g., domain walls, closure domains, polar vortices, bubble domains, and polar skyrmions) and their emergent physical properties in ferroelectric oxide films and heterostructures are explored. Lastly, a brief overview and prospectus of how the field may evolve in the coming years is provided.
The charge density wave material 1T-TaS 2 exhibits a pulse-induced insulator-to-metal transition, which shows promise for next-generation electronics such as memristive memory and neuromorphic hardware. However, the rational design of TaS 2 devices is hindered by a poor understanding of the switching mechanism, the pulse-induced phase, and the influence of material defects. Here, we operate a 2-terminal TaS 2 device within a scanning transmission electron microscope at cryogenic temperature, and directly visualize the changing charge density wave structure with nanoscale spatial resolution and down to 300 μs temporal resolution. We show that the pulse-induced transition is driven by Joule heating, and that the pulse-induced state corresponds to the nearly commensurate and incommensurate charge density wave phases, depending on the applied voltage amplitude. With our in operando cryogenic electron microscopy experiments, we directly correlate the charge density wave structure with the device resistance, and show that dislocations significantly impact device performance. This work resolves fundamental questions of resistive switching in TaS 2 devices, critical for engineering reliable and scalable TaS 2 electronics.
The major architectural features of the ILLIAC IV large scale, array processor are summarized along with their applicability to image processing. Several image processing algorithms are considered, including multispectral classification, texture feature extraction, two-dimensional Fourier transform, and synthetic aperture radar processing. The basic parallelism of the ILLIAC IV (64 processing elements acting in lock-step) is usually fully utilized by the image processing applications. The major architectural aspect of the system with respect to image processing is the relatively small local scratch-pad memory and the long latency time to access the main storage device. The major precision used for the image processing applications is the 32-bit floating point, given a choice of 8-bit integers and 64-bit floating point.
Up to 16 input signals feed each of up to 128 input circuit cards. Single input circuit card contains optical isolators with input-diode lamping, RC filters, Schmitt-trigger input buffers, and 16-to-1 multiplexer. Input circuit cards feed logic, memory, and input/output circuits, which are standard, off-the-shelf devices. Instrument records sequence and time of events and could be useful in monitoring operation of manufacturing machinery and furnishing information useful in diagnosis of machinery malfunctions.