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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 703 records · Page 39
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Hardware-in-the-Loop Evaluation for Potential High Limit Estimation-Based PV Plant Active Control

This paper validates the efficacy of an artificial intelligence (AI)-based photovoltaic (PV) plant control and optimization approach in enabling PV plants as accountable grid reliability service providers. The validation is performed in a realistic laboratory controller-hardware-in-the-loop environment, leveraging accurate PV plant modeling and standard industrial communication protocols. Through simulations that account for diverse weather conditions and active control scenarios, the results highlight the superior performance of the AI-based solution in comparison to a state-of-the-art reference-control grouping-based approach. Such a finding contributes to mitigating the risk of overcurtailment and uninstructed deviations of active PV plant controls, and offers practical guidance for its field deployment. Furthermore, it establishes a standardized testing framework for comparing various PV active control strategies.

hardware-in-the-loop↗
DOE OSTI2023

Hardware-in-the-Loop Evaluation of Grid-Edge DER Chip Integration Into Next-Generation Smart Meters

To facilitate the implementation of distributed energy resource management systems (DERMS), we propose to insert a grid-edge distributed energy resource (DER) chip hosting a DERMS algorithm into the next generation of smart meters. This will create a pathway for the wide adoption of DERMS technology because many utilities plan to invest in advanced metering infrastructure in the near future. This will also bridge the gap between an electrical power utility and DERs behind the meter. The DER chip is designed to follow power direction signals from the DERMS coordinator while balancing its local objectives. We tested the chip using a controller- and power-hardware-in-the-loop evaluation under three scenarios that a DERMS could face in the real world. The DER chip was capable of and effective at directing four heterogeneous DERs to respond to a DERMS coordinator for grid services (e.g., voltage regulation and a virtual power plant).

distributed energy resource management system↗
DOE OSTI2024

Implementing a Hardware Testbed Using 3-Level ANPC Software Defined Inverters for Fault Analysis of a Transmission Network

In this paper, we propose the implementation of a hardware testbed using 3-level active neutral point clamped (ANPC) software-defined inverters for fault analysis. A test case transmission network equipped with two grid forming (GFM) inverters and four resistive loads is considered in this research. Firstly, grid forming control laws including PI feedback control and droop control are implemented to operate the inverters in parallel. Then, we implement a fault ride-through (FRT) logic and perform a simulation of the test system by applying a three-phase fault. Simulation results show the effectiveness of the fault recovery algorithm upon clearance of the fault. Finally, a 3-level ANPC software-defined inverter is programmed with required control laws and characterized through various lab experiments.

3-level ANPC inverter↗
DOE OSTI2020

waveSZ: A Hardware-Algorithm Co-Design of Efficient Lossy Compression for Scientific Data

Error-bounded lossy compression is critical to the success of extreme-scale scientific research because of ever-increasing volumes of data produced by today's high-performance computing (HPC) applications. Not only can error-controlled lossy compressors significantly reduce the I/O and storage burden but they can retain high data fidelity for post analysis. Existing state-of-the-art lossy compressors, however, generally suffer from relatively low compression and decompression throughput (up to hundreds of megabytes per second on a single CPU core), which considerably restrict the adoption of lossy compression by many HPC applications especially those with a fairly high data production rate. In this paper, we propose a highly efficient lossy compression approach based on field programmable gate arrays (FPGAs) under the state-of-the-art lossy compression model SZ. Our contributions are fourfold. (1) We adopt a wavefront memory layout to alleviate the data dependency during the prediction for higher-dimensional predictors, such as the Lorenzo predictor. (2) We propose a co-design framework named WAVESZ based on the wavefront memory layout and the characteristics of SZ algorithm and carefully implement it by using high-level synthesis. (3) We propose a hardware-algorithm co-optimization method to improve the performance. (4) We evaluate our proposed WAVESZ on three real-world HPC simulation datasets from the Scientific Data Reduction Benchmarks and compare it with other state-of-the-art methods on both CPUs and FPGAs. Experiments show that our WAVESZ can improve SZ's compression throughput by 6.9x similar to 8.7x over the production version running on a state-of-the-art CPU and improve the compression ratio and throughput by 2.1x and 5.8x on average, respectively, respectively, compared with the state-of-the-art FPGA design.

Compression Ratio↗
DOE OSTI2015

Power Hardware-in-the-Loop-Based Anti-Islanding Evaluation and Demonstration

The National Renewable Energy Laboratory (NREL) teamed with Southern California Edison (SCE), Clean Power Research (CPR), Quanta Technology (QT), and Electrical Distribution Design (EDD) to conduct a U.S. Department of Energy (DOE) and California Public Utility Commission (CPUC) California Solar Initiative (CSI)-funded research project investigating the impacts of integrating high-penetration levels of photovoltaics (PV) onto the California distribution grid. One topic researched in the context of high-penetration PV integration onto the distribution system is the ability of PV inverters to (1) detect islanding conditions (i.e., when the distribution system to which the PV inverter is connected becomes disconnected from the utility power connection) and (2) disconnect from the islanded system within the time specified in the performance specifications outlined in IEEE Standard 1547. This condition may cause damage to other connected equipment due to insufficient power quality (e.g., over-and under-voltages) and may also be a safety hazard to personnel that may be working on feeder sections to restore service. NREL teamed with the Florida State University (FSU) Center for Advanced Power Systems (CAPS) to investigate a new way of testing PV inverters for IEEE Standard 1547 unintentional islanding performance specifications using power hardware-in-loop (PHIL) laboratory testing techniques.

14 SOLAR ENERGY↗
DOE OSTI2016

Hardware-in-the-Loop Testing of Utility-Scale Wind Turbine Generators

Historically, wind turbine prototypes were tested in the field, which was--and continues to be--a slow and expensive process. As a result, wind turbine dynamometer facilities were developed to provide a more cost-effective alternative to field testing. New turbine designs were tested and the design models were validated using dynamometers to drive the turbines in a controlled environment. Over the years, both wind turbine dynamometer testing and computer technology have matured and improved, and the two are now being joined to provide hardware-in-the-loop (HIL) testing. This type of testing uses a computer to simulate the items that are missing from a dynamometer test, such as grid stiffness, voltage, frequency, rotor, and hub. Furthermore, wind input and changing electric grid conditions can now be simulated in real time. This recent advance has greatly increased the utility of dynamometer testing for the development of wind turbine systems.

17 WIND ENERGY↗
DOE OSTI2023

Hardware Implementation and Market Impacts of Grid-Supportive Functions in End-Use Loads

Grid-supportive loads (GSLs) are power electronics-based end-use loads that can provide frequency response and other grid services by autonomously adjusting their output power using local grid measurements. This report provides details on GSL hardware design options and their associated costs and benefits for multiple devices, including EV chargers, refrigerators, and heat pumps. We consider mechanisms to incentivize adoption of GSLs at scale and estimate the quantity of frequency response that can be procured with GSLs.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2024

Hardware-in-the-loop Laboratory Performance Verification of Flexible Building Equipment in a Typical Commercial Building

This project aims to develop high-resolution equipment performance and occupant data that quantifies demand flexibility in typical commercial buildings. The dataset documented in this report includes comprehensive time-series measurements from hardware-in-the-loop (HIL) experiments conducted across multiple testbeds designed to simulate realistic operational environments for HVAC systems. Specifically, it captures minute-by-minute high-resolution data on the performance of various typical HVAC systems, including a variable-air-volume (VAV) air handling unit (AHU) system with chillers and an ice tank in the Intelligent Building Agents Laboratory (IBAL) at the National Institute of Standards and Technology (NIST), a two-stage air-source heat pump (ASHP) at the NIST, and a water-source heat pump (WSHP) at Texas A&M University (TAMU). The data were generated under a range of controlled conditions reflecting different grid scenarios and climatic influences, as well as various control strategies, building types, occupancy patterns, and occupant behaviors. This dataset provides DE-EE0009153 Final Report 5 detailed insights into the demand flexibility of these systems, including their response to grid signals, occupant behaviors, energy consumption patterns, and operational efficiency under different conditions.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2025

Evaluating Thermostats' Deadbands Using HVAC Hardware-In-the-Loop Experiment for Advanced Control Strategies

Smart thermostats have gained significant popularity due to their potential for optimizing energy consumption and enhanced user control while ensuring occupants' comfort. The deadband, also referred to as temperature differential, is defined as the temperature difference between the desired setpoint and upper threshold or lower threshold for the HVAC equipment to turn on. It is a key factor influencing energy efficiency and user satisfaction. This paper presents a comparative analysis of the deadbands of five different smart thermostats, tested with a heat pump, aiming to identify variations in their deadband settings and implications for energy management. The experimental study was conducted using a HVAC hardware-in-theloop (HIL) system that integrates smart thermostats with physical HVAC equipment in a simulated house environment. The study explores the trade-offs between energy efficiency and occupant comfort and highlights how different thermostats participating in demand response event cycle differently based on their deadband settings. The findings offer valuable insights into how selecting the right thermostat or configuring smart thermostat with appropriate deadband settings can be leveraged to enhance demand response capabilities, shift loads effectively and improve operational flexibility in HVAC systems.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2023

Hardware-in-the-Loop Efficiency Analysis of Tidal Power Systems

Marine renewable energy presents an opportunity for sustainable power in areas located near and in the marine environment. In particular, tidal energy offers a consistent and reliable resource. However, tidal energy harvesting systems seeking to take advantage of this resource face challenges associated with power electronics. Power conversion electronics struggle with low efficiencies, lack of off-the-shelf options for small-scale energy harvesting systems, and limited opportunities for testing with deployed turbines. This work demonstrates a hardware-in-the-loop experimental design and methodology for characterizing efficiency of tidal turbine power electronics and control methods. The suggested method removes barriers to testing these power electronics by eliminating the need for a physical tidal turbine and generator to produce accurate harvested tidal power profiles.

tidal turbine, hardware-in-the-loop, energy conver↗
DOE OSTI2023

Distributed Energy Management for Networked Microgrids with Hardware-in-the-Loop Validation

For the cooperative operation of networked microgrids, a distributed energy management considering network operational objectives and constraints is proposed in this work. Considering various ownership and privacy requirements of microgrids, utility directly interfaced distributed energy resources (DERs) and demand response, a distributed optimization is proposed for obtaining optimal network operational objectives with constraints satisfied through iteratively updated price signals. The alternating direction method of multipliers (ADMM) algorithm is utilized to solve the formulated distributed optimization. The proposed distributed energy management provides microgrids, utility-directly interfaced DERs and responsive demands the opportunity of contributing to better network operational objectives while preserving their privacy and autonomy. Results of numerical simulation using a networked microgrids system consisting of several microgrids, utility directly interfaced DERs and responsive demands validate the soundness and accuracy of the proposed distributed energy management. The proposed method is further tested on a practical two-microgrid system located in Adjuntas, Puerto Rico, and the applicability of the proposed strategy is validated through hardware-in-the-loop (HIL) testing.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2025

hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware

We present hls4ml, a free and open-source platform that translates machine learning (ML) models from modern deep learning frameworks into high-level synthesis (HLS) code that can be integrated into full designs for field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). With its flexible and modular design, hls4ml supports a large number of deep learning frameworks and can target HLS compilers from several vendors, including Vitis HLS, Intel oneAPI and Catapult HLS. Together with a wider eco-system for software-hardware co-design, hls4ml has enabled the acceleration of ML inference in a wide range of commercial and scientific applications where low latency, resource usage, and power consumption are critical. In this paper, we describe the structure and functionality of the hls4ml platform. The overarching design considerations for the generated HLS code are discussed, together with selected performance results.

FOS: Computer and information sciences↗