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At least 703 records · Page 39

Logic Gates Made of N-Channel JFETs and Epitaxial Resistors

Prototype logic gates made of n-channel junction field-effect transistors (JFETs) and epitaxial resistors have been demonstrated, with a view toward eventual implementation of digital logic devices and systems in silicon carbide (SiC) integrated circuits (ICs). This development is intended to exploit the inherent ability of SiC electronic devices to function at temperatures from 300 to somewhat above 500 C and withstand large doses of ionizing radiation. SiC-based digital logic devices and systems could enable operation of sensors and robots in nuclear reactors, in jet engines, near hydrothermal vents, and in other environments that are so hot or radioactive as to cause conventional silicon electronic devices to fail. At present, current needs for digital processing at high temperatures exceed SiC integrated circuit production capabilities, which do not allow for highly integrated circuits. Only single to small number component production of depletion mode n-channel JFETs and epitaxial resistors on a single substrate is possible. As a consequence, the fine matching of components is impossible, resulting in rather large direct-current parameter distributions within a group of transistors typically spanning multiples of 5 to 10. Add to this the lack of p-channel devices to complement the n-channel FETs, the lack of precise dropping diodes, and the lack of enhancement mode devices at these elevated temperatures and the use of conventional direct coupled and buffered direct coupled logic gate design techniques is impossible. The presented logic gate design is tolerant of device parameter distributions and is not hampered by the lack of complementary devices or dropping diodes. In addition to n-channel JFETs, these gates include level-shifting and load resistors (see figure). Instead of relying on precise matching of parameters among individual JFETS, these designs rely on choosing the values of these resistors and of supply potentials so as to make the circuits perform the desired functions throughout the ranges over which the parameters of the JFETs are distributed. The supply rails V(sub dd) and V(sub ss) and the resistors R are chosen as functions of the distribution of direct-current operating parameters of the group of transistors used.

Krasowski, Michael J.↗

NASA Tech Briefs, January 2009

Tech Briefs are short announcements of innovations originating from research and development activities of the National Aeronautics and Space Administration. They emphasize information considered likely to be transferable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. Topics covered include: The Radio Frequency Health Node Wireless Sensor System; Effects of Temperature on Polymer/Carbon Chemical Sensors; Small CO2 Sensors Operate at Lower Temperature; Tele-Supervised Adaptive Ocean Sensor Fleet; Synthesis of Submillimeter Radiation for Spectroscopy; 100-GHz Phase Switch/Mixer Containing a Slot-Line Transition; Generating Ka-Band Signals Using an X-Band Vector Modulator; SiC Optically Modulated Field-Effect Transistor; Submillimeter-Wave Amplifier Module with Integrated Waveguide Transitions; Metrology System for a Large, Somewhat Flexible Telescope; Economical Implementation of a Filter Engine in an FPGA; Improved Joining of Metal Components to Composite Structures; Machined Titanium Heat-Pipe Wick Structure; Gadolinia-Doped Ceria Cathodes for Electrolysis of CO2; Utilizing Ocean Thermal Energy in a Submarine Robot; Fuel-Cell Power Systems Incorporating Mg-Based H2 Generators; Alternative OTEC Scheme for a Submarine Robot; Sensitive, Rapid Detection of Bacterial Spores; Adenosine Monophosphate-Based Detection of Bacterial Spores; Silicon Microleaks for Inlets of Mass Spectrometers; CGH Figure Testing of Aspherical Mirrors in Cold Vacuums; Series-Coupled Pairs of Silica Microresonators; Precise Stabilization of the Optical Frequency of WGMRs; Formation Flying of Components of a Large Space Telescope; Laser Metrology Heterodyne Phase-Locked Loop; Spatial Modulation Improves Performance in CTIS; High-Performance Algorithm for Solving the Diagnosis Problem; Truncation Depth Rule-of-Thumb for Convolutional Codes; Efficient Method for Optimizing Placement of Sensors.

Source record↗

SOI CMOS Imager with Suppression of Cross-Talk

A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

Pain, Bedabrata↗

Improved Signal Chains for Readout of CMOS Imagers

An improved generic design has been devised for implementing signal chains involved in readout from complementary metal oxide/semiconductor (CMOS) image sensors and for other readout integrated circuits (ICs) that perform equivalent functions. The design applies to any such IC in which output signal charges from the pixels in a given row are transferred simultaneously into sampling capacitors at the bottoms of the columns, then voltages representing individual pixel charges are read out in sequence by sequentially turning on column-selecting field-effect transistors (FETs) in synchronism with source-follower- or operational-amplifier-based amplifier circuits. The improved design affords the best features of prior source-follower-and operational- amplifier-based designs while overcoming the major limitations of those designs. The limitations can be summarized as follows: a) For a source-follower-based signal chain, the ohmic voltage drop associated with DC bias current flowing through the column-selection FET causes unacceptable voltage offset, nonlinearity, and reduced small-signal gain. b) For an operational-amplifier-based signal chain, the required bias current and the output noise increase superlinearly with size of the pixel array because of a corresponding increase in the effective capacitance of the row bus used to couple the sampled column charges to the operational amplifier. The effect of the bus capacitance is to simultaneously slow down the readout circuit and increase noise through the Miller effect.

Pain, Bedabrata↗

Particle-Charge Spectrometer

An instrument for rapidly measuring the electric charges and sizes (from approximately 1 to approximately 100 micrometers) of airborne particles is undergoing development. Conceived for monitoring atmospheric dust particles on Mars, instruments like this one could also be used on Earth to monitor natural and artificial aerosols in diverse indoor and outdoor settings for example, volcanic regions, clean rooms, powder-processing machinery, and spray-coating facilities. The instrument incorporates a commercially available, low-noise, ultrasensitive charge-sensing preamplifier circuit. The input terminal of this circuit--the gate of a field-effect transistor--is connected to a Faraday-cage cylindrical electrode. The charged particles of interest are suspended in air or other suitable gas that is made to flow along the axis of the cylindrical electrode without touching the electrode. The flow can be channeled and generated by any of several alternative means; in the prototype of this instrument, the gas is drawn along a glass capillary tube (see upper part of figure) coaxial with the electrode. The size of a particle affects its rate of acceleration in the flow and thus affects the timing and shape of the corresponding signal peak generated by the charge-sensing amplifier. The charge affects the magnitude (and thus also the shape) of the signal peak. Thus, the signal peak (see figure) conveys information on both the size and electric charge of a sensed particle. In experiments thus far, the instrument has been found to be capable of measuring individual aerosol particle charges of magnitude greater than 350 e (where e is the fundamental unit of electric charge) with a precision of +/- 150 e. The instrument can sample particles at a rate as high as several thousand per second.

Fuerstenau, Stephen↗

Electronic Switch Arrays for Managing Microbattery Arrays

Integrated circuits have been invented for managing the charging and discharging of such advanced miniature energy-storage devices as planar arrays of microscopic energy-storage elements [typically, microscopic electrochemical cells (microbatteries) or microcapacitors]. The architecture of these circuits enables implementation of the following energy-management options: dynamic configuration of the elements of an array into a series or parallel combination of banks (subarrarys), each array comprising a series of parallel combination of elements; direct addressing of individual banks for charging/or discharging; and, disconnection of defective elements and corresponding reconfiguration of the rest of the array to utilize the remaining functional elements to obtain the desited voltage and current performance. An integrated circuit according to the invention consists partly of a planar array of field-effect transistors that function as switches for routing electric power among the energy-storage elements, the power source, and the load. To connect the energy-storage elements to the power source for charging, a specific subset of switches is closed; to connect the energy-storage elements to the load for discharging, a different specific set of switches is closed. Also included in the integrated circuit is circuitry for monitoring and controlling charging and discharging. The control and monitoring circuitry, the switching transistors, and interconnecting metal lines are laid out on the integrated-circuit chip in a pattern that registers with the array of energy-storage elements. There is a design option to either (1) fabricate the energy-storage elements in the corresponding locations on, and as an integral part of, this integrated circuit; or (2) following a flip-chip approach, fabricate the array of energy-storage elements on a separate integrated-circuit chip and then align and bond the two chips together.

Mojarradi, Mohammad↗

Nano-Multiplication-Region Avalanche Photodiodes and Arrays

Nano-multiplication-region avalanche photodiodes (NAPDs), and imaging arrays of NAPDs integrated with complementary metal oxide/semiconductor (CMOS) active-pixel-sensor integrated circuitry, are being developed for applications in which there are requirements for high-sensitivity (including photoncounting) detection and imaging at wavelengths from about 250 to 950 nm. With respect to sensitivity and to such other characteristics as speed, geometric array format, radiation hardness, power demand of associated circuitry, size, weight, and robustness, NAPDs and arrays thereof are expected to be superior to prior photodetectors and arrays including CMOS active-pixel sensors (APSs), charge-coupled devices (CCDs), traditional APDs, and microchannelplate/ CCD combinations. Figure 1 depicts a conceptual NAPD array, integrated with APS circuitry, fabricated on a thick silicon-on-insulator wafer (SOI). Figure 2 presents selected aspects of the structure of a typical single pixel, which would include a metal oxide/semiconductor field-effect transistor (MOSFET) integrated with the NAPD. The NAPDs would reside in silicon islands formed on the buried oxide (BOX) layer of the SOI wafer. The silicon islands would be surrounded by oxide-filled insulation trenches, which, together with the BOX layer, would constitute an oxide embedding structure. There would be two kinds of silicon islands: NAPD islands for the NAPDs and MOSFET islands for in-pixel and global CMOS circuits. Typically, the silicon islands would be made between 5 and 10 m thick, but, if necessary, the thickness could be chosen outside this range. The side walls of the silicon islands would be heavily doped with electron-acceptor impurities (p+-doped) to form anodes for the photodiodes and guard layers for the MOSFETs. A nanoscale reach-through structure at the front (top in the figures) central position of each NAPD island would contain the APD multiplication region. Typically, the reach-through structure would be about 0.1 microns in diameter and between 0.3 and 0.4 nm high. The top layer in the reach-through structure would be heavily doped with electron-donor impurities (n+-doped) to make it act as a cathode. A layer beneath the cathode, between 0.1 and 0.2 nm thick, would be p-doped to a concentration .10(exp 17)cu cm. A thin n+-doped polysilicon pad would be formed on the top of the cathode to protect the cathode against erosion during a metal-silicon alloying step that would be part of the process of fabricating the array.

Zheng, Xinyu↗

Two-Dimensional Quantum Model of a Nanotransistor

A mathematical model, and software to implement the model, have been devised to enable numerical simulation of the transport of electric charge in, and the resulting electrical performance characteristics of, a nanotransistor [in particular, a metal oxide/semiconductor field-effect transistor (MOSFET) having a channel length of the order of tens of nanometers] in which the overall device geometry, including the doping profiles and the injection of charge from the source, gate, and drain contacts, are approximated as being two-dimensional. The model and software constitute a computational framework for quantitatively exploring such device-physics issues as those of source-drain and gate leakage currents, drain-induced barrier lowering, and threshold voltage shift due to quantization. The model and software can also be used as means of studying the accuracy of quantum corrections to other semiclassical models.

Govindan, T. R.↗

High Power Amplifier and Power Supply

A document discusses the creation of a high-voltage power supply (HVPS) that is able to contain voltages up to -20 kV, keep electrical field strengths to below 200 V/mil (approximately equal to 7.87 kV/mm), and can provide a 200-nanosecond rise/fall time focus modulator swinging between cathode potential of 16.3 kV and -19.3 kV. This HVPS can protect the 95-GHz, pulsed extended interaction klystron (EIK) from arcs/discharges from all sources, including those from within the EIK fs vacuum envelope. This innovation has a multi-winding pulse transformer design, which uses new winding techniques to provide the same delays and rise/fall times (less than 10 nanoseconds) at different potential levels ranging from -20 kV to -16 kV. Another feature involves a high-voltage printed-wiring board that was corona-free at -20 kV DC with a 3- kV AC swing. The corona-free multilayer high-voltage board is used to simulate fields of less than 200 V/mil (approximately equal to 7.87 kV/mm) at 20 kV DC. Drive techniques for the modulator FETs (field-effect transistors) (four to 10 in a series) were created to change states (3,000-V swing) without abrupt steps, while still maintaining required delays and transition times. The packing scheme includes a potting mold to house a ten-stage modulator in the space that, in the past, only housed a four-stage modulator. Problems keeping heat down were solved using aluminum oxide substrate in the high-voltage section to limit temperature rise to less than 10 while withstanding -20 kV DC voltage and remaining corona-free.

Duong, Johnny↗

Zinc Alloys for the Fabrication of Semiconductor Devices

ZnBeO and ZnCdSeO alloys have been disclosed as materials for the improvement in performance, function, and capability of semiconductor devices. The alloys can be used alone or in combination to form active photonic layers that can emit over a range of wavelength values. Materials with both larger and smaller band gaps would allow for the fabrication of semiconductor heterostructures that have increased function in the ultraviolet (UV) region of the spectrum. ZnO is a wide band-gap material possessing good radiation-resistance properties. It is desirable to modify the energy band gap of ZnO to smaller values than that for ZnO and to larger values than that for ZnO for use in semiconductor devices. A material with band gap energy larger than that of ZnO would allow for the emission at shorter wavelengths for LED (light emitting diode) and LD (laser diode) devices, while a material with band gap energy smaller than that of ZnO would allow for emission at longer wavelengths for LED and LD devices. The amount of Be in the ZnBeO alloy system can be varied to increase the energy bandgap of ZnO to values larger than that of ZnO. The amount of Cd and Se in the ZnCdSeO alloy system can be varied to decrease the energy band gap of ZnO to values smaller than that of ZnO. Each alloy formed can be undoped or can be p-type doped using selected dopant elements, or can be n-type doped using selected dopant elements. The layers and structures formed with both the ZnBeO and ZnCdSeO semiconductor alloys - including undoped, p-type-doped, and n-type-doped types - can be used for fabricating photonic and electronic semiconductor devices for use in photonic and electronic applications. These devices can be used in LEDs, LDs, FETs (field effect transistors), PN junctions, PIN junctions, Schottky barrier diodes, UV detectors and transmitters, and transistors and transparent transistors. They also can be used in applications for lightemitting display, backlighting for displays, UV and visible transmitters and detectors, high-frequency radar, biomedical imaging, chemical compound identification, molecular identification and structure, gas sensors, imaging systems, and for the fundamental studies of atoms, molecules, gases, vapors, and solids.

Ryu, Yungryel↗

Silicon Nanowire Growth at Chosen Positions and Orientations

It is now possible to grow silicon nanowires at chosen positions and orientations by a method that involves a combination of standard microfabrication processes. Because their positions and orientations can be chosen with unprecedented precision, the nanowires can be utilized as integral parts of individually electronically addressable devices in dense arrays. Nanowires made from silicon and perhaps other semiconductors hold substantial promise for integration into highly miniaturized sensors, field-effect transistors, optoelectronic devices, and other electronic devices. Like bulk semiconductors, inorganic semiconducting nanowires are characterized by electronic energy bandgaps that render them suitable as means of modulating or controlling electronic signals through electrostatic gating, in response to incident light, or in response to molecules of interest close to their surfaces. There is now potential for fabricating arrays of uniform, individually electronically addressable nanowires tailored to specific applications. The method involves formation of metal catalytic particles at the desired positions on a substrate, followed by heating the substrate in the presence of silane gas. The figure illustrates an example in which a substrate includes a silicon dioxide surface layer that has been etched into an array of pillars and the catalytic (in this case, gold) particles have been placed on the right-facing sides of the pillars. The catalytic thermal decomposition of the silane to silicon and hydrogen causes silicon columns (the desired nanowires) to grow outward from the originally catalyzed spots on the substrate, carrying the catalytic particles at their tips. Thus, the position and orientation of each silicon nanowire is determined by the position of its originally catalyzed spot on the substrate surface, and the orientation of the nanowire is perpendicular to the substrate surface at the originally catalyzed spot.

Getty, Stephanie A.↗

Efficient Multiplexer FPGA Block Structures Based on G4FETs

Generic structures have been conceived for multiplexer blocks to be implemented in field-programmable gate arrays (FPGAs) based on four-gate field-effect transistors (G(sup 4)FETs). This concept is a contribution to the continuing development of digital logic circuits based on G4FETs and serves as a further demonstration that logic circuits based on G(sup 4)FETs could be more efficient (in the sense that they could contain fewer transistors), relative to functionally equivalent logic circuits based on conventional transistors. Results in this line of development at earlier stages were summarized in two previous NASA Tech Briefs articles: "G(sup 4)FETs as Universal and Programmable Logic Gates" (NPO-41698), Vol. 31, No. 7 (July 2007), page 44, and "Efficient G4FET-Based Logic Circuits" (NPO-44407), Vol. 32, No. 1 ( January 2008), page 38 . As described in the first-mentioned previous article, a G4FET can be made to function as a three-input NOT-majority gate, which has been shown to be a universal and programmable logic gate. The universality and programmability could be exploited to design logic circuits containing fewer components than are required for conventional transistor-based circuits performing the same logic functions. The second-mentioned previous article reported results of a comparative study of NOT-majority-gate (G(sup 4)FET)-based logic-circuit designs and equivalent NOR- and NAND-gate-based designs utilizing conventional transistors. [NOT gates (inverters) were also included, as needed, in both the G(sup 4)FET- and the NOR- and NAND-based designs.] In most of the cases studied, fewer logic gates (and, hence, fewer transistors), were required in the G(sup 4)FET-based designs. There are two popular categories of FPGA block structures or architectures: one based on multiplexers, the other based on lookup tables. In standard multiplexer- based architectures, the basic building block is a tree-like configuration of multiplexers, with possibly a few additional logic gates such as ANDs or ORs. Interconnections are realized by means of programmable switches that may connect the input terminals of a block to output terminals of other blocks, may bridge together some of the inputs, or may connect some of the input terminals to signal sources representing constant logical levels 0 or 1. The left part of the figure depicts a four-to-one G(sup 4)FET-based multiplexer tree; the right part of the figure depicts a functionally equivalent four-to-one multiplexer based on conventional transistors. The G(sup 4)FET version would contains 54 transistors; the conventional version contains 70 transistors.

Vatan, Farrokh↗

Circuit for Driving Piezoelectric Transducers

The figure schematically depicts an oscillator circuit for driving a piezoelectric transducer to excite vibrations in a mechanical structure. The circuit was designed and built to satisfy application-specific requirements to drive a selected one of 16 such transducers at a regulated amplitude and frequency chosen to optimize the amount of work performed by the transducer and to compensate for both (1) temporal variations of the resonance frequency and damping time of each transducer and (2) initially unknown differences among the resonance frequencies and damping times of different transducers. In other words, the circuit is designed to adjust itself to optimize the performance of whichever transducer is selected at any given time. The basic design concept may be adaptable to other applications that involve the use of piezoelectric transducers in ultrasonic cleaners and other apparatuses in which high-frequency mechanical drives are utilized. This circuit includes three resistor-capacitor networks that, together with the selected piezoelectric transducer, constitute a band-pass filter having a peak response at a frequency of about 2 kHz, which is approximately the resonance frequency of the piezoelectric transducers. Gain for generating oscillations is provided by a power hybrid operational amplifier (U1). A junction field-effect transistor (Q1) in combination with a resistor (R4) is used as a voltage-variable resistor to control the magnitude of the oscillation. The voltage-variable resistor is part of a feedback control loop: Part of the output of the oscillator is rectified and filtered for use as a slow negative feedback to the gate of Q1 to keep the output amplitude constant. The response of this control loop is much slower than 2 kHz and, therefore, does not introduce significant distortion of the oscillator output, which is a fairly clean sine wave. The positive AC feedback needed to sustain oscillations is derived from sampling the current through the piezoelectric transducer. This positive AC feedback, in combination with the slow feedback to the voltage-variable resistors, causes the overall loop gain to be just large enough to keep the oscillator running. The positive feedback loop includes two 16-channel multiplexers, which are not shown in the figure. One multiplexer is used to select the desired piezoelectric transducer. The other multiplexer, which is provided for use in the event that there are significant differences among the damping times of the 16 piezoelectric transducers, facilitates changing the value of one of the resistors in the positive-feedback loop to accommodate the damping time of the selected transducer.

Randall, David P.↗

Lightning Pin Injection Testing on MOSFETS

Lightning transients were pin-injected into metal-oxide-semiconductor field-effect transistors (MOSFETs) to induce fault modes. This report documents the test process and results, and provides a basis for subsequent lightning tests. MOSFETs may be present in DC-DC power supplies and electromechanical actuator circuits that may be used on board aircraft. Results show that unprotected MOSFET Gates are susceptible to failure, even when installed in systems in well-shielded and partial-shielded locations. MOSFET Drains and Sources are significantly less susceptible. Device impedance decreased (current increased) after every failure. Such a failure mode may lead to cascading failures, as the damaged MOSFET may allow excessive current to flow through other circuitry. Preliminary assessments on a MOSFET subjected to 20-stroke pin-injection testing demonstrate that Breakdown Voltage, Leakage Current and Threshold Voltage characteristics show damage, while the device continues to meet manufacturer performance specifications. The purpose of this research is to develop validated tools, technologies, and techniques for automated detection, diagnosis and prognosis that enable mitigation of adverse events during flight, such as from lightning transients; and to understand the interplay between lightning-induced surges and aging (i.e. humidity, vibration thermal stress, etc.) on component degradation.

Ely, Jay J.↗

Lattice-Matched Semiconductor Layers on Single Crystalline Sapphire Substrate

SiGe is an important semiconductor alloy for high-speed field effect transistors (FETs), high-temperature thermoelectric devices, photovoltaic solar cells, and photon detectors. The growth of SiGe layer is difficult because SiGe alloys have different lattice constants from those of the common Si wafers, which leads to a high density of defects, including dislocations, micro-twins, cracks, and delaminations. This innovation utilizes newly developed rhombohedral epitaxy of cubic semiconductors on trigonal substrates in order to solve the lattice mismatch problem of SiGe by using trigonal single crystals like sapphire (Al2O3) as substrate to give a unique growth-orientation to the SiGe layer, which is automatically controlled at the interface upon sapphire (0001). This technology is different from previous silicon on insulator (SOI) or SGOI (SiGe on insulator) technologies that use amorphous SiO2 as the growth plane. A cubic semiconductor crystal is a special case of a rhombohedron with the inter-planar angle, alpha = 90 deg. With a mathematical transformation, all rhombohedrons can be described by trigonal crystal lattice structures. Therefore, all cubic lattice constants and crystal planes (hkl) s can be transformed into those of trigonal crystal parameters. These unique alignments enable a new opportunity of perfect lattice matching conditions, which can eliminate misfit dislocations. Previously, these atomic alignments were thought to be impossible or very difficult. With the invention of a new x-ray diffraction measurement method here, growth of cubic semiconductors on trigonal crystals became possible. This epitaxy and lattice-matching condition can be applied not only to SiGe (111)/sapphire (0001) substrate relations, but also to other crystal structures and other materials, including similar crystal structures which have pointgroup rotational symmetries by 120 because the cubic (111) direction has 120 rotational symmetry. The use of slightly miscut (less than plus or minus 10 deg.) sapphire (0001) substrate can be used to improve epitaxial relationships better by providing attractive atomic steps in the epitaxial process.

Choi, Sang↗

Multiloop Rapid-Rise/Rapid Fall High-Voltage Power Supply

A proposed multiloop power supply would generate a potential as high as 1.25 kV with rise and fall times <100 s. This power supply would, moreover, be programmable to generate output potentials from 20 to 1,250 V and would be capable of supplying a current of at least 300 A at 1,250 V. This power supply is intended to be a means of electronic shuttering of a microchannel plate that would be used to intensify the output of a charge-coupled-device imager to obtain exposure times as short as 1 ms. The basic design of this power supply could also be adapted to other applications in which high voltages and high slew rates are needed. At the time of reporting the information for this article, there was no commercially available power supply capable of satisfying the stated combination of voltage, rise-time, and fall-time requirements. The power supply would include a preregulator that would be used to program a voltage 1/30 of the desired output voltage. By means of a circuit that would include a pulse-width modulator (PWM), two voltage doublers, and a transformer having two primary and two secondary windings, the preregulator output voltage would be amplified by a factor of 30. A resistor would limit the current by controlling a drive voltage applied to field-effect transistors (FETs) during turn-on of the PWM. Two feedback loops would be used to regulate the high output voltage. A pulse transformer would be used to turn on four FETs to short-circuit output capacitors when the outputs of the PWM were disabled. Application of a 0-to-5-V square to a PWM shut-down pin would cause a 20-to-1,250-V square wave to appear at the output.

Bearden, Douglas↗

Maintaining Stability During a Conducted-Ripple EMC Test

An improved technique, and electronic circuitry to implement the technique, have been developed for a military-standard electromagnetic-compatibility (EMC) test in which one analyzes susceptibility to low-frequency ripple conducted into the equipment under test via a DC power line. In the traditional technique for performing the particular test, the ripple is coupled onto the DC power line via a transformer. Depending upon some design details of the equipment under test, the inductance of the transformer can contribute a degree of instability that results in an oscillation of amplitude large enough to destroy the equipment. It is usually possible to suppress the oscillation by connecting a damping resistor to the primary terminals of the ripple-injection transformer. However, it is important to emphasize the usually in the preceding sentence: sometimes, the resistive damping becomes insufficient to suppress destructive oscillation. In addition, undesirably, the resistor contributes to power dissipation and power demand, and thereby also necessitates the use of a larger ripple voltage amplifier. Yet another disadvantage of the transformer-coupling technique is that the transformer introduces low-frequency distortion of the injected ripple voltage. The improved technique makes it possible to inject ripple with very low distortion at low frequency, without inducing oscillation. In this technique, a transformer is not used: Instead, power is fed to the equipment under test via series power field-effect transistors (FETs) controlled by a summing operational amplifier. One of the inputs to the amplifier controls the DC component of the power-line voltage; the other input, generated by an external oscillator, controls the ripple component. The circuitry for implementing this technique includes panel displays, an internal power supply for the operational amplifier and panel displays, and amplitude controls for the DC and ripple powerline voltage components.

Vorperian, Vatche↗

Analog Nonvolatile Computer Memory Circuits

In nonvolatile random-access memory (RAM) circuits of a proposed type, digital data would be stored in analog form in ferroelectric field-effect transistors (FFETs). This type of memory circuit would offer advantages over prior volatile and nonvolatile types: In a conventional complementary metal oxide/semiconductor static RAM, six transistors must be used to store one bit, and storage is volatile in that data are lost when power is turned off. In a conventional dynamic RAM, three transistors must be used to store one bit, and the stored bit must be refreshed every few milliseconds. In contrast, in a RAM according to the proposal, data would be retained when power was turned off, each memory cell would contain only two FFETs, and the cell could store multiple bits (the exact number of bits depending on the specific design). Conventional flash memory circuits afford nonvolatile storage, but they operate at reading and writing times of the order of thousands of conventional computer memory reading and writing times and, hence, are suitable for use only as off-line storage devices. In addition, flash memories cease to function after limited numbers of writing cycles. The proposed memory circuits would not be subject to either of these limitations. Prior developmental nonvolatile ferroelectric memories are limited to one bit per cell, whereas, as stated above, the proposed memories would not be so limited. The design of a memory circuit according to the proposal must reflect the fact that FFET storage is only partly nonvolatile, in that the signal stored in an FFET decays gradually over time. (Retention times of some advanced FFETs exceed ten years.) Instead of storing a single bit of data as either a positively or negatively saturated state in a ferroelectric device, each memory cell according to the proposal would store two values. The two FFETs in each cell would be denoted the storage FFET and the control FFET. The storage FFET would store an analog signal value, between the positive and negative FFET saturation values. This signal value would represent a numerical value of interest corresponding to multiple bits: for example, if the memory circuit were designed to distinguish among 16 different analog values, then each cell could store 4 bits. Simultaneously with writing the signal value in the storage FFET, a negative saturation signal value would be stored in the control FFET. The decay of this control-FFET signal from the saturation value would serve as a model of the decay, for use in regenerating the numerical value of interest from its decaying analog signal value. The memory circuit would include addressing, reading, and writing circuitry that would have features in common with the corresponding parts of other memory circuits, but would also have several distinctive features. The writing circuitry would include a digital-to-analog converter (DAC); the reading circuitry would include an analog-to-digital converter (ADC). For writing a numerical value of interest in a given cell, that cell would be addressed, the saturation value would be written in the control FFET in that cell, and the non-saturation analog value representing the numerical value of interest would be generated by use of the DAC and stored in the storage FFET in that cell. For reading the numerical value of interest stored in a given cell, the cell would be addressed, the ADC would convert the decaying control and storage analog signal values to digital values, and an associated fast digital processing circuit would regenerate the numerical value from digital values.

MacLeod, Todd↗