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We present initial results for the thin epitaxial Xilinx Virtex-4 Fie ld Programmable Gate Array (FPGA), and compare to previous results ob tained for the Virtex-II and Virtex-II Pro. The data presented was a cquired through a consortium based effort with the common goal of pr oviding the space community with data and mitigation methods for the use of Xilinx FPGAs in space.
We report on the development of a hardware platform for integrated tuning and closed-loop operation of MEMS gyroscopes. The platform was developed and tested for the second generation JPL/Boeing Post-Resonator MEMS gyroscope. The control of this device is implemented through a digital design on a Field Programmable Gate Array (FPGA). A software interface allows the user to configure, calibrate, and tune the bias voltages on the micro-gyro. The interface easily transitions to an embedded solution that allows for the miniaturization of the system to a single chip.
Radiation Environmental Modeling is crucial to proper predictive modeling and electronic response to the radiation environment. When compared to on-orbit data, CREME96 has been shown to be inaccurate in predicting the radiation environment. The NEDD bases much of its radiation environment data on CREME96 output. Close coordination and partnership with DoD radiation-hardened efforts will result in leveraged - not duplicated or independently developed - technology capabilities of: a) Radiation-hardened, reconfigurable FPGA-based electronics; and b) High Performance Processors (NOT duplication or independent development).
The increased role of unmanned aerial vehicles (UAV) in NASA's suborbital program has created a strong interest in the development of instruments with new capabilities, more compact sizes and reduced weights than the instruments currently operated on manned aircrafts. There is a strong demand and tremendous potential for using high altitude UAV (HUAV) to carry weather radars for measurements of reflectivity and wind fields from tropical storms. Tropical storm genesis frequently occurs in ocean regions that are inaccessible to piloted aircraft due to the long off shore range and the required periods of time to gather significant data. Important factors of interest for the study of hurricane genesis include surface winds, profiled winds, sea surface temperatures, precipitation, and boundary layer conditions. Current satellite precipitation and surface wind sensors have resolutions that are too large and revisit times that are too infrequent to study this problem. Furthermore, none of the spaceborne sensors measure winds within the storm itself. A dual beam X-band Doppler radar, UAV Radar (URAD), is under development at the NASA Goddard Space Flight Center for the study of tropical storms from HUAV platforms, such as a Global Hawk. X-band is the most desirable frequency for airborne weather radars since these can be built in a relatively compact size using off-the-shelf components which cost significantly less than other higher frequency radars. Furthermore, X-band radars provide good sensitivity with tolerable attenuation in storms. The low-cost and light-weight URAD will provide new capabilities for studying hurricane genesis by analyzing the vertical structure of tropical cyclones as well as 3D reflectivity and wind fields in clouds. It will enable us to measure both the 3D precipitation structure and surface winds by using two antenna beams: fixed nadir and conical scanning each produced by its associated subsystem. The nadir subsystem is a magnetron based radar modified from a marine radar transceiver. It is capable of measuring vertical reflectivity and velocity profile while being a lower-cost, smaller size, and lighter weight version of the NASA ER-2 Doppler Radar (EDOP), which has flown during many NASA field campaigns and has provided valuable scientific information on hurricanes and weather phenomena. Unfortunately, EDOP is too large and heavy for most UAV platforms, but the experience gained with this instrument provided us with the heritage to build a new low-cost, light-weight, smaller system that will be capable of flying on UAVs. The scanning subsystem uses a TWT transmitter and provides measurements of 3D reflectivity/wind fields in-clouds. Conical scanning of the radar beam at a 35 deg. incidence angle will also provide information of surface wind speed and direction derived from the surface return over a single 360 deg. sweep. URAD data system will be Linux based with the capability of autonomous operation. It will utilize cutting edge digital receiver and FPGA technologies to carry out the data acquisition and processing tasks. High speed navigation data from the aircraft will also be captured and saved along with radar data for 3D measurement field reconstruction and aircraft motion correction. There is a tremendous potential for UAVs to carry down-looking weather radars for measurements of reflectivity, horizontal and vertical winds from tropical storms. With operation from HUAV platforms, the dual beam X-band radar under development promises to provide greatly needed information for tropical storm research.
According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.
The present invention presents an optical encoder with increased conversion rates. Improvement in the conversion rate is a result of combining changes in the pattern recognition encoder's scale pattern with an image sensor readout technique which takes full advantage of those changes, and lends itself to operation by modern, high-speed, ultra-compact microprocessors and digital signal processors (DSP) or field programmable gate array (FPGA) logic elements which can process encoder scale images at the highest speeds. Through these improvements, all three components of conversion time (reciprocal conversion rate)--namely exposure time, image readout time, and image processing time--are minimized.
In this paper we present protograph codes with a small number of degree-3 nodes and one high degree node. The iterative decoding threshold for proposed rate 1/2 codes are lower, by about 0.2 dB, than the best known irregular LDPC codes with degree at least 3. The main motivation is to gain linear minimum distance to achieve low error floor. Also to construct rate-compatible protograph-based LDPC codes for fixed block length that simultaneously achieves low iterative decoding threshold and linear minimum distance. We start with a rate 1/2 protograph LDPC code with degree-3 nodes and one high degree node. Higher rate codes are obtained by connecting check nodes with degree-2 non-transmitted nodes. This is equivalent to constraint combining in the protograph. The condition where all constraints are combined corresponds to the highest rate code. This constraint must be connected to nodes of degree at least three for the graph to have linear minimum distance. Thus having node degree at least 3 for rate 1/2 guarantees linear minimum distance property to be preserved for higher rates. Through examples we show that the iterative decoding threshold as low as 0.544 dB can be achieved for small protographs with node degrees at least three. A family of low- to high-rate codes with minimum distance linearly increasing in block size and with capacity-approaching performance thresholds is presented. FPGA simulation results for a few example codes show that the proposed codes perform as predicted.
A low-complexity, adaptive predictive technique for lossless compression of hyperspectral imagery is described. This technique is designed to be suitable for implementation in hardware such as a field programmable gate array (FPGA); such an implementation could be used for high-speed compression of hyperspectral imagery onboard a spacecraft. The predictive step of the technique makes use of the sign algorithm, which is a relative of the least mean square (LMS) algorithm from the field of low-complexity adaptive filtering. The compressed data stream consists of prediction residuals encoded using a method similar to that of the JPEG-LS lossless image compression standard. Compression results are presented for several datasets including some raw Airborne Visible/ Infrared Imaging Spectrometer (AVIRIS) datasets and raw Atmospheric Infrared Sounder (AIRS) datasets. The compression effectiveness obtained with the technique is competitive with that of the best of previously described techniques with similar complexity.
The Radiation Hardened Electronics for Space Environments (RHESE) project consists of a series of tasks designed to develop and mature a broad spectrum of radiation hardened and low temperature electronics technologies. Three approaches are being taken to address radiation hardening: improved material hardness, design techniques to improve radiation tolerance, and software methods to improve radiation tolerance. Within these approaches various technology products are being addressed including Field Programmable Gate Arrays (FPGA), Field Programmable Analog Arrays (FPAA), MEMS, Serial Processors, Reconfigurable Processors, and Parallel Processors. In addition to radiation hardening, low temperature extremes are addressed with a focus on material and design approaches. System level applications for the RHESE technology products are discussed.
Beginning with the launch of the Lunar Reconnaissance Orbiter (LRO) in October of 2008, NASA will once again begin its quest to land humans on the Moon. This effort will require the development of new spacecraft which will safely transport people from the Earth to the Moon and back again, as well as robotic probes tagged with science, re-supply, and communication duties. In addition to the next-generation spacecraft currently under construction, including the Orion capsule, NASA is also investigating and developing cutting edge navigation sensors which will allow for autonomous state estimation in low Earth orbit (LEO) and cislunar space. Such instruments could provide an extra layer of redundancy in avionics systems and reduce the reliance on support and on the Deep Space Network (DSN). One such sensor is the weak-signal Global Positioning System (GPS) receiver "Navigator" being developed at NASA's Goddard Space Flight Center (GSFC). At the heart of the Navigator is a Field Programmable Gate Array (FPGA) based acquisition engine. This engine allows for the rapid acquisition/reacquisition of strong GPS signals, enabling the receiver to quickly recover from outages due to blocked satellites or atmospheric entry. Additionally, the acquisition algorithm provides significantly lower sensitivities than a conventional space-based GPS receiver, permitting it to acquire satellites well above the GPS constellation. This paper assesses the performance of the Navigator receiver based upon three of the major flight regimes of a manned lunar mission: Earth ascent, cislunar navigation, and entry. Representative trajectories for each of these segments were provided by NASA. The Navigator receiver was connected to a Spirent GPS signal generator, to allow for the collection of real-time, hardware-in-the-loop results for each phase of the flight. For each of the flight segments, the Navigator was tested on its ability to acquire and track GPS satellites under the dynamical environment unique to that trajectory.
We present guidel!nes to reduce risk to an acceptable level when using complex devices in space applications. Application to Virtex 4 Field Programmable Gate Array (FPGA) on Express Logistic Carrier (ELC) project is presented.
This viewgraph presentation addresses the integrated cycling and component selection technologies for aerospace systems. The topics include: 1) Semiconductors: The Evolution of ICs - Availability and Technology; 2) IC Selection Requirements - three fields of thought, "The Good", "The Bad" and "The Ugly"; 3) Reliability and Radiation; 4) Radiation Perspective-Four methods of selecting ICs for space systems, Guaranteed hardness, historical ground-based radiation data, historical flight usage, and unknown assurance; 5) Understanding Risk, including risk trade space and ASICs and FPGA sample selection criteria.
Single-event upsets (SEUs) pose great threats to avionic systems state machine control logic, which are frequently used to control sequence of events and to qualify protocols. The risks of SEUs manifest in two ways: (a) the state machine s state information is changed, causing the state machine to unexpectedly transition to another state; (b) due to the asynchronous nature of SEU, the state machine's state registers become metastable, consequently causing any combinational logic associated with the metastable registers to malfunction temporarily. Effect (a) can be mitigated with methods such as triplemodular redundancy (TMR). However, effect (b) cannot be eliminated and can degrade the effectiveness of any mitigation method of effect (a). Although there is no way to completely eliminate the risk of SEU-induced errors, the risk can be made very small by use of a combination of very fast state-machine logic and error-detection logic. Therefore, one goal of two main elements of the present method is to design the fastest state-machine logic circuitry by basing it on the fastest generic state-machine design, which is that of a one-hot state machine. The other of the two main design elements is to design fast error-detection logic circuitry and to optimize it for implementation in a field-programmable gate array (FPGA) architecture: In the resulting design, the one-hot state machine is fitted with a multiple-input XNOR gate for detection of illegal states. The XNOR gate is implemented with lookup tables and with pipelines for high speed. In this method, the task of designing all the logic must be performed manually because no currently available logic synthesis software tool can produce optimal solutions of design problems of this type. However, some assistance is provided by a script, written for this purpose in the Python language (an object-oriented interpretive computer language) to automatically generate hardware description language (HDL) code from state-transition rules.
The Digital Phase Meter is based on a modified phase-locked loop. When phase alignment between the reference input and the phase-shifted metrological input is achieved, the loop locks and the phase shift of the digital phase shifter equals the phase difference that one seeks to measure. This digital phase meter is being developed for incorporation into a laser heterodyne interferometer in a metrological apparatus, but could also be adapted to other uses. Relative to prior phase meters of similar capability, including digital ones, this digital phase meter is smaller, less complex, and less expensive. The phase meter has been constructed and tested in the form of a field-programmable gate array (FPGA).
A document discusses the replication of the functionality of the onboard space-shuttle general-purpose computers (GPCs) in field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs). The purpose of the replication effort is to enable utilization of proven space-shuttle flight software and software-development facilities to the extent possible during development of software for flight computers for a new generation of launch vehicles derived from the space shuttles. The replication involves specifying the instruction set of the central processing unit and the input/output processor (IOP) of the space-shuttle GPC in a hardware description language (HDL). The HDL is synthesized to form a "core" processor in an FPGA or, less preferably, in an ASIC. The core processor can be used to create a flight-control card to be inserted into a new avionics computer. The IOP of the GPC as implemented in the core processor could be designed to support data-bus protocols other than that of a multiplexer interface adapter (MIA) used in the space shuttle. Hence, a computer containing the core processor could be tailored to communicate via the space-shuttle GPC bus and/or one or more other buses.
Tech Briefs are short announcements of innovations originating from research and development activities of the National Aeronautics and Space Administration. They emphasize information considered likely to be transferable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. Topics covered include: The Radio Frequency Health Node Wireless Sensor System; Effects of Temperature on Polymer/Carbon Chemical Sensors; Small CO2 Sensors Operate at Lower Temperature; Tele-Supervised Adaptive Ocean Sensor Fleet; Synthesis of Submillimeter Radiation for Spectroscopy; 100-GHz Phase Switch/Mixer Containing a Slot-Line Transition; Generating Ka-Band Signals Using an X-Band Vector Modulator; SiC Optically Modulated Field-Effect Transistor; Submillimeter-Wave Amplifier Module with Integrated Waveguide Transitions; Metrology System for a Large, Somewhat Flexible Telescope; Economical Implementation of a Filter Engine in an FPGA; Improved Joining of Metal Components to Composite Structures; Machined Titanium Heat-Pipe Wick Structure; Gadolinia-Doped Ceria Cathodes for Electrolysis of CO2; Utilizing Ocean Thermal Energy in a Submarine Robot; Fuel-Cell Power Systems Incorporating Mg-Based H2 Generators; Alternative OTEC Scheme for a Submarine Robot; Sensitive, Rapid Detection of Bacterial Spores; Adenosine Monophosphate-Based Detection of Bacterial Spores; Silicon Microleaks for Inlets of Mass Spectrometers; CGH Figure Testing of Aspherical Mirrors in Cold Vacuums; Series-Coupled Pairs of Silica Microresonators; Precise Stabilization of the Optical Frequency of WGMRs; Formation Flying of Components of a Large Space Telescope; Laser Metrology Heterodyne Phase-Locked Loop; Spatial Modulation Improves Performance in CTIS; High-Performance Algorithm for Solving the Diagnosis Problem; Truncation Depth Rule-of-Thumb for Convolutional Codes; Efficient Method for Optimizing Placement of Sensors.
This paper describes a new reconfigurable analog array (MA) architecture and integrated circuit (IC) used to map analog circuits that can adapt to extreme temperatures under programmable control. Algorithm-driven adaptation takes place on the RAA IC. The algorithms are implemented in a separate Field Programmable Gate Array (FPGA) IC, co-located with the RAA in the extreme temperature environment. The experiments demonstrate circuit adaptation over a wide temperature range, from extremely low temperature of -180 C to high 120 C.
Reconfigurable Field Programmable Gate Arrays (FPGAs) from Altera and Actel and an FPGA-based quick-turnApplication Specific Integrated Circuit (ASIC) from Altera were subjected to single-event testing using heavy ions. Both Altera devices (Stratix II and HardCopy II) exhibited a low latchup threshold (below an LET of 3 MeV-cm2/mg) and thus are not recommended for applications in the space radiation environment. The flash-based Actel ProASIC Plus device did not exhibit latchup to an effective LET of 75 MeV-cm2/mg at room temperature. In addition, these tests did not show flash cell charge loss (upset) or retention damage. Upset characterization of the design-level flip-flops yielded an LET threshold below 10 MeV-cm2/mg and a high LET cross section of about lxlO-6 cm2/bit for storing ones and about lxl0-7 cm2/bit for storing zeros . Thus, the ProASIC device may be suitable for critical flight applications with appropriate triple modular redundancy mitigation techniques.