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NASA NTRS2004

F-OWL: An Inference Engine for Semantic Web

Understanding and using the data and knowledge encoded in semantic web documents requires an inference engine. F-OWL is an inference engine for the semantic web language OWL language based on F-logic, an approach to defining frame-based systems in logic. F-OWL is implemented using XSB and Flora-2 and takes full advantage of their features. We describe how F-OWL computes ontology entailment and compare it with other description logic based approaches. We also describe TAGA, a trading agent environment that we have used as a test bed for F-OWL and to explore how multiagent systems can use semantic web concepts and technology.

Zou, Youyong↗

NASA NTRS2005

Figure Control of Lightweight Optical Structures

The goal of this paper is to demonstrate the use of fuzzy logic controllers in modifying the figure of a piezoceramic bimorph mirror. Non-contact electron actuation technology is used to actively control a bimorph mirror comprised two PZT-5H wafers by varying the electron flux and electron voltages. Due to electron blooming generated by the electron flux, it is difficult to develop an accurate control model for the bimorph mirror through theoretical analysis alone. The non-contact shape control system with electron flux blooming can be approximately described with a heuristic model based on experimental data. Two fuzzy logic feedback controllers are developed to control the shape of the bimorph mirror according to heuristic fuzzy inference rules generated from previous experimental results. Validation of the proposed fuzzy logic controllers is also discussed.

Main, John A.↗

NASA NTRS2004

NASA Glenn's Single-Stage Axial Compressor Facility Upgraded

NASA Glenn Research Center's Single-Stage Axial Compressor Facility was upgraded in fiscal year 2003 to expand and improve its research capabilities for testing high-speed fans and compressors. The old 3000-hp drive motor and gearbox were removed and replaced with a refurbished 7000-hp drive motor and gearbox, with a maximum output speed of 21,240 rpm. The higher horsepower rating permits testing of fans and compressors with higher pressure ratio or higher flow. A new inline torquemeter was installed to provide an alternate measurement of fan and compressor efficiency, along with the standard pressure and temperature measurements. A refurbished compressor bearing housing was also installed with bidirectional rotation capability, so that a variety of existing hardware could be tested. Four new lubrication modules with backup capability were installed for the motor, gearbox, torquemeter, and compressor bearing housing, so that in case the primary pump fails, the backup will prevent damage to the rotating hardware. The combustion air supply line for the facility inlet air system was activated to provide dry air for repeatable inlet conditions. New flow conditioning hardware was installed in the facility inlet plenum tank, which greatly reduced the inlet turbulence. The new inlet can also be easily modified to accommodate 20- or 22-in.-diameter fans and compressors, so a variety of existing hardware from other facilities (such as Glenn's 9- by 15-Foot Low-Speed Wind Tunnel) can be tested in the Single-Stage Axial Compressor Facility. An exhaust line was also installed to provide bleed capability to remove the inlet boundary layer. To improve the operation and control of the facility, a new programmable logic controller (PLC) was installed to upgrade from hardwired relay logic to software logic. The PLC also enabled the usage of human-machine interface software to allow for easier operation of the facility and easier reconfiguration of the facility controls when necessary. Finally, a new health-monitoring system was installed to measure shaft speed, shaft movement, and machine vibration on all of the rotating equipment. The system also provides automatic alarms and shutdown of the equipment when required. An integrated systems test for checkout of the facility was completed on June 17, 2003. Research testing resumed on June 30 with data obtained in support of the Ultra-Efficient Engine Technology Project's Compressor Casing Treatment Project.

Brokopp, Richard A.↗

NASA NTRS2007

Assurance of Complex Electronics. What Path Do We Take?

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled in software, such as communication protocols. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of "software-like" bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and "bugs" can be detected earlier in the development cycle, thus creating a development process for CE that will be easily maintained and configurable based on the device used.

FROM↗

NASA NTRS2007

Software Process Assurance for Complex Electronics

Complex Electronics (CE) now perform tasks that were previously handled in software, such as communication protocols. Many methods used to develop software bare a close resemblance to CE development. Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. With CE devices obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that used standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques were used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that was more easily maintained, consistent and configurable based on the device used.

Plastow, Richard A.↗

NASA NTRS2007

Filling the Assurance Gap on Complex Electronics

Many of the methods used to develop software bare a close resemblance to Complex Electronics (CE) development. CE are now programmed to perform tasks that were previously handled by software, such as communication protocols. For example, the James Webb Space Telescope will use Field Programmable Gate Arrays (FPGAs), which can have over a million logic gates, to send telemetry. System-on-chip (SoC) devices, another type of complex electronics, can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, mature software methodologies have been proposed, with slight modifications, to develop these devices. By using standardized S/W Engineering methods such as checklists, missing requirements and bugs can be detected earlier in the development cycle, thus creating a development process for CE that can be easily maintained and configurable based on the device used.

Plastow, Richard A.↗

NASA NTRS2007

Software Process Assurance for Complex Electronics (SPACE)

Complex Electronics (CE) are now programmed to perform tasks that were previously handled in software, such as communication protocols. Many of the methods used to develop software bare a close resemblance to CE development. For instance, Field Programmable Gate Arrays (FPGAs) can have over a million logic gates while system-on-chip (SOC) devices can combine a microprocessor, input and output channels, and sometimes an FPGA for programmability. With this increased intricacy, the possibility of software-like bugs such as incorrect design, logic, and unexpected interactions within the logic is great. Since CE devices are obscuring the hardware/software boundary, we propose that mature software methodologies may be utilized with slight modifications in the development of these devices. Software Process Assurance for Complex Electronics (SPACE) is a research project that looks at using standardized S/W Assurance/Engineering practices to provide an assurance framework for development activities. Tools such as checklists, best practices and techniques can be used to detect missing requirements and bugs earlier in the development cycle creating a development process for CE that will be more easily maintained, consistent and configurable based on the device used.

Plastow, Richard A.↗

NASA NTRS1987

Pointing compensation system for spacecraft instruments

A closed loop system reduces pointing errors in one or more spacecraft instruments. Associated with each instrument is a electronics package (3) for commanding motion in that instrument and a pointing control system (5) for imparting motion in that instrument in response to a command (4) from the commanding package (3). Spacecraft motion compensation logic (25) compensates for instrument pointing errors caused by instrument-motion-induced spacecraft motion. Any finite number of instruments can be so compensated, by providing each pointing control system (5) and each commanding package (3), for the instruments desired to be compensated, with a link to the spacecraft motion compensation logic (25). The spacecraft motion compensation logic (25) is an electronic manifestation of the algebraic negative of a model of the dynamics of motion of the spacecraft. An example of a suitable model, and computer-simulated results, are presented.

Plescia, Carl T.↗

NASA NTRS1987

Method and apparatus for characterizing propagation delays of integrated circuit devices

Propagation delay of a signal through a channel is measured by cyclically generating a first step-wave signal for transmission through the channel to a two-input logic element and a second step-wave signal with a controlled delay to the second input terminal of the logic element. The logic element determines which signal is present first at its input terminals and stores a binary signal indicative of that determination for control of the delay of the second signal which is advanced or retarded for the next cycle until both the propagation delayed first step-wave signal and the control delayed step-wave signal are coincident. The propagation delay of the channel is then determined by measuring the time between the first and second step-wave signals out of the controlled step-wave signal generator.

Blaes, Brent R.↗

NASA NTRS1989

Multi-port, optically addressed RAM

A random access memory addressing system utilizing optical links between memory and the read/write logic circuits comprises addressing circuits including a plurality of light signal sources, a plurality of optical gates including optical detectors associated with the memory cells, and a holographic optical element adapted to reflect and direct the light signals to the desired memory cell locations. More particularly, it is a multi-port, binary computer memory for interfacing with a plurality of computers. There are a plurality of storage cells for containing bits of binary information, the storage cells being disposed at the intersections of a plurality of row conductors and a plurality of column conductors. There is interfacing logic for receiving information from the computers directing access to ones of the storage cells. There are first light sources associated with the interfacing logic for transmitting a first light beam with the access information modulated thereon. First light detectors are associated with the storage cells for receiving the first light beam, for generating an electrical signal containing the access information, and for conducting the electrical signal to the one of the storage cells to which it is directed. There are holographic optical elements for reflecting the first light beam from the first light sources to the first light detectors.

Johnston, Alan R.↗

NASA NTRS1990

High-speed dynamic domino circuit implemented with gaas mesfets

A dynamic logic circuit (AND or OR) utilizes one depletion-mode metal-semiconductor FET for precharging an internal node A, and a plurality of the same type of FETs in series, or a FET in parallel with one or more of the series connected FETs for implementing the logic function. A pair of FETs are connected to provide an output inverter with two series diodes for level shift. A coupling capacitor may be employed with a further FET to provide level shifting required between the inverter and the logic circuit output terminal. These circuits may be cascaded to form a domino chain.

Yang, Long↗

NASA NTRS2007

Circuit and Method for Communication Over DC Power Line

A circuit and method for transmitting and receiving on-off-keyed (OOK) signals with fractional signal-to-noise ratios uses available high-temperature silicon- on-insulator (SOI) components to move computational, sensing, and actuation abilities closer to high-temperature or high-ionizing radiation environments such as vehicle engine compartments, deep-hole drilling environments, industrial control and monitoring of processes like smelting, and operations near nuclear reactors and in space. This device allows for the networking of multiple, like nodes to each other and to a central processor. It can do this with nothing more than the already in-situ power wiring of the system. The device s microprocessor allows it to make intelligent decisions within the vehicle operational loop and to effect control outputs to its associated actuators. The figure illustrates how each node converts digital serial data to OOK 18-kHz in transmit mode and vice-versa in receive mode; though operations at lower frequencies or up to a megahertz are within reason using this method and these parts. This innovation s technique modulates a DC power bus with millivolt-level signals through a MOSFET (metal oxide semiconductor field effect transistor) and resistor by OOK. It receives and demodulates this signal from the DC power bus through capacitive coupling at high temperature and in high ionizing radiation environments. The demodulation of the OOK signal is accomplished by using an asynchronous quadrature detection technique realized by a quasi-discrete Fourier transform through use of the quadrature components (0 and 90 phases) of the carrier frequency as generated by the microcontroller and as a function of the selected crystal frequency driving its oscillator. The detected signal is rectified using an absolute-value circuit containing no diodes (diodes being non-operational at high temperatures), and only operational amplifiers. The absolute values of the two phases of the received signal are then summed and hard limited (digitized) by comparing them to a reference level and are then input into a microprocessor as a serial bit stream. The quasi-discrete Fourier transform is performed in high-temperature components (operational amplifiers, analog switches, resistors, and capacitors). The demodulated signal is a serial data stream that is input to the UART (universal asynchronous receiver transmitter) receiver pin of the microprocessor. The OOK of the carrier frequency uses the output of the UART pin as an enabling signal that drives the gate of the MOSFET. Logic low bits enable the carrier frequency (realized by using the 0 phase signal from the microcontroller, though either phase may be used) to be DC-coupled to the power supply bus through a current-limiting resistor mounted between the MOSFET drain and the supply rail. The presence of logic lows on the power supply rail is realized by carrier bursts while logic highs are realized by the absence of bursts.

Krasowski, Michael J.↗

NASA NTRS2010

Decision Engines for Software Analysis Using Satisfiability Modulo Theories Solvers

The area of software analysis, testing and verification is now undergoing a revolution thanks to the use of automated and scalable support for logical methods. A well-recognized premise is that at the core of software analysis engines is invariably a component using logical formulas for describing states and transformations between system states. The process of using this information for discovering and checking program properties (including such important properties as safety and security) amounts to automatic theorem proving. In particular, theorem provers that directly support common software constructs offer a compelling basis. Such provers are commonly called satisfiability modulo theories (SMT) solvers. Z3 is a state-of-the-art SMT solver. It is developed at Microsoft Research. It can be used to check the satisfiability of logical formulas over one or more theories such as arithmetic, bit-vectors, lists, records and arrays. The talk describes some of the technology behind modern SMT solvers, including the solver Z3. Z3 is currently mainly targeted at solving problems that arise in software analysis and verification. It has been applied to various contexts, such as systems for dynamic symbolic simulation (Pex, SAGE, Vigilante), for program verification and extended static checking (Spec#/Boggie, VCC, HAVOC), for software model checking (Yogi, SLAM), model-based design (FORMULA), security protocol code (F7), program run-time analysis and invariant generation (VS3). We will describe how it integrates support for a variety of theories that arise naturally in the context of the applications. There are several new promising avenues and the talk will touch on some of these and the challenges related to SMT solvers. Proceedings

Bjorner, Nikolaj↗

NASA NTRS2011

Interface Supports Multiple Broadcast Transceivers for Flight Applications

A wireless avionics interface provides a mechanism for managing multiple broadcast transceivers. This interface isolates the control logic required to support multiple transceivers so that the flight application does not have to manage wireless transceivers. All of the logic to select transceivers, detect transmitter and receiver faults, and take autonomous recovery action is contained in the interface, which is not restricted to using wireless transceivers. Wired, wireless, and mixed transceiver technologies are supported. This design s use of broadcast data technology provides inherent cross strapping of data links. This greatly simplifies the design of redundant flight subsystems. The interface fully exploits the broadcast data link to determine the health of other transceivers used to detect and isolate faults for fault recovery. The interface uses simplified control logic, which can be implemented as an intellectual-property (IP) core in a field-programmable gate array (FPGA). The interface arbitrates the reception of inbound data traffic appearing on multiple receivers. It arbitrates the transmission of outbound traffic. This system also monitors broadcast data traffic to determine the health of transmitters in the network, and then uses this health information to make autonomous decisions for routing traffic through transceivers. Multiple selection strategies are supported, like having an active transceiver with the secondary transceiver powered off except to send periodic health status reports. Transceivers can operate in round-robin for load-sharing and graceful degradation.

Block, Gary L.↗

NASA NTRS2006

Mercury Shopping Cart Interface

Mercury Shopping Cart Interface (MSCI) is a reusable component of the Power User Interface 5.0 (PUI) program described in another article. MSCI is a means of encapsulating the logic and information needed to describe an orderable item consistent with Mercury Shopping Cart service protocol. Designed to be used with Web-browser software, MSCI generates Hypertext Markup Language (HTML) pages on which ordering information can be entered. MSCI comprises two types of Practical Extraction and Report Language (PERL) modules: template modules and shopping-cart logic modules. Template modules generate HTML pages for entering the required ordering details and enable submission of the order via a Hypertext Transfer Protocol (HTTP) post. Shopping cart modules encapsulate the logic and data needed to describe an individual orderable item to the Mercury Shopping Cart service. These modules evaluate information entered by the user to determine whether it is sufficient for the Shopping Cart service to process the order. Once an order has been passed from MSCI to a deployed Mercury Shopping Cart server, there is no further interaction with the user.

Pfister, Robin↗

NASA NTRS2005

Training Software in Artificial-Intelligence Computing Techniques

The Artificial Intelligence (AI) Toolkit is a computer program for training scientists, engineers, and university students in three soft-computing techniques (fuzzy logic, neural networks, and genetic algorithms) used in artificial-intelligence applications. The program promotes an easily understandable tutorial interface, including an interactive graphical component through which the user can gain hands-on experience in soft-computing techniques applied to realistic example problems. The tutorial provides step-by-step instructions on the workings of soft-computing technology, whereas the hands-on examples allow interaction and reinforcement of the techniques explained throughout the tutorial. In the fuzzy-logic example, a user can interact with a robot and an obstacle course to verify how fuzzy logic is used to command a rover traverse from an arbitrary start to the goal location. For the genetic algorithm example, the problem is to determine the minimum-length path for visiting a user-chosen set of planets in the solar system. For the neural-network example, the problem is to decide, on the basis of input data on physical characteristics, whether a person is a man, woman, or child. The AI Toolkit is compatible with the Windows 95,98, ME, NT 4.0, 2000, and XP operating systems. A computer having a processor speed of at least 300 MHz, and random-access memory of at least 56MB is recommended for optimal performance. The program can be run on a slower computer having less memory, but some functions may not be executed properly.

Howard, Ayanna↗

NASA NTRS2005

Fast Algorithms for Model-Based Diagnosis

Two improved new methods for automated diagnosis of complex engineering systems involve the use of novel algorithms that are more efficient than prior algorithms used for the same purpose. Both the recently developed algorithms and the prior algorithms in question are instances of model-based diagnosis, which is based on exploring the logical inconsistency between an observation and a description of a system to be diagnosed. As engineering systems grow more complex and increasingly autonomous in their functions, the need for automated diagnosis increases concomitantly. In model-based diagnosis, the function of each component and the interconnections among all the components of the system to be diagnosed (for example, see figure) are represented as a logical system, called the system description (SD). Hence, the expected behavior of the system is the set of logical consequences of the SD. Faulty components lead to inconsistency between the observed behaviors of the system and the SD. The task of finding the faulty components (diagnosis) reduces to finding the components, the abnormalities of which could explain all the inconsistencies. Of course, the meaningful solution should be a minimal set of faulty components (called a minimal diagnosis), because the trivial solution, in which all components are assumed to be faulty, always explains all inconsistencies. Although the prior algorithms in question implement powerful methods of diagnosis, they are not practical because they essentially require exhaustive searches among all possible combinations of faulty components and therefore entail the amounts of computation that grow exponentially with the number of components of the system.

Fijany, Amir↗

NASA NTRS2005

Full-Circle Resolver-to-Linear-Analog Converter

A circuit generates sinusoidal excitation signals for a shaft-angle resolver and, like the arctangent circuit described in the preceding article, generates an analog voltage proportional to the shaft angle. The disadvantages of the circuit described in the preceding article arise from the fact that it must be made from precise analog subcircuits, including a functional block capable of implementing some trigonometric identities; this circuitry tends to be expensive, sensitive to noise, and susceptible to errors caused by temperature-induced drifts and imprecise matching of gains and phases. These disadvantages are overcome by the design of the present circuit. The present circuit (see figure) includes an excitation circuit, which generates signals Ksin(Omega(t)) and Kcos(Omega(t)) [where K is an amplitude, Omega denotes 2(pi)x a carrier frequency (the design value of which is 10 kHz), and t denotes time]. These signals are applied to the excitation terminals of a shaft-angle resolver, causing the resolver to put out signals C sin(Omega(t)-Theta) and C cos(Omega(t)-Theta). The cosine excitation signal and the cosine resolver output signal are processed through inverting comparator circuits, which are configured to function as inverting squarers, to obtain logic-level or square-wave signals .-LL[cos(Omega(t)] and -LL[cos(Omega(t)-Theta)], respectively. These signals are fed as inputs to a block containing digital logic circuits that effectively measure the phase difference (which equals Theta between the two logic-level signals). The output of this block is a pulse-width-modulated signal, PWM(Theta), the time-averaged value of which ranges from 0 to 5 VDC as Theta ranges from .180 to +180deg. PWM(Theta) is fed to a block of amplifying and level-shifting circuitry, which converts the input PWM waveform to an output waveform that switches between precise reference voltage levels of +10 and -10 V. This waveform is processed by a two-pole, low-pass filter, which removes the carrier-frequency component. The final output signal is a DC potential, proportional to Theta that ranges continuously from -10 V at Theta = -180deg to +10 V at Theta = +180deg..

Alhorn, Dean C.↗