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At least 685 records · Page 38

Down-to-earth supercomputing at NASA Ames

The requirements for computers for aerospace vehicle design problems, in particular fluid dynamics, are examined. The levels of approximation to Navier-Stokes equations are: (1) linearized inviscid form, (2) nonlinear inviscid equation, (3) Reynolds-averaged Navier-Stokes equation, (4) large eddy simulation with models for subgrid scale turbulence, and (5) full Navier-Stokes equations to calculate laminar/turbulent transition and turbulence dissipation. The Cray 2 with 256 megaword memory and 4.1 nsec clock and the Cray X-MP/48 with a 128 megaword memory and a 9.5 nsec clock of the Ames facility are described, and an example revealing their applicability is presented. The use of zonal methods to simulate aerodynamic flow fields numerically is discussed. Consideration is given to the development of a program for simulation of aerodynamic flow fields, the compilers, symbolic debuggers, the scheduling of multiple CPUs, and the analysis and storage of the data.

Stevens, Kenneth G., Jr.↗

VLSI Reed Solomon decoder design

A Reed Solomon code is a highly efficient error correcting code that NASA will use in future space communication missions. A VLSI implementation of the decoder is presented that accepts data rates of 80 Mbits/second. A total of seven chips are needed and operate with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field operations per second are achieved with this chip set.

Maki, Gary K.↗

Multitasking the code ARC3D

The CRAY multitasking system was developed in order to utilize all four processors and sharply reduce the wall clock run time. This paper describes the techniques used to modify the computational fluid dynamics code ARC3D for this run and analyzes the achieved speedup. The ARC3D code solves either the Euler or thin-layer N-S equations using an implicit approximate factorization scheme. Results indicate that multitask processing can be used to achieve wall clock speedup factors of over three times, depending on the nature of the program code being used. Multitasking appears to be particularly advantageous for large-memory problems running on multiple CPU computers.

Barton, John T.↗

Electronic Neural-Network Simulator

Experimental circuits faster than simulation programs run on digital computers. Serial shift register routes clock pulses C1 to neurons in sequence. Clock pulses C2 interrogate neurons. Neuron interconnection information stored in simulated synapses. Can be expanded to greater complexity.

Moopenn, Alex W.↗

Fast Synchronization With Burst-Mode Digital Signals

Oscillator quickly synchronized with data clock. Sampling clock synchronized with sinusoid by feedback technique. Signal is measure of phase-error angle theta and generated digitally by technique related to calculation of theta from periodic samples of sinusoid.

Lee, Lin-Nan↗

Optical communication with semiconductor laser diodes

Slot timing recovery in a direct detection optical PPM communication system can be achieved by processing the photodetector waveform with a nonlinear device whose output forms the input to a phase lock group. The choice of a simple transition detector as the nonlinearity is shown to give satisfactory synchronization performance. The rms phase error of the recovered slot clock and the effect of slot timing jitter on the bit error probability were directly measured. The experimental system consisted of an AlGaAs laser diode (lambda = 834 nm) and a silicon avalanche photodiode (APD) photodetector and used Q=4 PPM signaling operated at a source data rate of 25 megabits/second. The mathematical model developed to characterize system performance is shown to be in good agreement with actual performance measurements. The use of the recovered slot clock in the receiver resulted in no degradation in receiver sensitivity compared to a system with perfect slot timing. The system achieved a bit error probability of 10 to the minus 6 power at received signal energies corresponding to an average of less than 60 detected photons per information bit.

Davidson, F.↗

High data rate Reed-Solomon encoding and decoding using VLSI technology

Presented as an implementation of a Reed-Solomon encode and decoder, which is 16-symbol error correcting, each symbol is 8 bits. This Reed-Solomon (RS) code is an efficient error correcting code that the National Aeronautics and Space Administration (NASA) will use in future space communications missions. A Very Large Scale Integration (VLSI) implementation of the encoder and decoder accepts data rates up 80 Mbps. A total of seven chips are needed for the decoder (four of the seven decoding chips are customized using 3-micron Complementary Metal Oxide Semiconduction (CMOS) technology) and one chip is required for the encoder. The decoder operates with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field (GF) operations per second are achieved with the decoder chip set and 640 MOPS are achieved with the encoder chip.

Miller, Warner↗

Relationships of earthquakes (and earthquake-associated mass movements) and polar motion as determined by Kalman filtered, Very-Long-Baseline-Interferometry

A Kalman filter was designed to yield optimal estimates of geophysical parameters from Very Long Baseline Interferometry (VLBI) group delay data. The geophysical parameters are the polar motion components, adjustments to nutation in obliquity and longitude, and a change in the length of day parameter. The VLBI clock (and clock rate) parameters and atmospheric zenith delay parameters are estimated simultaneously. Filter background is explained. The IRIS (International Radio Interferometric Surveying) VLBI data are Kalman filtered. The resulting polar motion estimates are examined. There are polar motion signatures at the times of three large earthquakes occurring in 1984 to 1986: Mexico, 19 September, 1985 (Magnitude M sub s = 8.1); Chile, 3 March, 1985 (M sub s = 7.8); and Taiwan, 14 November, 1986 (M sub s = 7.8). Breaks in polar motion occurring about 20 days after the earthquakes appear to correlate well with the onset of increased regional seismic activity and a return to more normal seismicity (respectively). While the contribution of these three earthquakes to polar motion excitations is small, the cumulative excitation due to earthquakes, or seismic phenomena over a Chandler wobble damping period may be significant. Mechanisms for polar motion excitation due to solid earth phenomena are examined. Excitation functions are computed, but the data spans are too short to draw conclusions based on these data.

Preisig, Joseph Richard Mark↗

Gallium Arsenide Domino Circuit

Advantages include reduced power and high speed. Experimental gallium arsenide field-effect-transistor (FET) domino circuit replicated in large numbers for use in dynamic-logic systems. Name of circuit denotes mode of operation, which logic signals propagate from each stage to next when successive stages operated at slightly staggered clock cycles, in manner reminiscent of dominoes falling in a row. Building block of domino circuit includes input, inverter, and level-shifting substages. Combinational logic executed in input substage. During low half of clock cycle, result of logic operation transmitted to following stage.

Yang, Long↗

A burst compression and expansion technique for variable-rate users in satellite-switched TDMA networks

A burst compression and expansion technique is described for asynchronously interconnecting variable-data-rate users with cost-efficient ground terminals in a satellite-switched, time-division-multiple-access (SS/TDMA) network. Compression and expansion buffers in each ground terminal convert between lower rate, asynchronous, continuous-user data streams and higher-rate TDMA bursts synchronized with the satellite-switched timing. The technique described uses a first-in, first-out (FIFO) memory approach which enables the use of inexpensive clock sources by both the users and the ground terminals and obviates the need for elaborate user clock synchronization processes. A continous range of data rates from kilobits per second to that approaching the modulator burst rate (hundreds of megabits per second) can be accommodated. The technique was developed for use in the NASA Lewis Research Center System Integration, Test, and Evaluation (SITE) facility. Some key features of the technique have also been implemented in the gound terminals developed at NASA Lewis for use in on-orbit evaluation of the Advanced Communications Technology Satellite (ACTS) high burst rate (HBR) system.

Budinger, James M.↗

Preliminary error budget for an optical ranging system: Range, range rate, and differenced range observables

Future missions to the outer solar system or human exploration of Mars may use telemetry systems based on optical rather than radio transmitters. Pulsed laser transmission can be used to deliver telemetry rates of about 100 kbits/sec with an efficiency of several bits for each detected photon. Navigational observables that can be derived from timing pulsed laser signals are discussed. Error budgets are presented based on nominal ground stations and spacecraft-transceiver designs. Assuming a pulsed optical uplink signal, two-way range accuracy may approach the few centimeter level imposed by the troposphere uncertainty. Angular information can be achieved from differenced one-way range using two ground stations with the accuracy limited by the length of the available baseline and by clock synchronization and troposphere errors. A method of synchronizing the ground station clocks using optical ranging measurements is presented. This could allow differenced range accuracy to reach the few centimeter troposphere limit.

Folkner, W. M.↗

A burst compression and expansion technique for variable-rate users in satellite-switched TDMA networks

A burst compression and expansion technique is described for asynchronously interconnecting variable-data-rate users with cost-efficient ground terminals in a satellite-switched, time-division-multiple-access (SS/TDMA) network. Compression and expansion buffers in each ground terminal convert between lower rate, asynchronous, continuous-user data streams and higher-rate TDMA bursts synchronized with the satellite-switched timing. The technique described uses a first-in, first-out (FIFO) memory approach which enables the use of inexpensive clock sources by both the users and the ground terminals and obviates the need for elaborate user clock synchronization processes. A continuous range of data rates from kilobits per second to that approaching the modulator burst rate (hundreds of megabits per second) can be accommodated. The technique was developed for use in the NASA Lewis Research Center System Integration, Test, and Evaluation (SITE) facility. Some key features of the technique have also been implemented in the ground terminals developed at NASA Lewis for use in on-orbit evaluation of the Advanced Communications Technology Satellite (ACTS) high burst rate (HBR) system.

Budinger, James M.↗

Word timing recovery in direct detection optical PPM communication systems with avalanche photodiodes using a phase lock loop

A technique for word timing recovery in a direct-detection optical PPM communication system is described. It tracks on back-to-back pulse pairs in the received random PPM data sequences with the use of a phase locked loop. The experimental system consisted of an 833-nm AlGaAs laser diode transmitter and a silicon avalanche photodiode photodetector, and it used Q = 4 PPM signaling at source data rate 25 Mb/s. The mathematical model developed to describe system performance is shown to be in good agreement with the experimental measurements. Use of this recovered PPM word clock with a slot clock recovery system caused no measurable penalty in receiver sensitivity. The completely self-synchronized receiver was capable of acquiring and maintaining both slot and word synchronizations for input optical signal levels as low as 20 average detected photons per information bit. The receiver achieved a bit error probability of 10 to the -6th at less than 60 average detected photons per information bit.

Sun, Xiaoli↗

Phase-lock-loop application for fiber optic receiver

Phase-locked loop circuits are frequently employed in communication systems. In recent years, digital phase-locked loop circuits were utilized in optical communications systems. In an optical transceiver system, the digital phase-locked loop circuit is connected to the output of the receiver to extract a clock signal from the received coded data (NRZ, Bi-Phase, or Manchester). The clock signal is then used to reconstruct or recover the original data from the coded data. A theoretical approach to the design of a digital phase-locked loop circuit operation at 1 and 50 MHz is described. Hardware implementation of a breadboard design to function at 1 MHz and a printed-circuit board designed to function at 50 MHz were assembled using emitter coupled logic (ECL) to verify experimentally the theoretical design.

Ruggles, Stephen L.↗

Current GPS/GLONASS time reference and UTC

The world's two global satellite navigation systems, GPS and GLONASS, will both become operational during the early 1990's. Each will offer, independently of the other, precise location and time transfer continuously anywhere in the world and indeed in space itself. Many potential users, in particular the civil aviation community, are keenly interested in a joint GPS/GLONASS operation since it would offer substantial advantages in defining and maintaining the integrity of the navigation aid. The question arises of compatibility of GPS/GLONASS from the point of view of satellite on-board clocks, their system references, their national standards and ultimately UTC. Results are presented on the characterization of GLONASS system and spacecraft clocks as compared to their Navstar GPS counterparts.

Daly, Peter↗

Rubidium atomic frequency standards for GPS Block IIR

The Rubidium Atomic Frequency Standards (RAFS) were provided for the GPS Block IIR NAVSTAR satellites. These satellites will replenish and upgrade the space segment of the Global Positioning System in the mid 1990s. The GPS RAFS Rb clocks are the latest generation of the high-performance rubidium frequency standards. They offer an aging rate in the low pp 10(exp 14)/day range and a drift-corrected 1-day stability in the low pp 10(exp 14) range. The Block IIR version of these devices will have improved performance, higher reliability, smaller size, and greater radiation hardness. The GPS Block IIR atomic clocks have a natural frequency configuration whereby they output a frequency of about 13.4 MHz that is a submultiple of the atomic resonance of Rb (or Cs). The RAFS operates at a low, fixed C-field for increased stability. The GPS Block IIR RAFS design, including the changes and improvements made, and the test results obtained are described.

Riley, William J.↗

Highly parallel computer architecture for robotic computation

In a computer having a large number of single instruction multiple data (SIMD) processors, each of the SIMD processors has two sets of three individual processor elements controlled by a master control unit and interconnected among a plurality of register file units where data is stored. The register files input and output data in synchronism with a minor cycle clock under control of two slave control units controlling the register file units connected to respective ones of the two sets of processor elements. Depending upon which ones of the register file units are enabled to store or transmit data during a particular minor clock cycle, the processor elements within an SIMD processor are connected in rings or in pipeline arrays, and may exchange data with the internal bus or with neighboring SIMD processors through interface units controlled by respective ones of the two slave control units.

Fijany, Amir↗

50 Mbps free space direct detection laser diode optical communication system with Q = 4 PPM signaling

A 50 Mbps direct detection optical communication system for use in an intersatellite link was constructed with an AlGaAs laser diode transmitter and a silicon avalanche photodiode photodetector. The system used a Q = 4 PPM format. The receiver consisted of a maximum likelihood PPM detector and a timing recovery subsystem. The PPM slot clock was recovered at the receiver by using a transition detector followed by a PLL. The PPM word clock was recovered by using a second PLL whose input was derived from the presence of back-to-back PPM pulses contained in the received random PPM pulse sequences. The system achieved a bit error rate of 0.000001 at less than 50 detected signal photons/information bit. The receiver was capable of acquiring and maintaining slot and word synchronization for received signal levels greater than 20 photons/information bit, at which the receiver bit error rate was about 0.01.

Sun, Xiaoli↗