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Design and Performance of a 2.7 THz Waveguide Tripler

The design and performance of a 0.9 THz to 2.7 THz waveguide tripler are presented. An unusual split block configuration with parallel input and output waveguides accommodates a monolithic membrane diode (MoMeD) circuit. Submicron planar GaAs Schottky diodes in single and antiparallel pairs are implemented with matching filters on a 3-micrometer thick suspended substrate as part of the MoMeD structure. The filters are a combination of short hammerheads and high-low impedance elements. Only a few circuit variations have been measured to date. The best current performance shows an output power of 0.1 microW and an efficiency of 0.002% at the band center frequency of 2.55 THz.

Maiwald, Frank↗

The Goddard VLBI SINEX Files

The Goddard VLBI group generates SINEX files for individual 24-hr sessions and multiyear TRF solutions. Each 24-hr file includes the reduced normal matrix for the station positions, EOP, and EOP rates. A global Terrestrial Reference Frame (TRF) SINEX file has the reduced normal matrix for station positions and velocities but no EOP parameters. Both types of normal matrix are free from any datum constraints and are designed for combination solutions that will later apply the necessary datum constraints. The SINEX files also contain blocks that provide the constraints and covariance of well-defined 24-hr or global TRF solutions. These blocks are not yet part of the SINEX 2.0 specification. For the TRF solutions the Goddard VLBI group also generates the corresponding EOP time series. SINEX files and EOP time series are distributed through the IVS. The algorithms for generating the various blocks and the proper use of such SINEX files will be discussed.

Ma, Chopo↗

Three-Function Logic Gate Controlled by Analog Voltage

The figure is a schematic diagram of a complementary metal oxide/semiconductor (CMOS) electronic circuit that performs one of three different logic functions, depending on the level of an externally applied control voltage, V(sub sel). Specifically, the circuit acts as A NAND gate at V(sub sel) = 0.0 V, A wire (the output equals one of the inputs) at V(sub sel) = 1.0 V, or An AND gate at V(sub sel) = -1.8 V. [The nominal power-supply potential (VDD) and logic "1" potential of this circuit is 1.8 V.] Like other multifunctional circuits described in several prior NASA Tech Briefs articles, this circuit was synthesized following an automated evolutionary approach that is so named because it is modeled partly after the repetitive trial-and-error process of biological evolution. An evolved circuit can be tested by computational simulation and/or tested in real hardware, and the results of the test can provide guidance for refining the design through further iteration. The evolutionary synthesis of electronic circuits can now be implemented by means of a software package Genetic Algorithms for Circuit Synthesis (GACS) that was developed specifically for this purpose. GACS was used to synthesize the present trifunctional circuit. As in the cases of other multifunctional circuits described in several prior NASA Tech Briefs articles, the multiple functionality of this circuit, the use of a single control voltage to select the function, and the automated evolutionary approach to synthesis all contribute synergistically to a combination of features that are potentially advantageous for the further development of robust, multiple-function logic circuits, including, especially, field-programmable gate arrays (FPGAs). These advantages include the following: This circuit contains only 9 transistors about half the number of transistors that would be needed to obtain equivalent NAND/wire/AND functionality by use of components from a standard digital design library. If multifunctional gates like this circuit were used in the place of the configurable logic blocks of present commercial FPGAs, it would be possible to change the functions of the resulting digital systems within shorter times. For example, by changing a single control voltage, one could change the function of thousands of FPGA cells within nanoseconds. In contrast, typically, the reconfiguration in a conventional FPGA by use of bits downloaded from look-up tables via a digital bus takes microseconds.

Zebulum, Ricardo↗

Engineering Innovations for Exploration Challenges

This slide presentation reviews some of the engineering innovations requirements for the challenges of space exploration which NASA has and will be involved in. It reviews some significant successes in space transportation, exploration and science accomplished during 2009, and it reviews some of the places that are available for exploration in the near term and the specific missions that NASA has assigned to Marshall. It also reviews the project lifecycle management model, that is designed to reduce undefined, but known, risks. It also demonstrates the sustainable long-term program of block upgrades that contribute to long-term success of programs.

Dumbacher, Daniel L.↗

High-Throughput, Adaptive FFT Architecture for FPGA-Based Spaceborne Data Processors

Exponential growth in microelectronics technology such as field-programmable gate arrays (FPGAs) has enabled high-performance spaceborne instruments with increasing onboard data processing capabilities. As a commonly used digital signal processing (DSP) building block, fast Fourier transform (FFT) has been of great interest in onboard data processing applications, which needs to strike a reasonable balance between high-performance (throughput, block size, etc.) and low resource usage (power, silicon footprint, etc.). It is also desirable to be designed so that a single design can be reused and adapted into instruments with different requirements. The Multi-Pass Wide Kernel FFT (MPWK-FFT) architecture was developed, in which the high-throughput benefits of the parallel FFT structure and the low resource usage of Singleton s single butterfly method is exploited. The result is a wide-kernel, multipass, adaptive FFT architecture. The 32K-point MPWK-FFT architecture includes 32 radix-2 butterflies, 64 FIFOs to store the real inputs, 64 FIFOs to store the imaginary inputs, complex twiddle factor storage, and FIFO logic to route the outputs to the correct FIFO. The inputs are stored in sequential fashion into the FIFOs, and the outputs of each butterfly are sequentially written first into the even FIFO, then the odd FIFO. Because of the order of the outputs written into the FIFOs, the depth of the even FIFOs, which are 768 each, are 1.5 times larger than the odd FIFOs, which are 512 each. The total memory needed for data storage, assuming that each sample is 36 bits, is 2.95 Mbits. The twiddle factors are stored in internal ROM inside the FPGA for fast access time. The total memory size to store the twiddle factors is 589.9Kbits. This FFT structure combines the benefits of high throughput from the parallel FFT kernels and low resource usage from the multi-pass FFT kernels with desired adaptability. Space instrument missions that need onboard FFT capabilities such as the proposed DESDynl, SWOT (Surface Water Ocean Topography), and Europa sounding radar missions would greatly benefit from this technology with significant reductions in non-recurring cost and risk.

NguyenKobayashi, Kayla↗

A Modular Framework for Modeling Hardware Elements in Distributed Engine Control Systems

Progress toward the implementation of distributed engine control in an aerospace application may be accelerated through the development of a hardware-in-the-loop (HIL) system for testing new control architectures and hardware outside of a physical test cell environment. One component required in an HIL simulation system is a high-fidelity model of the control platform: sensors, actuators, and the control law. The control system developed for the Commercial Modular Aero-Propulsion System Simulation 40k (C-MAPSS40k) provides a verifiable baseline for development of a model for simulating a distributed control architecture. This distributed controller model will contain enhanced hardware models, capturing the dynamics of the transducer and the effects of data processing, and a model of the controller network. A multilevel framework is presented that establishes three sets of interfaces in the control platform: communication with the engine (through sensors and actuators), communication between hardware and controller (over a network), and the physical connections within individual pieces of hardware. This introduces modularity at each level of the model, encouraging collaboration in the development and testing of various control schemes or hardware designs. At the hardware level, this modularity is leveraged through the creation of a SimulinkR library containing blocks for constructing smart transducer models complying with the IEEE 1451 specification. These hardware models were incorporated in a distributed version of the baseline C-MAPSS40k controller and simulations were run to compare the performance of the two models. The overall tracking ability differed only due to quantization effects in the feedback measurements in the distributed controller. Additionally, it was also found that the added complexity of the smart transducer models did not prevent real-time operation of the distributed controller model, a requirement of an HIL system.

propulsion simulation↗

Space Environment Testing of Photovoltaic Array Systems at NASA's Marshall Space Flight Center

To successfully operate a photovoltaic (PV) array system in space requires planning and testing to account for the effects of the space environment. It is critical to understand space environment interactions not only on the PV components, but also the array substrate materials, wiring harnesses, connectors, and protection circuitry (e.g. blocking diodes). Key elements of the space environment which must be accounted for in a PV system design include: Solar Photon Radiation, Charged Particle Radiation, Plasma, and Thermal Cycling. While solar photon radiation is central to generating power in PV systems, the complete spectrum includes short wavelength ultraviolet components, which photo-ionize materials, as well as long wavelength infrared which heat materials. High energy electron radiation has been demonstrated to significantly reduce the output power of III-V type PV cells; and proton radiation damages material surfaces - often impacting coverglasses and antireflective coatings. Plasma environments influence electrostatic charging of PV array materials, and must be understood to ensure that long duration arcs do not form and potentially destroy PV cells. Thermal cycling impacts all components on a PV array by inducing stresses due to thermal expansion and contraction. Given such demanding environments, and the complexity of structures and materials that form a PV array system, mission success can only be ensured through realistic testing in the laboratory. NASA's Marshall Space Flight Center has developed a broad space environment test capability to allow PV array designers and manufacturers to verify their system's integrity and avoid costly on-orbit failures. The Marshall Space Flight Center test capabilities are available to government, commercial, and university customers. Test solutions are tailored to meet the customer's needs, and can include performance assessments, such as flash testing in the case of PV cells.

Phillips, Brandon S.↗

The Utilization Profiles of the CCSDS Unified Space Link Protocol (USLP)

The purpose of this paper is to identify the utilization profiles for interfacing the Data Protocol Sublayer using the Unified Space Link Protocols (USLP) (reference 1) with the space link coding procedures as specified in the CCSDS Coding & Synchronization Blue Books (references 2 through 5), used in both telecommand and telemetry applications. This paper describes how the USLP Protocol utilizes the coding and synchronization sublayer to support: a. Direct to Earth (DTE) telemetry links for engineering and science data b. Direct to Earth (DTE) telemetry links for very high rate science data c. Direct from Earth (DFE) command, sequencing and flight software loads d. Space to Space Links (Proximity) utilized by orbiters for data exchange to/from surface bound assets. The CCSDS has divided the functions of the Data Link Layer into two sublayers: the Data Link Protocol Sublayer (DLP-SL) and the Coding and Synchronization Sublayer (CS-SL). The Data Link Protocol Sublayer (DLP-SL) interfaces to the users, accepting the data that is to be transported, on the sending side of the link, and delivering that data on the receiving end. The Transfer Frame is the data unit that is transferred across the Data Link Protocol Sublayer and the Coding and Synchronization Sublayer boundary. The Coding and Synchronization Sublayer (CS-SL) provides the encoding, randomization, and frame synchronization functions that prepares the USLP Transfer Frame for transport across the space link. The CS-SL is divided into 2 processes: 1) The Frame Interface Processes (FIP) performs the interface functions required to prepare the data for delivery to the Coding/Decoding Process (CDP). This process includes prepending a Frame Start Marker to the provided frame, when management has designated that the frame is not to be aligned to the codeblock or when there is no block code used. 2) The Coding/Decoding Process (CDP) performs the forward error correction processes that are used to optimize the performance of the link and minimize the error rate. The CDP creates the symbol stream that is delivered to the Physical Layer. The transfer of the USLP transfer frames across different types of space links is the focus of this paper. The Protocol Data Unit (PDU) that is passed in both directions between the Data Link Protocol Sublayer (DLP-SL) and Coding and Synchronization Sublayer (CS-SL) is the transfer frame. The USLP frame structure provides flexibility that can be constrained by the functions utilized within the CS-SL that prepare the transfer frame for transit. For example, the USLP transfer frame contains a length field that enables the frame to be of variable length but CS-SL under certain conditions may constrain the frame to be fixed in length. This paper describes 5 operational modes available for use by the Data Link Layer to provide data exchange across the USLP space link. These modes are different because different operational requirements apply to vastly different types of space links and thus the communications implementation requirements differ. The environmental issues include the power or energy available, the distance between the end points of the link, the complexity of the equipment available at those end points, the atmospheric conditions and radiometric frequency selection. The CS-SL utilizes different forward error correcting codes supported by specific operational modes to configure the data for transit. This paper describes all of the operational modes in a series of data models which decompose the functionality between the Data Link Protocol Sublayer and the Coding and Synchronization sublayer. The operational modes described are: 1. Uncoded Mode: has been used for short links that contain significant available power to provide an acceptable frame error rate. The frames in this mode can be variable in length and typically use an error detection algorithm (i.e., CRC) to determine if there are errors in the received frame. 2. Convolutional Only Mode: is currently the prime forward error correction coding used for the proximity links. The frames in this mode can be variable in length and typically use an error detection algorithm (i.e., CRC) to determine if there are errors in the received frame. 3. Variable Length Frame Aligned to Variable Length Codeblock (TC): is used for Direct from Earth links were power levels are high and the simple, least complex code i.e., the BCH code is used. This mode has been in use since the early 1970s. The BCH code is a short code and the decoder is easy to implement. 4. Fixed Length Frame Aligned to Fixed Length Codeblock (AOS/TM): was introduced when the concatenated Convolutional and Reed-Solomon Code was formulated to provide significant reduction in link data error rate and the ability to determine if there was an error in the decoded codeblock. The frame is aligned to the codeblock so that there is a one to one relationship of frame errors to codeblock errors without additional error detection coding being added. This mode requires the protocol frames to be the exact size of the message portion of the codeblock. 5. Frames Unaligned to Fixed Length Codeblocks (Currently used for very high rates and space to space links): This mode is currently used for missions that have a very high data rate that can be controlled adaptively as the environment changes and as the next generation operating mode for the proximity link. This mode from a coded data stream point of view is exactly like that described in 4. above, except that the frame need not be aligned to the codeblock. There is no requirement on frame length when using this mode. Thus when using USLP it can be used to support links that require short or long frames. There is also no mandatory requirement that frames cannot be separated by idle data reducing the tight data rate connection requirements between the data link protocol sublayer and the coding & synchronization sublayer. In conclusion, how these operational modes can be put to use in mission operational scenarios is described for Direct from Earth links (DFE), Direct to Earth links (DTE), and Proximity links.

Greenberg, E.↗

A Small Fission Power System with Stirling Power Conversion for NASA Science Missions

In early 2010, a joint National Aeronautics and Space Administration (NASA) and Department of Energy (DOE) study team developed a concept for a 1 kWe Fission Power System with a 15-year design life that could be available for a 2020 launch to support future NASA science missions. The baseline concept included a solid block uranium-molybdenum reactor core with embedded heat pipes and distributed thermoelectric converters directly coupled to aluminum radiator fins. A short follow-on study was conducted at NASA Glenn Research Center (GRC) to evaluate an alternative power conversion approach. The GRC study considered the use of free-piston Stirling power conversion as a substitution to the thermoelectric converters. The resulting concept enables a power increase to 3 kWe with the same reactor design and scalability to 10 kW without changing the reactor technology. This paper presents the configuration layout, system performance, mass summary, and heat transfer analysis resulting from the study.

Mason, Lee↗

The Large UV/Optical/Infrared Surveyor (LUVOIR): Decadal Mission Study Update

NASA commissioned the study of four large mission concepts, including the Large Ultraviolet / Optical / Infrared (LUVOIR) Surveyor, to be evaluated by the 2020 Decadal Survey in Astrophysics. In response, the Science and Technology Definition Team (STDT) identified a broad range of science objectives for LUVOIR that include the direct imaging and spectral characterization of habitable exoplanets around sun-like stars, the study of galaxy formation and evolution, the exchange of matter between galaxies, star and planet formation, and the remote sensing of Solar System objects. To meet these objectives, the LUVOIR Study Office, located at NASA’s Goddard Space Flight Center (GSFC), completed the first design iteration of a 15-m segmented-aperture observatory that would be launched by the Space Launch System (SLS) Block 2 configuration. The observatory includes four serviceable instruments: the Extreme Coronagraph for Living Planetary Systems (ECLIPS), an optical / near-infrared coronagraph capable of delivering 10^-10contrast at inner working angles as small as 2 O/D; the LUVOIR UV Multi-object Spectrograph (LUMOS), which will provide low- and medium-resolution UV (100 – 400 nm) multi-object imaging spectroscopy in addition to far-UV imaging; the High Definition Imager (HDI), a high-resolution wide-field-of-view NUV-Optical-NIR imager; and Pollux, a high-resolution UV spectro-polarimeter being contributed by Centre National d’Etudes Spatiales (CNES).The study team has executed a second design iteration to further improve upon the 15-m concept, while simultaneously studying an 8-m concept. In these proceedings, we provide an update on these two architectures.

space telescopes↗

A SIMULINK environment for flight dynamics and control analysis: Application to the DHC-2 Beaver. Part 1: Implementation of a model library in SIMULINK. Part 2: Nonlinear analysis of the Beaver autopilot

The design of advanced Automatic Aircraft Control Systems (AACS's) can be improved upon considerably if the designer can access all models and tools required for control system design and analysis through a graphical user-interface, from within one software environment. This MSc-thesis presents the first step in the development of such an environment, which is currently being done at the Section for Stability and Control of Delft University of Technology, Faculty of Aerospace Engineering. The environment is implemented within the commercially available software package MATLAB/SIMULINK. The report consists of two parts. Part I gives a detailed description of the AACS design environment. The heart of this environment is formed by the SIMULINK implementation of a nonlinear aircraft model in block-diagram format. The model has been worked out for the old laboratory aircraft of the Faculty, the De Havilland DHC-2 'Beaver', but due to its modular structure, it can easily be adapted for other aircraft. Part I also describes MATLAB programs which can be applied for finding steady-state trimmed-flight conditions and for linearization of the aircraft model, and it shows how the built-in simulation routines of SIMULINK have been used for open-loop analysis of the aircraft dynamics. Apart from the implementation of the models and tools, a thorough treatment of the theoretical backgrounds is presented. Part II of this report presents a part of an autopilot design process for the 'Beaver' aircraft, which clearly demonstrates the power and flexibility of the AACS design environment from part I. Evaluations of all longitudinal and lateral control laws by means of nonlinear simulations are treated in detail. The AACS design environment from part I proved to be a very useful tool for designing the control laws of the 'Beaver' autopilot within a very tight time-schedule. The autopilot design process itself will be used as a guideline for future AACS research at the Faculty of Aerospace Engineering. Flight tests of the 'Beaver' autopilot, done after evaluating the control laws in the SIMULINK package, proved to be quite successful. In the future, the AACS design package will evolve into a standardized, integrated design environment which can be applied to virtually any type of aircraft. The AACS design cycle will be shortened further by developing tools for automatically porting control laws from the MATLAB/SIMULINK environment to a piloted real-time flight simulator and the Flight Control Computers of the aircraft.

Flight Control System Design↗

The Large UV/Optical/Infrared Surveyor (LUVOIR): Decadal Mission Study Update

NASA commissioned the study of four large mission concepts, including the Large Ultraviolet / Optical / Infrared (LUVOIR) Surveyor, to be evaluated by the 2020 Decadal Survey in Astrophysics. In response, the Science and Technology Definition Team (STDT) identified a broad range of science objectives for LUVOIR that include the direct imaging and spectral characterization of habitable exoplanets around sun-like stars, the study of galaxy formation and evolution, the exchange of matter between galaxies, star and planet formation, and the remote sensing of Solar System objects. To meet these objectives, the LUVOIR Study Office, located at NASA's Goddard Space Flight Center (GSFC), completed the first design iteration of a 15-m segmented-aperture observatory that would be launched by the Space Launch System (SLS) Block 2 configuration. The observatory includes four serviceable instruments: the Extreme Coronagraph for Living Planetary Systems (ECLIPS), an optical / near-infrared coronagraph capable of delivering 10(exp -10) contrast at inner working angles as small as 2 lambda/D; the LUVOIR UV Multi-object Spectrograph (LUMOS), which will provide low- and medium-resolution UV (100 - 400 nm) multi-object imaging spectroscopy in addition to far-UV imaging; the High Definition Imager (HDI), a high-resolution wide-field-of-view NUV-Optical-NIR imager; and Pollux, a high-resolution UV spectro-polarimeter being contributed by Centre National d'Etudes Spatiales (CNES). The study team has executed a second design iteration to further improve upon the 15-m concept, while simultaneously studying an 8-m concept. In these proceedings, we provide an update on these two architectures.

cosmic origins↗

Trellises and Trellis-Based Decoding Algorithms for Linear Block Codes

Decoding algorithms based on the trellis representation of a code (block or convolutional) drastically reduce decoding complexity. The best known and most commonly used trellis-based decoding algorithm is the Viterbi algorithm. It is a maximum likelihood decoding algorithm. Convolutional codes with the Viterbi decoding have been widely used for error control in digital communications over the last two decades. This chapter is concerned with the application of the Viterbi decoding algorithm to linear block codes. First, the Viterbi algorithm is presented. Then, optimum sectionalization of a trellis to minimize the computational complexity of a Viterbi decoder is discussed and an algorithm is presented. Some design issues for IC (integrated circuit) implementation of a Viterbi decoder are considered and discussed. Finally, a new decoding algorithm based on the principle of compare-select-add is presented. This new algorithm can be applied to both block and convolutional codes and is more efficient than the conventional Viterbi algorithm based on the add-compare-select principle. This algorithm is particularly efficient for rate 1/n antipodal convolutional codes and their high-rate punctured codes. It reduces computational complexity by one-third compared with the Viterbi algorithm.

Lin, Shu↗

Clearance Analysis of Node 3 Aft CBM to the Stowed FGB Solar Array

In early 2011, the ISS Vehicle Configuration Office began considering the relocation of the Permanent Multipurpose Module (PMM) to the aft facing Common Berthing Mechanism (CBM) on Node 3 to open a berthing location for visiting vehicles on the Node 1 nadir CBM. In this position, computer-aided design (CAD) models indicated that the aft end of the PMM would be only a few inches from the stowed Functional Cargo Block (FGB) port solar array. To validate the CAD model clearance analysis, in the late summer of 2011 the Image Science and Analysis Group (ISAG) was asked to determine the true geometric relationship between the on-orbit aft facing Node 3 CBM and the FGB port solar array. The desired measurements could be computed easily by photogrammetric analysis if current imagery of the ISS hardware were obtained. Beginning in the fall of 2011, ISAG used the Dynamic Onboard Ubiquitous Graphics (DOUG) program to design a way to acquire imagery of the aft face of Node 3, the aft end-cone of Node 1, the port side of pressurized mating adapter 1 (PMA1), and the port side of the FGB out to the tip of the port solar array using cameras on the Space Station Remote Manipulator System (SSRMS). This was complicated by the need to thread the SSRMS under the truss, past Node 3 and the Cupola, and into the space between the aft side of Node 3 and the FGB solar array to acquire more than 100 images from multiple positions. To minimize the number of SSRMS movements, the Special Purpose Dexterous Manipulator (SPDM) would be attached to the SSRMS. This would make it possible to park the SPDM in one position and acquire multiple images by changing the viewing orientation of the SPDM body cameras using the pan/tilt units on which the cameras are mounted. Using this implementation concept, ISAG identified four SSRMS/SPDM positions from which all of the needed imagery could be acquired. Based on a photogrammetric simulation, it was estimated that the location of the FGB solar array could be measured within an accuracy of about 1 in. in each axis relative to the ISS Analysis Coordinate System (ISSACS). In October 2011, a proposed image-acquisition plan was drafted by ISAG and released for review. The ISS Robotics flight control team (ROBO) proposed minor changes to SPDM positions 1 and 4 to meet ISS proximity requirements. The updated image acquisition plan and draft chit were presented to and approved by the Systems Working Group (SWG) November 18 and were sent to the Vehicle Configuration Board (VCB) in early December 2011. Working with ROBO on 3 successive days (February 21, 22, and 23), ISAG collected 161 images of the ISS. Approximately 40 images were collected from each of the four different SSRMS/SPDM positions, with each set mapping the region from the Node 3 end cone, across Node 1, along the forward port side portion of the FGB, and out the port side FGB solar arrays. From this imagery, the best 80 images were selected for use in the analysis. The images were radiometrically enhanced to improve color and contrast and loaded into the FotoG analysis software along with the camera parameters and control data, which consisted of the coordinates for 54 handrail attachment bolts on the aft face of Node 3, in the ISSACS coordinate system. The results of this analysis produced the measured coordinates of 116 points distributed across the face of the FGB solar array panels (see figure 3) along with propagated uncertainty estimates in each coordinate axis. These results were sent to the ISS Vehicle Configuration Office, which sent them to the Configuration Analysis Modeling and Mass Properties (CAMMP) team for comparison with the Russian-provided CAD model for the retracted FGB solar arrays. The CAMMP analysis unexpectedly showed that the measured location of the port FGB solar array was up to 41-in. further outboard than the design and was slightly twisted about its rotational axis. The unexpected comparison results produced some initial concern regarding the accuracy of the photogrammetric measurements. To verify the measured results, ISAG personnel conducted a second analysis using just the imagery of the solar arrays in an arbitrary coordinate system defined by the three corner points of the inboard-most panel, with the design distance between points A1 and A10 as the only scale. The new measurements agreed with the original results to within less than 1 in. RMS in each axis, confirming the original solar array measurements. ISAG produced a final report for the ISS Vehicle Configuration Office documenting an apparent anomaly in the retracted configuration of the port FGB solar arrays. A copy of the measurement report was translated and sent to the Russian Space Agency. During a Vehicle Integrated Performance and Resources (VIPeR) teleconference September 24, 2012, the Russians acknowledged receipt of a translated copy of the ISAG report. The Russian representative stated that the head of the solar array design team claimed that the measured configuration was impossible unless the structure was physically broken. The Russians acknowledged that they had no expertise in photogrammetry, so the analysis technique employed was a "black box" to them, and they did not know how to use the ISAG results. They asked for a single image in which the overextension of the port solar array could be obviously seen. On November 10, 2012, during a face-to-face meeting with their Russian counterparts at JSC, ISAG presented nadir-view imagery of the FGB acquired during Space Shuttle rendezvous. Using the known width of the pressurized portion of the FGB as a scale, this analysis clearly showed that the port FGB solar array was extended outboard further than the Russian design for the retracted solar array.

Liddle, Donn↗

Test aspects of the JPL Viterbi decoder

The generation of test vectors and design-for-test aspects of the Jet Propulsion Laboratory (JPL) Very Large Scale Integration (VLSI) Viterbi decoder chip is discussed. Each processor integrated circuit (IC) contains over 20,000 gates. To achieve a high degree of testability, a scan architecture is employed. The logic has been partitioned so that very few test vectors are required to test the entire chip. In addition, since several blocks of logic are replicated numerous times on this chip, test vectors need only be generated for each block, rather than for the entire circuit. These unique blocks of logic have been identified and test sets generated for them. The approach employed for testing was to use pseudo-exhaustive test vectors whenever feasible. That is, each cone of logid is tested exhaustively. Using this approach, no detailed logic design or fault model is required. All faults which modify the function of a block of combinational logic are detected, such as all irredundant single and multiple stuck-at faults.

Breuer, M. A.↗

Sequencing System Building Blocks: Using a Component Architecture for Sequencing Software

Over the last few years software engineering has made significant strides in making more flexible architectures and designs possible. However, at the same time, spacecraft have become more complex and flight software has become more sophisticated. Typically spacecraft are often one-of-a-kind entities that have different hardware designs, different capabilities, different instruments, etc. Ground software has become more complex and operations teams have had to learn a myriad of tools that all have different user interfaces and represent data in different ways. At Jet Propulsion Laboratory (JPL) these themes have collided to require a new approach to producing ground system software. Two different groups have been looking at tackling this particular problem. One group is working for the JPL Mars Technology Program in the Mars Science Laboratory (MSL) Focused Technology area. The other group is the JPL Multi-Mission Planning and Sequencing Group. The major concept driving these two approaches on a similar path is to provide software that can be a more cohesive flexible system that provides a set of planning and sequencing system of services. This paper describes the efforts that have been made to date to create a unified approach from these disparate groups.

multi mission planning↗

Sequence System Building Blocks: Using a Component Architecture for Sequencing Software

Over the last few years software engineering has made significant strides in making more flexible architectures and designs possible. However, at the same time, spacecraft have become more complex and flight software has become more sophisticated. Typically spacecraft are often one-of-a-kind entities that have different hardware designs, different capabilities, different instruments, etc. Ground software has become more complex and operations teams have had to learn a myriad of tools that all have different user interfaces and represent data in different ways. At Jet Propulsion Laboratory (JPL) these themes have collided to require an new approach to producing ground system software. Two different groups have been looking at tackling this particular problem. One group is working for the JPL Mars Technology Program in the Mars Science Laboratory (MSL) Focused Technology area. The other group is the JPL Multi-Mission Planning and Sequencing Group . The major concept driving these two approaches on a similar path is to provide software that can be a more cohesive flexible system that provides a act of planning and sequencing system of services. This paper describes the efforts that have been made to date to create a unified approach from these disparate groups.

flexible architectures↗

General-Purpose Data-Formatting Input/Output System

Multiplexable input/output (I/O) system developed as interface between host computer and real-time, fixed-base simulator cockpit. Unit designed to be general-purpose interface and operated through virtually any 8- or 16-bit, transistor/transistor-logic-level, parallel-I/O port with or without handshaking. Accepts byte-coded data in form of data blocks from host computer and routes data to various system I/O modules like discrete outputs, lamp drivers, and seven-segment-display drivers. Formats and routes data from input modules back to host computer. Other modules designed to drive alphanumeric displays and communications interfaces and to serve as analog-to-digital and digital-to-analog converter modules.

Busquets, Anthony M.↗