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Parallel lasers interact in shared space to alter output wavelength. New device consists of two stripe lasers in aluminum gallium arsenide chip. Parallel stripes close enough so light from lower laser coupled into upper laser and vice versa. Lasers operated by low-duty-cycle current pulses. Lasing threshold of each about 100 mA. Currents controlled independently. Useful in optical communications systems employing wavelength-division multiplexing.
Over the past two decades, fiber optics has emerged as a highly practical and cost-efficient communications technology. Its competitiveness vis-a-vis other transmission media, especially satellite, has become a critical question. This report studies the likely evolution and application of fiber optic networks in the United States to the end of the century. The outlook for the technology of fiber systems is assessed and forecast, scenarios of the evolution of fiber optic network development are constructed, and costs to provide service are determined and examined parametrically as a function of network size and traffic carried. Volume 1 consists of the Executive Summary. Volume 2 focuses on fiber optic technology and long distance fiber optic networks. Volume 3 develops a traffic and financial model of a nationwide long distance transmission network. Among the study's most important conclusions are: revenue requirements per circuit for LATA-to-LATA fiber optic links are less than one cent per call minute; multiplex equipment, which is likely to be required in any competing system, is the largest contributor to circuit costs; the potential capacity of fiber optic cable is very large and as yet undefined; and fiber optic transmission combined with other network optimization schemes can lead to even lower costs than those identified in this study.
The hardware and software characteristics of a time division multiplex system are described. The system is used to sample analog and digital data. The data is merged with synchronization information to produce a serial pulse coded modulation (PCM) bit stream. Information presented herein is required by users to design compatible interfaces and assure effective utilization of this encoder system. GSFC/Wallops Flight Facility has flown approximately 50 of these systems through 1984 on sounding rockets with no inflight failures. Aydin Vector manufactures all of the components for these systems.
Experience gained in operating infrared detector arrays for high sensitivity astronomical applications at the University of Rochester are summarized. Progress made in operating the 32 x 32 InSb array with bump-bonded Silicon CCD readout is described. Astronomical work done with the 32 x 32 camera is also described. Plans for the future, including improvements for the 32 x 32 camera system as well as implementing a new generation of 58 x 62 InSb array using switched-MOSFET direct readout multiplexing system in the place of the older CCD technology is discussed.
Hybrid silicon Infrared Charge Coupled Devices (IRCCDs) are evaluated for use as viable astronomical detectors. A Si:In photoconductor array which is bump-bonded to a silicon multiplexer is described. A summary of the device parameters is given.
The fabrication of antimony doped silicon (Si:Sb) detector arrays are described for use in 30 micron infrared imaging applications. The operation of the multiplexer readout circuit which will be used for this application is also described.
The NASA Lewis Research Center is in the process of installing a new data acquisition and display system. This new system will provide small and medium sized aeronautics test facilities with a state-of-the-art real-time data acquisition and display system. The new data system will provide for the acquisition of signals from a variety of instrumentation sources. They include analog measurements of temperatures, pressures, and other steady state voltage inputs; frequency inputs to measure speed and flow; discrete I/O for significant events, and modular instrument systems such as multiplexed pressure modules or electronic instrumentation with a IEEE 488 interface. The data system is designed to acquire data, convert it to engineering units, compute test dependent performance calculations, limit check selected channels or calculations, and display the information in alphanumeric or graphical form with a cycle time of one second for the alphanumeric data. This paper describes the system configuration, its salient features, and the expected impact on testing.
Preliminary resistojet design requirements were established based on initial technical requirements imposed by the results of NASA and Rocketdyne studies. The requirements are directed toward long life, simplicity, flexibility, and commonality with other space station components. The resistojet assembly is comprised of eight resistojets, fluid components downstream of the waste fluid storage system, a power controller, structure, and shielding. It consists of two identical subassemblies, one of which is redundant. Each subassembly consists of four 500-W resistojets, series redundant latch values, a power controller, a water vaporizer, two pressure regulators, filters, check valves, disconnects, fluid tubing, and electrical cables. All components are packaged at the end of the stinger aft of the JEM and Columbus modules. Different flow and power control methods were studied. A constant inlet pressure and a two-power setting controller were tentatively selected based on simplicity and reasonably high specific impulse for the range of waste gas compositions that are anticipated. The constant pressure is supplied by pressure regulators. The two set point power control includes individual power supplies to each resistojet heater and water vaporizer. An embedded data processor, a multiplexer-demultiplexer, and a network interface unit that are standard space station components are included in the power controller. The total dry weight of the resistojet assembly is approximately 172 lb. The total cost for design, development, test, evaluation, qualification, and flight hardware is estimated to be $16 million.
The technical feasibility and economic viability of satellite system architectures that are suitable for customer premise service (CPS) communications are investigated. System evaluation is performed at 30/20 GHz (Ka-band); however, the system architectures examined are equally applicable to 14/11 GHz (Ku-band). Emphasis is placed on systems that permit low-cost user terminals. Frequency division multiple access (FDMA) is used on the uplink, with typically 10,000 simultaneous accesses per satellite, each of 64 kbps. Bulk demodulators onboard the satellite, in combination with a baseband multiplexer, convert the many narrowband uplink signals into a small number of wideband data streams for downlink transmission. Single-hop network interconnectivity is accomplished via downlink scanning beams. Each satellite is estimated to weigh 5600 lb and consume 6850W of power; the corresponding payload totals are 1000 lb and 5000 W. Nonrecurring satellite cost is estimated at $110 million, with the first-unit cost at $113 million. In large quantities, the user terminal cost estimate is $25,000. For an assumed traffic profile, the required system revenue has been computed as a function of the internal rate of return (IRR) on invested capital. The equivalent user charge per-minute of 64-kbps channel service has also been determined.
The technical feasibility and economic viability of satellite system architectures that are suitable for Customer Premise Service (CPS) communications is investigated. System evaluation is performed at 30/20 GHz (Ka-band); however, the system architectures examined are equally applicable to 14/11 GHz (Ku-band). Emphasis is placed on system that permit low cost user terminals. Frequency Division Multiple Access (FDMA) is used on the uplink, with typically 10,000 simultaneous accesses per satellite, each of 64 kbps. Bulk demodulators onboard the satellite, in combination with a baseband multiplexer, convert the many narrowband uplink signals into a small number of wideband data streams for downlink transmission. Single hop network interconnectivity is accomplished through use of downlink scanning beams. Each satellite is estimated to weigh 5600 lb and consume 6850W of power; the corresponding payload totals are 1000 lb and 5000W. Nonrecurring satellite cost is estimated at $110 million, with the first unit cost at $113 million. In large quantities, the user terminal cost estimate is $25,000.
The status of development and characterization tests of integrated infrared detector array technology for astronomy applications is described. The devices under development include intrinsic, extrinsic silicon, and extrinsic germanium detectors, with hybrid silicon multiplexers. Laboratory test results and successful astronomy imagery have established the usefulness of integrated arrays in low-background astronomy applications.
For satellites to remain a vital part of future national and international communications, system concepts that use their inherent advantages to the fullest must be created. Network architectures that take maximum advantage of satellites equipped with onboard processing are explored. Satellite generations must accommodate various services for which satellites constitute the preferred vehicle of delivery. Such services tend to be those that are widely dispersed and present thin to medium loads to the system. Typical systems considered are thin and medium route telephony, maritime, land and aeronautical radio, VSAT data, low bit rate video teleconferencing, and high bit rate broadcast of high definition video. Delivery of services by TDMA and FDMA multiplexing techniques and combinations of the two for individual and mixed service types are studied. The possibilities offered by onboard circuit switched and packet switched architectures are examined and the results strongly support a preference for the latter. A detailed design architecture encompassing the onboard packet switch and its control, the related demand assigned TDMA burst structures, and destination packet protocols for routing traffic are presented. Fundamental onboard hardware requirements comprising speed, memory size, chip count, and power are estimated. The study concludes with identification of key enabling technologies and identifies a plan to develop a POC model.
Two solid-state sensors for use in remote sensing instruments operating in the pushbroom mode are examined. The design and characteristics of the visible/near-infrared (VIS/NIR) device and the short-wavelength infrared (SWIR) device are described. The VIS/NIR is a CCD imager with four parallel sensor lines, each 1024 pixel long; the chip design and filter system of the VIS/NIR are studied. The performance of the VIS/NIR sensor with mask and its system performance are measured. The SWIR is a dual-band line imager consisting of palladium silicide Schottky-barrier detectors coupled to CCD multiplexers; the performance of the device is analyzed. The substrate materials and layout designs used to assemble the 4 x 5120-element VIS/NIR array and the 2 x 2560-element SWIR array are discussed, and the planarity of the butted arrays are verified using a profilometer. The optical and electrical characteristics, and the placement and butting accuracy of the arrays are evaluated. It is noted that the arrays met or exceed their expected performance.
Attention is given to the component design and optical configuration features of a generic optical linear algebra processor (OLAP) architecture, as well as the large number of OLAP architectures, number representations, algorithms and applications encountered in current literature. Number-representation issues associated with bipolar and complex-valued data representations, high-accuracy (including floating point) performance, and the base or radix to be employed, are discussed, together with case studies on a space-integrating frequency-multiplexed architecture and a hybrid space-integrating and time-integrating multichannel architecture.
Short and medium IR wavelength 64 x 64 hybrid focal plane arrays (FPAs) have been developed using sapphire-grown HgCdTe. The short wavelength arrays were developed for a prototype airborne imaging spectrometer, while those of medium wavelength are suitable for tactical missile seekers and strategic surveillance systems. Attention is presently given to results obtained for these FPAs' current-voltage characteristics, as well as for their characterization at different temperatures. The detector arrays were also mated to a multiplexer and characterized under different operating conditions. The unit cell size used is 52 x 52 microns.
The technologies for optimized, i.e., state of the art, operation of satellite-based communications systems are surveyed. Features of spaceborne active repeater systems, low-noise signal amplifiers, power amplifiers, and high frequency switches are described. Design features and capabilities of various satellite antenna systems are discussed, including multiple beam, shaped reflector shaped beam, offset reflector multiple beam, and mm-wave and laser antenna systems. Attitude control systems used with the antenna systems are explored, along with multiplexers, filters, and power generation, conditioning and amplification systems. The operational significance and techniques for exploiting channel bandwidth, baseband and modulation technologies are described. Finally, interconnectivity among communications satellites by means of RF and laser links is examined, as are the roles to be played by the Space Station and future large space antenna systems.
The development and evaluation of an integrated array of antimony-doped silicon detectors is described. The spectral range of extrinsic silicon-integrated arrays useful for low-background IR astronomical applications is extended to about 31 microns with this development. The 58 x 62-element array is accessed by a direct readout multiplexer. The device is evaluated with a flexible microcomputer-based drive and readout electronics system in a low-background test dewar. Acceptance testing indicates single-pixel NEPs in the mid-10 to the -18th W/sq rt Hz range, and good global uniformity statistics.
The design for a 1-GHz digital integrated circuit tester for the evaluation of custom GaAs chips and subsystems is discussed. Technology-related problems affecting the design of a GaAs computer are discussed, with emphasis on the problems introduced by long printed-circuit-board interconnect. High-speed interface modules provide a link between the low-speed microprocessor and the chip under test. Memory-multiplexer and memory-shift register architectures for the storage of test vectors are described in addition to an architecture for local data storage consisting of a long chain of GaAs shift registers. The tester is constructed around a VME system card cage and backplane, and very little high-speed interconnect exists between boards. The tester has a three part self-test consisting of a CPU board confidence test, a main memory confidence test, and a high-speed interface module functional test.