Analysis of the modified integrate and dump decision device
Modified integrate and dump detector using FM click mechanism for improving bit decision and reducing error rates in FSK system
Hayre, H. S.↗
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Results for “bit error”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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MIDAS - A microcomputer-based image display and analysis system with full Landsat frame processing capabilities
Image Display and Analysis Systems (MIDAS) developed at NASA/Ames for the analysis of Landsat MSS images is described. The MIDAS computer power and memory, graphics, resource-sharing, expansion and upgrade, environment and maintenance, and software/user-interface requirements are outlined; the implementation hardware (including 32-bit microprocessor, 512K error-correcting RAM, 70 or 140-Mbyte formatted disk drive, 512 x 512 x 24 color frame buffer, and local-area-network transceiver) and applications software (ELAS, CIE, and P-EDITOR) are characterized; and implementation problems, performance data, and costs are examined. Planned improvements in MIDAS hardware and design goals and areas of exploration for MIDAS software are discussed.
Hofman, L. B.↗
A new method for frame synchronization
A frame synchronization method based on an examination of the shortest bit length containing all error bursts is introduced. It is shown that the new method is more reliable and efficient than the commonly used one based on counting the number of errors for the convolutionally coded channel.
Shahshahani, M.↗
Output data formatter for the Electronically Scanned Thinned Array Radiometer (ESTAR) instrument
A prototype Output Data Formatter (ODF) for the ESTAR (Electronically Scanned Thinned Array Radiometer) instrument has been designed and tested. It employs programmable logic devices to format and tag correlator data for transmission to Earth. After accepting 170 bits or correlator and error data in parallel, it appends an identification word and then serially passes the data to the Small Explorer Data System (SEDS) for transmission at a maximum rate of greater than 15 Mb/sec. Implemented with two reprogrammable field programmable gate arrays (FPGA's), each contained in a 132-pin plastic pin grid array (PGA) package, the design is cascadeable, fully testable, and low-power.
Chren, William A., Jr.↗
Modulation and synchronization technique for MF-TDMA system
This report addresses modulation and synchronization techniques for a multi-frequency time division multiple access (MF-TDMA) system with onboard baseband processing. The types of synchronization techniques analyzed are asynchronous (conventional) TDMA, preambleless asynchronous TDMA, bit synchronous timing with a preamble, and preambleless bit synchronous timing. Among these alternatives, preambleless bit synchronous timing simplifies onboard multicarrier demultiplexer/demodulator designs (about 2:1 reduction in mass and power), requires smaller onboard buffers (10:1 to approximately 3:1 reduction in size), and provides better frame efficiency as well as lower onboard processing delay. Analysis and computer simulation illustrate that this technique can support a bit rate of up to 10 Mbit/s (or higher) with proper selection of design parameters. High bit rate transmission may require Doppler compensation and multiple phase error measurements. The recommended modulation technique for bit synchronous timing is coherent QPSK with differential encoding for the uplink and coherent QPSK for the downlink.
Faris, Faris↗
Self-Checking Memory Interface
Memory-interface integrated circuit not only detects errors in data from other circuits but also detects errors within itself. Memory-interface chip encodes 16-bit words with Hamming code for single-error correction or double-error detection. Chip used in fault-tolerant computers under development by NASA.
Sievers, M. W.↗
Symbol synchronization for the TDRSS decoder
Each 8 bits out of the Viterbi decoder correspond to one symbol of the R/S code. Synchronization must be maintained here so that each 8-bit symbol delivered to the R/S decoder corresponds to an 8-bit symbol from the R/S encoder. Lack of synchronization, would cause an error in almost every R/S symbol since even a - 1-bit sync slip shifts every bit in each 8-bit symbol by one position, therby confusing the mapping betweeen 8-bit sequences and symbols. The error correcting capability of the R/S code would be exceeded. Possible ways to correcting this condition include: (1) designing the R/S decoder to recognize the overload and shifting the output sequence of the inner decoder to establish a different sync state; (2) using the characteristics of the inner decoder to establish symbol synchronization for the outer code, with or without a deinterleaver and an interleaver; and (3) modifying the encoder to alternate periodically between two sets of generators.
Costello, D. J., Jr.↗
DSN telemetry system performance with convolutionally coded data: Maximum likelihood decoding
DSN telemetry system performance is analyzed based on convolutionally coded data for the short constraint length 7:1/2 codes at low bit rates, 8 to 2,048 bits per second, obtained from CTA 21 for the S-band configuration. The results indicate that a loss of one or more decibels in the system performance may be expected due to system degradation. Also, burst error lengths up to 100 bits may not be unusual in actual operational situations.
Benjauthrit, B.↗
SZ3: A Modular Framework for Composing Prediction-Based Error-Bounded Lossy Compressors
Today's scientific simulations require a significant reduction of data volume because of extremely large amounts of data they produce and the limited I/O bandwidth and storage space. Here, error-bounded lossy compression has been considered one of the most effective solutions to the above problem. In practice, however, the best-fit compression method often needs to be customized or optimized in particular because of diverse characteristics in different datasets and various user requirements on the compression quality and performance. In this paper, we address this issue with a novel modular, composable compression framework named SZ3. Our contributions are four-folds. (1) We develop SZ3 which features an innovative modular abstraction for the prediction-based compression framework, such that compression modules can be plugged in easily to create new compressors based on characteristics of data and user requirements. (2) We create a new compression pipeline by SZ3 for GAMESS data, which significantly improves the compression ratios over state-of-the-art compressors. (3) We develop an adaptive compression pipeline by SZ3 for APS data with minimal efforts, which leads to the best rate-distortion among all existing error-bounded lossy compressors for any bit-rate. (4) We compare the sustainability of SZ3 with leading error-bounded prediction-based compressors, and then demonstrate the necessity of diverse pipelines by integrating and evaluating several compression pipelines on diverse scientific datasets from multiple disciplines. Experiments show that SZ3 incurs very limited overhead in compressor integration and our customized compression pipelines lead to up to 20% improvement in compression ratios under the same data distortion, when compared with the best existing approach.
97 MATHEMATICS AND COMPUTING↗
Synchronization Technique For Reception Of Coded Data
Shortest sequence of bits likely to be filled with error bursts examined. Algorithm improves synchronization of frames of noisy binary-coded data signals after Viterbi decoding (recovery from "inner" convolutional code used in transmission channel) and before Reed-Solomon or other decoding (recovery from "outer" error-correcting block code). Based on comparisons of sequences of correct and erroneous Viterbi-decoded received bits with known marker sequence denoting beginning of frame of data. Does not require count of number of bits in received sequence disagreeing with corresponding bits in marker sequence.
Shahshahani, Mehrdad M.↗
Performance of a finite phase state bit-synchronization loop with and without sequential filters
A discrete phase state bit-synchronization loop is proposed for synchronization and detection of a binary nonreturn-to-zero (NRZ) process. The general loop model is developed for 11 and 17 phase states with optional sequential loop filter. Loop performance is considered in terms of the phase error density function, rms phase error, and mean time to bit slippage. It is shown that satisfactory loop performance can be achieved at -3 dB SNR through use of sequential loop filters.
Ransom, J. J.↗
Effects of Heavy Ion Exposure on Nanocrystal Nonvolatile Memory
We have irradiated engineering samples of Freescale 4M nonvolatile memories with heavy ions. They use Silicon nanocrystals as the storage element, rather than the more common floating gate. The irradiations were performed using the Texas A&M University cyclotron Single Event Effects Test Facility. The chips were tested in the static mode, and in the dynamic read mode, dynamic write (program) mode, and dynamic erase mode. All the errors observed appeared to be due to single, isolated bits, even in the program and erase modes. These errors appeared to be related to the micro-dose mechanism. All the errors corresponded to the loss of electrons from a programmed cell. The underlying physical mechanisms will be discussed in more detail later. There were no errors, which could be attributed to malfunctions of the control circuits. At the highest LET used in the test (85 MeV/mg/sq cm), however, there appeared to be a failure due to gate rupture. Failure analysis is being conducted to confirm this conclusion. There was no unambiguous evidence of latchup under any test conditions. Generally, the results on the nanocrystal technology compare favorably with results on currently available commercial floating gate technology, indicating that the technology is promising for future space applications, both civilian and military.
Oldham, Timothy R.↗
The dependence of single event upset on proton energy /15-590 MeV/
Low earth orbit satellite and Jupiter orbiter probe semiconductor devices may incur soft errors or single event upsets, manifested as bit flips, during exposure to such nuclear particles or heavy ions as trapped protons with energies ranging up to 1000 MeV. Experimental data is given on the average proton fluence needed to cause a bit flip as a function of proton energy for isoplanar bipolar TTL RAMs. Error dependence data shape and threshold energy can be related to the existing body of theoretical data on energy deposition following proton nuclear reactions. Experimental data also show that the relative cross sectional amplitude for functionally identical devices can be related to the device's power consumption.
Nichols, D. K.↗
Universal Decoder for PPM of any Order
A recently developed algorithm for demodulation and decoding of a pulse-position- modulation (PPM) signal is suitable as a basis for designing a single hardware decoding apparatus to be capable of handling any PPM order. Hence, this algorithm offers advantages of greater flexibility and lower cost, in comparison with prior such algorithms, which necessitate the use of a distinct hardware implementation for each PPM order. In addition, in comparison with the prior algorithms, the present algorithm entails less complexity in decoding at large orders. An unavoidably lengthy presentation of background information, including definitions of terms, is prerequisite to a meaningful summary of this development. As an aid to understanding, the figure illustrates the relevant processes of coding, modulation, propagation, demodulation, and decoding. An M-ary PPM signal has M time slots per symbol period. A pulse (signifying 1) is transmitted during one of the time slots; no pulse (signifying 0) is transmitted during the other time slots. The information intended to be conveyed from the transmitting end to the receiving end of a radio or optical communication channel is a K-bit vector u. This vector is encoded by an (N,K) binary error-correcting code, producing an N-bit vector a. In turn, the vector a is subdivided into blocks of m = log2(M) bits and each such block is mapped to an M-ary PPM symbol. The resultant coding/modulation scheme can be regarded as equivalent to a nonlinear binary code. The binary vector of PPM symbols, x is transmitted over a Poisson channel, such that there is obtained, at the receiver, a Poisson-distributed photon count characterized by a mean background count nb during no-pulse time slots and a mean signal-plus-background count of ns+nb during a pulse time slot. In the receiver, demodulation of the signal is effected in an iterative soft decoding process that involves consideration of relationships among photon counts and conditional likelihoods of m-bit vectors of coded bits. Inasmuch as the likelihoods of all the m-bit vectors of coded bits mapping to the same PPM symbol are correlated, the best performance is obtained when the joint mbit conditional likelihoods are utilized. Unfortunately, the complexity of decoding, measured in the number of operations per bit, grows exponentially with m, and can thus become prohibitively expensive for large PPM orders. For a system required to handle multiple PPM orders, the cost is even higher because it is necessary to have separate decoding hardware for each order. This concludes the prerequisite background information. In the present algorithm, the decoding process as described above is modified by, among other things, introduction of an lbit marginalizer sub-algorithm. The term "l-bit marginalizer" signifies that instead of m-bit conditional likelihoods, the decoder computes l-bit conditional likelihoods, where l is fixed. Fixing l, regardless of the value of m, makes it possible to use a single hardware implementation for any PPM order. One could minimize the decoding complexity and obtain an especially simple design by fixing l at 1, but this would entail some loss of performance. An intermediate solution is to fix l at some value, greater than 1, that may be less than or greater than m. This solution makes it possible to obtain the desired flexibility to handle any PPM order while compromising between complexity and loss of performance.
Moision, Bruce E.↗
Improved Speech Coding Based on Open-Loop Parameter Estimation
A nonlinear optimization algorithm for linear predictive speech coding was developed early that not only optimizes the linear model coefficients for the open loop predictor, but does the optimization including the effects of quantization of the transmitted residual. It also simultaneously optimizes the quantization levels used for each speech segment. In this paper, we present an improved method for initialization of this nonlinear algorithm, and demonstrate substantial improvements in performance. In addition, the new procedure produces monotonically improving speech quality with increasing numbers of bits used in the transmitted error residual. Examples of speech encoding and decoding are given for 8 speech segments and signal to noise levels as high as 47 dB are produced. As in typical linear predictive coding, the optimization is done on the open loop speech analysis model. Here we demonstrate that minimizing the error of the closed loop speech reconstruction, instead of the simpler open loop optimization, is likely to produce negligible improvement in speech quality. The examples suggest that the algorithm here is close to giving the best performance obtainable from a linear model, for the chosen order with the chosen number of bits for the codebook.
Juang, Jer-Nan↗
Least reliable bits coding (LRBC) for high data rate satellite communications
LRBC, a bandwidth efficient multilevel/multistage block-coded modulation technique, is analyzed. LRBC uses simple multilevel component codes that provide increased error protection on increasingly unreliable modulated bits in order to maintain an overall high code rate that increases spectral efficiency. Soft-decision multistage decoding is used to make decisions on unprotected bits through corrections made on more protected bits. Analytical expressions and tight performance bounds are used to show that LRBC can achieve increased spectral efficiency and maintain equivalent or better power efficiency compared to that of BPSK. The relative simplicity of Galois field algebra vs the Viterbi algorithm and the availability of high-speed commercial VLSI for block codes indicates that LRBC using block codes is a desirable method for high data rate implementations.
Vanderaar, Mark↗
Let Each Quantum Bit Choose Its Basis Gates
Near-term quantum computers are primarily limited by errors in quantum operations (or gates) between two quantum bits (or qubits). A physical machine typically provides a set of basis gates that include primitive 2-qubit (2Q) and 1-qubit (1Q) gates that can be implemented in a given technology. 2Q entangling gates, coupled with some 1Q gates, allow for universal quantum computation. In superconducting technologies, the current state of the art is to implement the same 2Q gate between every pair of qubits (typically an XX-or XY-type gate). This strict hardware uniformity requirement for 2Q gates in a large quantum computer has made scaling up a time and resource-intensive endeavor in the lab. We propose a radical idea – allow the 2Q basis gate(s) to differ between every pair of qubits, selecting the best entangling gates that can be calibrated between given pairs of qubits. This work aims to give quantum scientists the ability to run meaningful algorithms with qubit systems that are not perfectly uniform. Scientists will also be able to use a much broader variety of novel 2Q gates for quantum computing. We develop a theoretical framework for identifying good 2Q basis gates on “nonstandard” Cartan trajectories that deviate from “standard” trajectories like XX. We then introduce practical methods for calibration and compilation with nonstandard 2Q gates, and discuss possible ways to improve the compilation. To demonstrate our methods in a case study, we simulated both standard XY-type trajectories and faster, nonstandard trajectories using an entangling gate architecture with far-detuned transmon qubits. We identify efficient 2Q basis gates on these nonstandard trajectories and use them to compile a number of standard benchmark circuits such as QFT and QAOA. Furthermore, our results demonstrate an 8x improvement over the baseline 2Q gates with respect to speed and coherence-limited gate fidelity.
quantum computing↗
System and methods for hardware-software cooperative pipeline error detection
An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.
97 MATHEMATICS AND COMPUTING↗