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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 667 records · Page 37
All sourcesNASA NTRSDOE OSTI
DOE OSTI2014

Contact resistance improvement using interfacial silver nanoparticles in amorphous indium-zinc-oxide thin film transistors

We describe an approach to reduce the contact resistance at compositional conducting/semiconducting indium-zinc-oxide (IZO) homojunctions used for contacts in thin film transistors (TFTs). By introducing silver nanoparticles (Ag NPs) at the homojunction interface between the conducting IZO electrodes and the amorphous IZO channel, we reduce the specific contact resistance, obtained by transmission line model measurements, down to ∼10{sup −2 }Ω cm{sup 2}, ∼3 orders of magnitude lower than either NP-free homojunction contacts or solid Ag metal contacts. The resulting back-gated TFTs with Ag NP contacts exhibit good field effect mobility of ∼27 cm{sup 2}/V s and an on/off ratio >10{sup 7}. We attribute the improved contact resistance to electric field concentration by the Ag NPs.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Scaling behavior of hysteresis in multilayer MoS{sub 2} field effect transistors

Extrinsic hysteresis effects are often observed in MoS{sub 2} field effect devices due to adsorption of gas molecules on the surface of MoS{sub 2} channel. Scaling is a common method used in ferroics to quantitatively study the hysteresis. Here, the scaling behavior of hysteresis in multilayer MoS{sub 2} field effect transistors with a back-gated configuration was investigated. The power-law scaling relations were obtained for hysteresis area (〈A〉) and memory window (ΔV) with varying the region of back-gate voltage (V{sub bg,max}). It is interesting to find that the transition voltage in the forward sweep (V{sub FW}) and in the backward sweep (V{sub BW}) shifted to the opposite directions of back-gate voltage (V{sub bg}) with increasing V{sub bg,max}. However, when decreasing V{sub bg,max}, V{sub FW} shifted to positive and reversibly recovered, but V{sub BW} almost kept unchanged. The evolution of 〈A〉, ΔV, V{sub FW,} and V{sub BW} with V{sub bg,max} were discussed by the electrons transferring process between the adsorbate and MoS{sub 2} channel.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

High performance unipolar inverters by utilizing organic field-effect transistors with ultraviolet/ozone treated polystyrene dielectric

High performance unipolar inverters based on a significant variation of threshold voltage (V{sub th}) of organic field-effect transistors (OFETs), which was realized by introducing UV/ozone (UVO) treatment to polystyrene (PS) dielectric, were fabricated. A controllable V{sub th} shift of more than 10 V was obtained in the OFETs by adjusting the UVO treating time, and the unipolar inverters exhibited inverting voltage near 1/2 driving voltage and a noise margin of more than 70% of ideal value. From the analysis of scanning electron microscopy, atom force microscopy, and X-ray photoelectron spectroscopy, the dramatic controllable V{sub th} of OFETs, which played a key role in high performance unipolar inverters, was attributed to the newly generated oxygen functional groups in the PS dielectric induced by UVO treatment.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Rapid low-temperature processing of metal-oxide thin film transistors with combined far ultraviolet and thermal annealing

We propose a combined far ultraviolet (FUV) and thermal annealing method of metal-nitrate-based precursor solutions that allows efficient conversion of the precursor to metal-oxide semiconductor (indium zinc oxide, IZO, and indium oxide, In{sub 2}O{sub 3}) both at low-temperature and in short processing time. The combined annealing method enables a reduction of more than 100 °C in annealing temperature when compared to thermally annealed reference thin-film transistor (TFT) devices of similar performance. Amorphous IZO films annealed at 250 °C with FUV for 5 min yield enhancement-mode TFTs with saturation mobility of ∼1 cm{sup 2}/(V·s). Amorphous In{sub 2}O{sub 3} films annealed for 15 min with FUV at temperatures of 180 °C and 200 °C yield TFTs with low-hysteresis and saturation mobility of 3.2 cm{sup 2}/(V·s) and 7.5 cm{sup 2}/(V·s), respectively. The precursor condensation process is clarified with x-ray photoelectron spectroscopy measurements. Introducing the FUV irradiation at 160 nm expedites the condensation process via in situ hydroxyl radical generation that results in the rapid formation of a continuous metal-oxygen-metal structure in the film. The results of this paper are relevant in order to upscale printed electronics fabrication to production-scale roll-to-roll environments.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Microscopic origin of low frequency noise in MoS{sub 2} field-effect transistors

We report measurement of low frequency 1/f noise in molybdenum di-sulphide (MoS{sub 2}) field-effect transistors in multiple device configurations including MoS{sub 2} on silicon dioxide as well as MoS{sub 2}-hexagonal boron nitride (hBN) heterostructures. All as-fabricated devices show similar magnitude of noise with number fluctuation as the dominant mechanism at high temperatures and density, although the calculated density of traps is two orders of magnitude higher than that at the SiO{sub 2} interface. Measurements on the heterostructure devices with vacuum annealing and dual gated configuration reveals that along with the channel, metal-MoS{sub 2} contacts also play a significant role in determining noise magnitude in these devices.

36 MATERIALS SCIENCE↗
DOE OSTI2014

Semianalytical quantum model for graphene field-effect transistors

We develop a semianalytical model for monolayer graphene field-effect transistors in the ballistic limit. Two types of devices are considered: in the first device, the source and drain regions are doped by charge transfer with Schottky contacts, while, in the second device, the source and drain regions are doped electrostatically by a back gate. The model captures two important effects that influence the operation of both devices: (i) the finite density of states in the source and drain regions, which limits the number of states available for transport and can be responsible for negative output differential resistance effects, and (ii) quantum tunneling across the potential steps at the source-channel and drain-channel interfaces. By comparison with a self-consistent non-equilibrium Green's function solver, we show that our model provides very accurate results for both types of devices, in the bias region of quasi-saturation as well as in that of negative differential resistance.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2014

Au-gated SrTiO{sub 3} field-effect transistors with large electron concentration and current modulation

We report the fabrication of low-leakage rectifying Pt and Au Schottky diodes and Au-gated metal-semiconductor field effect transistors (MESFETs) on n-type SrTiO{sub 3} thin films grown by hybrid molecular beam epitaxy. In agreement with previous studies, we find that compared to Pt, Au provides a higher Schottky barrier height with SrTiO{sub 3}. As a result of the large dielectric constant of SrTiO{sub 3} and the large Schottky barrier height of Au, the Au-gated MESFETs are able to modulate ∼1.6 × 10{sup 14 }cm{sup −2} electron density, the highest modulation yet achieved using metal gates in any material system. These MESFETs modulate current densities up to ∼68 mA/mm, ∼20× times larger than the best demonstrated SrTiO{sub 3} MESFETs. We also discuss the roles of the interfacial layer, and the field-dependent dielectric constant of SrTiO{sub 3} in increasing the pinch off voltage of the MESFET.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Low-temperature study of array of dopant atoms on transport behaviors in silicon junctionless nanowire transistor

We demonstrate temperature-dependent quantum transport characteristics in silicon junctionless nanowire transistor fabricated on Silicon-on-Insulator substrate by the femtosecond laser lithography. Clear drain-current oscillations originated from dopant-induced quantum dots are observed in the initial stage of the conduction for the silicon nanowire channel at low temperatures. Arrhenius plot of the conductance indicates the transition temperature of 30 K from variable-range hopping to nearest-neighbor hopping, which can be well explained under Mott formalism. The transition of electron hopping behavior is the interplay result between the thermal activation and the Coulomb interaction.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2014

Effect of tunneling layers on the performances of floating-gate based organic thin-film transistor nonvolatile memories

Two types of floating-gate based organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) were demonstrated, with poly(methyl methacrylate co glycidyl methacrylate) (P(MMA-GMA)) and tetratetracontane (TTC) as the tunneling layer, respectively. Their device performances were measured and compared. In the memory with a P(MMA-GMA) tunneling layer, typical unipolar hole transport was obtained with a relatively small mobility of 0.16 cm{sup 2}/V s. The unidirectional shift of turn-on voltage (V{sub on}) due to only holes trapped/detrapped in/from the floating gate resulted in a small memory window of 12.5 V at programming/erasing voltages (V{sub P}/V{sub E}) of ±100 V and a nonzero reading voltage. Benefited from the well-ordered molecule orientation and the trap-free surface of TTC layer, a considerably high hole mobility of 1.7 cm{sup 2}/V s and a visible feature of electrons accumulated in channel and trapped in floating-gate were achieved in the memory with a TTC tunneling layer. High hole mobility resulted in a high on current and a large memory on/off ratio of 600 at the V{sub P}/V{sub E} of ±100 V. Both holes and electrons were injected into floating-gate and overwritten each other, which resulted in a bidirectional V{sub on} shift. As a result, an enlarged memory window of 28.6 V at the V{sub P}/V{sub E} of ±100 V and a zero reading voltage were achieved. Based on our results, a strategy is proposed to optimize FG-OTFT-NVMs by choosing a right tunneling layer to improve the majority carrier mobility and realize ambipolar carriers injecting and trapping in the floating-gate.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

On the origin of the two-dimensional electron gas at AlGaN/GaN heterojunctions and its influence on recessed-gate metal-insulator-semiconductor high electron mobility transistors

It is commonly accepted that interface states at the passivation surface of AlGaN/GaN heterostructures play an important role in the formation of the 2DEG density. Several interface state models are cited throughout literature, some with discrete levels, others with different kinds of distributions, or a combination of both. The purpose of this article is to compare the existing interface state models with both direct and indirect measurements of these interface states from literature (e.g., through the hysteresis of transfer characteristics of Metal-Insulator-Semiconductor High Electron Mobility Transistors (MISHEMTs) employing such an interface in the gate region) and Technology Computer Aided Design (TCAD) simulations of 2DEG densities as a function of the AlGaN thickness. The discrepancies between those measurements and TCAD simulations (also those commonly found in literature) are discussed. Then, an alternative model inspired by the Disorder Induced Gap State model for compound semiconductors is proposed. It is shown that defining a deep border trap inside the insulator can solve these discrepancies and that this alternative model can explain the origin of the two dimensional electron gas in combination with a high-quality interface that, by definition, has a low interface state density.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Examination of the ambient effects on the stability of amorphous indium-gallium-zinc oxide thin film transistors using a laser-glass-sealing technology

The effect of an ambient atmosphere with a positive bias constant current stress (CCS) and a negative bias illumination stress (NBIS) on the stability of amorphous In-Ga-Zn-O thin film transistors (TFTs) is examined by utilizing a glass-hermetic-sealant with a moisture permeability of less than 10{sup −6} g/m{sup 2} · day. In the CCS test, the threshold voltage shift (ΔV{sub th}) was remarkably suppressed in the glass-sealed TFTs. The unsealed and resin-sealed TFTs exhibited large ΔV{sub th} values. During the NBIS tests, the glass-sealed TFTs had almost the same negative ΔV{sub th} as the unsealed and resin sealed TFTs. Among the different TFTs, no significant differences were observed in the threshold voltage, the subthreshold swing and the saturation mobility as a function of the photon energy. It is concluded that ambient molecules were the primary origin of the instability of the ΔV{sub th}, induced by a CCS, but they were not related to the NBIS instability. The major role of the effective passivation layers in the NBIS test was not to simply block out the ambient effects, but to reduce the extra density of states at/near the surface of the back channel.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Combustion-process derived comparable performances of Zn-(In:Sn)-O thin-film transistors with a complete miscibility

Amorphous zinc-indium-tin oxide (a-ZITO) thin-film transistors (TFTs) have been prepared using a low-temperature combustion process, with an emphasis on complete miscibility of In and Sn contents. The a-ZITO TFTs were comparatively studied in detail, especially for the working stability. The a-ZITO TFTs all exhibited acceptable and excellent behaviors from Sn-free TFTs to In-free TFTs. The obtained a-ZTO TFTs presented a field-effect mobility of 1.20 cm{sup 2} V{sup −1} s{sup −1}, an on/off current ratio of 4.89 × 10{sup 6}, and a long-term stability under positive bias stress, which are comparable with those of the a-ZIO TFTs. The In-free a-ZTO TFTs are very potential for electrical applications with a low cost.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks

This work investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors (n-MOSFETs) with high-k/metal gate stacks. Many groups have proposed new models (i.e., single-particle and multiple-particle process) to well explain the hot carrier degradation in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO{sub 2} interface. However, for high-k dielectric devices, experiment results show that the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Manipulation of transport hysteresis on graphene field effect transistors with Ga ion irradiation

We have studied the effect of Ga ion irradiation on the controllable hysteretic behavior of graphene field effect transistors fabricated on Si/SO{sub 2} substrates. The various densities of defects in graphene were monitored by Raman spectrum. It was found that the Dirac point shifted to the positive gate voltage constantly, while the hysteretic behavior was enhanced first and then weakened, with the dose of ion irradiation increasing. By contrasting the trap charges density induced by dopant and the total density of effective trap charges, it demonstrated that adsorbate doping was not the decisive factor that induced the hysteretic behavior. The tunneling between the defect sites induced by ion irradiation was also an important cause for the hysteresis.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

High temperature study of flexible silicon-on-insulator fin field-effect transistors

We report high temperature electrical transport characteristics of a flexible version of the semiconductor industry's most advanced architecture: fin field-effect transistor on silicon-on-insulator with sub-20 nm fins and high-κ/metal gate stacks. Characterization from room to high temperature (150 °C) was completed to determine temperature dependence of drain current (I{sub ds}), gate leakage current (I{sub gs}), transconductance (g{sub m}), and extracted low-field mobility (μ{sub 0}). Mobility degradation with temperature is mainly caused by phonon scattering. The other device characteristics show insignificant difference at high temperature which proves the suitability of inorganic flexible electronics with advanced device architecture.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Influence of an anomalous dimension effect on thermal instability in amorphous-InGaZnO thin-film transistors

This paper investigates abnormal dimension-dependent thermal instability in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors. Device dimension should theoretically have no effects on threshold voltage, except for in short channel devices. Unlike short channel drain-induced source barrier lowering effect, threshold voltage increases with increasing drain voltage. Furthermore, for devices with either a relatively large channel width or a short channel length, the output drain current decreases instead of saturating with an increase in drain voltage. Moreover, the wider the channel and the shorter the channel length, the larger the threshold voltage and output on-state current degradation that is observed. Because of the surrounding oxide and other thermal insulating material and the low thermal conductivity of the IGZO layer, the self-heating effect will be pronounced in wider/shorter channel length devices and those with a larger operating drain bias. To further clarify the physical mechanism, fast I{sub D}-V{sub G} and modulated peak/base pulse time I{sub D}-V{sub D} measurements are utilized to demonstrate the self-heating induced anomalous dimension-dependent threshold voltage variation and on-state current degradation.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Fabrication and characterization of Cu(In,Ga)Se{sub 2} p-channel thin film transistors

Cu(In,Ga)Se{sub 2} thin film transistors are demonstrated with the on-off ratio of ∼10{sup 3} and the saturation hole mobility of 1.8 cm{sup 2}/V-s. Due to the high hole concentration (∼5 × 10{sup 17 }cm{sup −3}), the channel needs to be etched to turn off for the accumulation mode operation. The Cu(In,Ga)Se{sub 2} film after etching reveals a larger mobility, and a narrower (112) X-ray diffraction line than the original thick layer, indicating the better crystallinity of the initial growth as compared to the subsequent Cu(In,Ga)Se{sub 2} layer. Both the hole concentration and the saturation mobility increase with the decreasing Cu/(In + Ga) ratio probably due to the effect of Cu vacancies.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Electrical characteristics of field-effect transistors based on indium arsenide nanowire thinner than 10 nm

To suppress short channel effects, lower off-state leakage current and enhance gate coupling efficiency, InAs nanowires (NWs) with diameter smaller than 10 nm could be needed in field-effect transistors (FETs) as the channel length scales down to tens of nanometers to improve the performance and increase the integration. Here, we fabricate and study FETs based on ultrathin wurtzite-structured InAs NWs, with the smallest NW diameter being 7.2 nm. The FETs based on ultrathin NWs exhibit high I{sub on}/I{sub off} ratios of up to 2 × 10{sup 8}, small subthreshold swings of down to 120 mV/decade, and operate in enhancement-mode. The performance of the devices changes as a function of the diameter of the InAs NWs. The advantages and challenges of the FETs based on ultrathin NWs are discussed.

77 NANOSCIENCE AND NANOTECHNOLOGY↗