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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 667 records · Page 37
All sourcesNASA NTRSDOE OSTI
NASA NTRS2018

SpaceWire as a Cube-Sat Instrument Interface

SpaceWire is used in the control and data interface for an instrument on a pair of small satellites, one of which was launched in summer 2017. The instrument SpaceWire interface is implemented in a Field Programmable Gate Array as an instantiated core controlled by a LEON3FT CPU, which is also implemented as an instantiated core. The UT699 processor in the flight computer provides the spacecraft side’s SpaceWire interface. A simple message based protocol consisting of four message types was defined, based on existing SpaceWire standards. One was for passing commands to and responses from the instrument in the form of text strings similar to those from a system console where each line of text is passed in a SpaceWire message. Another was for passing spacecraft time to the instrument. The third was for transferring files using a subset of the Remote Memory Access Protocol (RMAP). The fourth was for retrieving science data from the instrument. A set of user application programming interface (API) routines provided an abstracted interface to both the serial console (used during debug) and the SpaceWire device interface. Early instrument development and testing was done with a set of utilities that controlled a Star-Dundee USB-SpaceWire brick providing a user interface similar to a serial console terminal emulator with the addition of file and data transfers. Later in the integration and test process, these utilities were integrated with the COSMOS ground systems software used for spacecraft control, providing a seamless transition from standalone instrument tests to benchtop flat-sat test and full spacecraft level tests.

Lux, James P.↗
NASA NTRS2003

Advanced Data Acquisition Systems

Current and future requirements of the aerospace sensors and transducers field make it necessary for the design and development of new data acquisition devices and instrumentation systems. New designs are sought to incorporate self-health, self-calibrating, self-repair capabilities, allowing greater measurement reliability and extended calibration cycles. With the addition of power management schemes, state-of-the-art data acquisition systems allow data to be processed and presented to the users with increased efficiency and accuracy. The design architecture presented in this paper displays an innovative approach to data acquisition systems. The design incorporates: electronic health self-check, device/system self-calibration, electronics and function self-repair, failure detection and prediction, and power management (reduced power consumption). These requirements are driven by the aerospace industry need to reduce operations and maintenance costs, to accelerate processing time and to provide reliable hardware with minimum costs. The project's design architecture incorporates some commercially available components identified during the market research investigation like: Field Programmable Gate Arrays (FPGA) Programmable Analog Integrated Circuits (PAC IC) and Field Programmable Analog Arrays (FPAA); Digital Signal Processing (DSP) electronic/system control and investigation of specific characteristics found in technologies like: Electronic Component Mean Time Between Failure (MTBF); and Radiation Hardened Component Availability. There are three main sections discussed in the design architecture presented in this document. They are the following: (a) Analog Signal Module Section, (b) Digital Signal/Control Module Section and (c) Power Management Module Section. These sections are discussed in detail in the following pages. This approach to data acquisition systems has resulted in the assignment of patent rights to Kennedy Space Center under U.S. patent # 6,462,684. Furthermore, NASA KSC commercialization office has issued licensing rights to Circuit Avenue Netrepreneurs, LLC , a minority-owned business founded in 1999 located in Camden, NJ.

Perotti, J.↗
DOE OSTI2024

PLC Vulnerabilities and Mitigations

Programmable Logic Controllers (PLCs) are used extensively in many high-importance industrial and nonindustrial settings including controlling elevators, manufacturing machines, and utility facilities such as power and natural gas, however cybersecurity protection for them has been neglected. Within recent years, PLCs have been put under more security scrutiny and experts have advocated for changes from the addition of protocol encryption and network segmentation to intrusion detection systems on the PLCs themselves. While PLC security is critical, a large portion of the PLCs available today will never receive these changes due to being legacy or the difficulty of overhauling the security on existing systems. Due to the infeasibility of applying many recommended security measures towards currently available machines, we aim to provide realistic and affordable best practices for hardening PLCs. We will first conduct security analysis and consider attack vectors within our target PLC. Once we’ve analyzed the device’s security, we will evaluate a variety of mitigation methods and create guidelines to effectively reduce the threat posed by PLC attacks with minimal disruption to operations.

42 ENGINEERING↗
NASA NTRS2024

Stress Control of Multilayer Suspended MEMS Structures In High Contrast Microshutters

The microshutter array (MSA) is a programmable field mask (Fig. 1) that enables large-format multi-object spectroscopy at extremely high contrast ratios of over 105 in space [1]. Assessment of the first generation MSAs used on the James Webb Space Telescope (JWST) revealed light leakage and stuck shutters due to warping (Fig. 2) [2]. Such leakage is partially reduced with appropriate light shields and mitigation strategies. Anticipation of stricter performance requirements for the upcoming Habitable Worlds Observatory Flagship [3] motivates the study. In this paper, we present the systematic study of film stress effects using finite element modeling (FEM) and analysis of newly fabricated MSAs. We present structural designs to mitigate stress effects and improve flatness of suspended structures in micro-electromechanical systems (MEMS). Our study aims to provide a comprehensive view of film-to-film interaction, mechanical, and structural considerations in design and process definition that goes beyond NGMSA devices. The presented findings can be of value to the stress and morphology control in any suspended MEMS membranes.

Microshutters↗
DOE OSTI2013

High speed, multi-channel, user programmable digital data acquisition system.

As applications for radiation detection become more demanding, and in turn improvements are made in the technology of radiation detection, there is a need for high speed digital detector readout electronics matching these improvements. Specifically, full control over the on-line processing resources of modern digital electronics is desirable so that researchers can develop custom algorithms for special applications.In the proposed effort, the 500 MHz digital readout electronics previously developed by our company will be redesigned to allow user access to the on-line processing resources. In Phase I, the division of online processing into vendor and user firmware sections has been studied on existing hardware. In Phase II, the hardware will be upgraded to better facilitate the division, and the firmware will be restructured into a robust vendor logic block (providing standard functions such as host I/O, on-board memory I/O, energy computation, MCA spectra, timestamps, waveform capture, run statistics, and triggering and timing) and a user logic block for custom algorithms (with templates and examples for frequently used functions). Investigating several options to divide online processing, it was determined that the most promising approach is to “partition” a single FPGA integrated circuit into a vendor and user section, which is supported in newer devices. The analog front end of the existing electronics proved suitable for most applications, in particular high rate measurements with germanium detectors. The design architecture for new electronics was developed, combining one of the new FPGA device with the analog front end.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

High-speed programmable photonic circuits in a cryogenically compatible, visible–near-infrared 200 mm CMOS architecture

Abstract Recent advances in photonic integrated circuits have enabled a new generation of programmable Mach–Zehnder meshes (MZMs) realized by using cascaded Mach–Zehnder interferometers capable of universal linear-optical transformations on N input/output optical modes. MZMs serve critical functions in photonic quantum information processing, quantum-enhanced sensor networks, machine learning and other applications. However, MZM implementations reported to date rely on thermo-optic phase shifters, which limit applications due to slow response times and high power consumption. Here we introduce a large-scale MZM platform made in a 200 mm complementary metal–oxide–semiconductor foundry, which uses aluminium nitride piezo-optomechanical actuators coupled to silicon nitride waveguides, enabling low-loss propagation with phase modulation at greater than 100 MHz in the visible–near-infrared wavelengths. Moreover, the vanishingly low hold-power consumption of the piezo-actuators enables these photonic integrated circuits to operate at cryogenic temperatures, paving the way for a fully integrated device architecture for a range of quantum applications.

47 OTHER INSTRUMENTATION↗
DOE OSTI2019

Printed assemblies of microscale triple–junction inverted metamorphic GaInP/GaAs/InGaAs solar cells

Inverted metamorphic (IMM) multijunction solar cells represent a promising material platform for ultrahigh efficiency photovoltaic systems (UHPVs) with a clear pathway to beyond 50% efficiency. The conventional device processing of IMM solar cells, however, typically involves wafer bonding of a centimeter-scale die and destructive substrate removal, thereby imposing severe restrictions in achievable cell size, type of module substrate, spatial layout, as well as cost effectiveness. Here, we report material design and fabrication strategies for microscale triple-junction IMM (3J IMM) Ga 0.51 In 0.49 P/GaAs/In 0.26 Ga 0.74 As solar cells that can overcome these difficulties. Specialized schemes of delineation and undercut etching enable the defect-free release of microscale IMM solar cells and printed assemblies on a glass substrate in a manner that preserves the growth substrate, where efficiencies of 27.3% and 33.9% are demonstrated at simulated AM1.5D one- and 351 sun illumination, respectively. A composite carrier substrate where released IMM microcells are formed in fully functional, print-ready configurations allows high-throughput transfer printing of individual IMM microcells in a programmable spatial layout on versatile choices of module substrate, all desired for CPV applications.

14 SOLAR ENERGY↗
DOE OSTI2015

A novel digital pulse processing architecture for nuclear instrumentation

The field of nuclear instrumentation covers a wide range of applications, including counting, spectrometry, pulse shape discrimination and multi-channel coincidence. These applications are the topic of many researches, new algorithms and implementations are constantly proposed thanks to advances in digital signal processing. However, these improvements are not yet implemented in instrumentation devices. This is especially true for neutron-gamma discrimination applications which traditionally use charge comparison method while literature proposes other algorithms based on frequency domain or wavelet theory which show better performances. Another example is pileups which are generally rejected while pileup correction algorithms also exist. These processes are traditionally performed offline due to two issues. The first is the Poissonian characteristic of the signal, composed of random arrival pulses which requires to current architectures to work in data flow. The second is the real-time requirement, which implies losing pulses when the pulse rate is too high. Despite the possibility of treating the pulses independently from each other, current architectures paralyze the acquisition of the signal during the processing of a pulse. This loss is called dead-time. These two issues have led current architectures to use dedicated solutions based on re-configurable components like Field Programmable Gate Arrays (FPGAs) to overcome the need of performance necessary to deal with dead-time. However, dedicated hardware algorithm implementations on re-configurable technologies are complex and time-consuming. For all these reasons, a programmable Digital pulse Processing (DPP) architecture in a high level language such as Cor C++ which can reduce dead-time would be worthwhile for nuclear instrumentation. This would reduce prototyping and test duration by reducing the level of hardware expertise to implement new algorithms. However, today's programmable solutions do not meet the need of performance to operate online and not allow scaling with the increase in the number of measurement channel. That is why an innovative DPP architecture is proposed in this paper. This architecture is able to overcome dead-time while being programmable and is flexible with the number of measurement channel. Proposed architecture is based on an innovative execution model for pulse processing applications which can be summarized as follow. The signal is not composed of pulses only, consequently, pulses processing does not have to operate on the entire signal. Therefore, the first step of our proposal is pulse extraction by the use of dedicated components named pulse extractors. The triggering step can be achieved after the analog-to-digital conversion without any signal shaping or filtering stages. Pileup detection and accurate pulse time stamping are done at this stage. Any application downstream this step can work on adaptive variable-sized array of samples simplifying pulse processing methods. Then, once the data flow is broken, it is possible to distribute pulses on Functional Units (FUs) which perform processing. As the date of each pulse is known, they can be processed individually out-of-order to provide the results. To manage the pulses distribution, a scheduler and an interconnection network are used. pulses are distributed on the first FU which is not busy without congesting the interconnection network. For this reason, the process duration does not result anymore in dead-time if there are enough FUs. FUs are designed to be standalone and to comprises at least a programmable general purpose processor (ARM, Microblaze) allowing the implementation of complex algorithms without any modification of the hardware. An acquisition chain is composed of a succession of algorithms which lead to organize our FUs as a software macro-pipeline, A simple approach consists in assigning one algorithm per FU. Consequently, the global latency becomes the worst latency of algorithms execution on FU. Moreover, as algorithms are executed locally - i.e. on a FU - this approach limits shared memory requirement. To handle multichannel, we propose FUs sharing, this approach maximize the chance to find a non-busy FU to process an incoming pulse. This is possible since each channel receive random event independently, the pulse extractors associated to them do not necessarily need to access simultaneously to all Computing resources at the same time to distribute their pulses. The major contribution of this paper is the proposition of an execution model and its associated hardware programmable architecture for digital pulse processing that can handle multiple acquisition channels while maintaining the scalability thanks to the use of shared resources. This execution model and associated architecture are validated by simulation of a cycle accurate architecture SystemC model. Proposed architecture shows promising results in terms of scalability while maintaining zero dead-time. This work also permit the sizing of hardware resources requirement required for a predefined set of applications. Future work will focus on the interconnection network and a scheduling policy that can exploit the variable-length of pulses. Then, the hardware implementation of this architecture will be performed and tested for a representative set of application.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1983

A sun acquisition sensor for spacecraft guidance and control

The combination of a strap-down analog sun acquisition sensor (AS) and an on-board digital programmable signal processor results in a versatile guidance and control system. The combination can orient the rotation axis of a spin-stabilized spacecraft to the sun no matter what the initial attitude of the spacecraft. During the sun orientation process, spacecraft spin rate can be sensed and supplied as an input to the control algorithm. If needed, the AS-signal processor combination can be used to perform a rhumb-line turn maneuver. In case of unexpected spacecraft operating conditions, or unplanned pointing directions, the signal processor program can be updated via earth-based transmission of another program to cover the new situation. Using only three radiation-hard cadmium-sulfide detectors, containing no moving parts, needing only a few microwatts of power, included in a volume of 550 cubic cm (a redundant pair), and weighing only 540 grams, the AS is a small, simple, sturdy sensing device.

Birnbaum, M. M.↗
NASA NTRS2004

Communications interface for wireless communications headset

A universal interface adapter circuit interfaces, for example, a wireless communications headset with any type of communications system, including those that require push-to-talk (PTT) signaling. The interface adapter is comprised of several main components, including an RF signaling receiver, a microcontroller and associated circuitry for decoding and processing the received signals, and programmable impedance matching and line interfacing circuitry for interfacing a wireless communications headset system base to a communications system. A signaling transmitter, which is preferably portable (e.g., handheld), is employed by the wireless headset user to send signals to the signaling receiver. In an embodiment of the invention directed specifically to push-to-talk (PTT) signaling, the wireless headset user presses a button on the signaling transmitter when they wish to speak. This sends a signal to the microcontroller which decodes the signal and recognizes the signal as being a PTT request. In response, the microcontroller generates a control signal that closes a switch to complete a voice connection between the headset system base and the communications system so that the user can communicate with the communications system. With this arrangement, the wireless headset can be interfaced to any communications system that requires PTT signaling, without modification of the headset device. In addition, the interface adapter can also be configured to respond to or deliver any other types of signals, such as dual-tone-multiple-frequency (DTMF) tones, and on/off hook signals. The present invention is also scalable, and permits multiple wireless users to operate independently in the same environment through use of a plurality of the interface adapters.

Seibert, Marc A.↗
DOE OSTI2023

Field programmable spin arrays for scalable quantum repeaters

The large scale control over thousands of quantum emitters desired by quantum network technology is limited by the power consumption and cross-talk inherent in current microwave techniques. Here we propose a quantum repeater architecture based on densely-packed diamond color centers (CCs) in a programmable electrode array, with quantum gates driven by electric or strain fields. This ‘field programmable spin array’ (FPSA) enables high-speed spin control of individual CCs with low cross-talk and power dissipation. Integrated in a slow-light waveguide for efficient optical coupling, the FPSA serves as a quantum interface for optically-mediated entanglement. We evaluate the performance of the FPSA architecture in comparison to a routing-tree design and show an increased entanglement generation rate scaling into the thousand-qubit regime. Our results enable high fidelity control of dense quantum emitter arrays for scalable networking.

42 ENGINEERING↗
DOE OSTI2024

Distilling particle knowledge for fast reconstruction at high-energy physics experiments

Knowledge distillation is a form of model compression that allows artificial neural networks of different sizes to learn from one another. Its main application is the compactification of large deep neural networks to free up computational resources, in particular on edge devices. In this article, we consider proton-proton collisions at the High-Luminosity Large Hadron Collider (HL-LHC) and demonstrate a successful knowledge transfer from an event-level graph neural network (GNN) to a particle-level small deep neural network (DNN). Our algorithm, DistillNet, is a DNN that is trained to learn about the provenance of particles, as provided by the soft labels that are the GNN outputs, to predict whether or not a particle originates from the primary interaction vertex. The results indicate that for this problem, which is one of the main challenges at the HL-LHC, there is minimal loss during the transfer of knowledge to the small student network, while improving significantly the computational resource needs compared to the teacher. This is demonstrated for the distilled student network on a CPU, as well as for a quantized and pruned student network deployed on a field programmable gate array. Our study proves that knowledge transfer between networks of different complexity can be used for fast artificial intelligence (AI) in high-energy physics that improves the expressiveness of observables over non-AI-based reconstruction algorithms. Such an approach can become essential at the HL-LHC experiments, e.g. to comply with the resource budget of their trigger stages.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
DOE OSTI2012

Evaluation of the Leon3 Soft-Core Processor Within a Xilinx Radiation-Hardened Field-Programmable Gate Array

The purpose of this document is to summarize the work done to evaluate the performance of the Leon3 soft-core processor in a radiation environment while instantiated in a radiation-hardened static random-access memory based field-programmable gate array. This evaluation will look at the differences between two soft-core processors: the open-source Leon3 core and the fault-tolerant Leon3 core. Radiation testing of these two cores was conducted at the Texas A&M University Cyclotron facility and Lawrence Berkeley National Laboratory. The results of these tests are included within the report along with designs intended to improve the mitigation of the open-source Leon3. The test setup used for evaluating both versions of the Leon3 is also included within this document.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2004

Tunable-Bandwidth Filter System

A tunable-bandwidth filter system (TBFS), now undergoing development, is intended to be part of a remote sensing multispectral imaging system that will operate in the visible and near infrared spectral region (wavelengths from 400 to 900 nm). Attributes of the TBFS include rapid tunability of the pass band over a wide wavelength range and high transmission efficiency. The TBFS is based on a unique integration of two pairs of broadband Raman reflection holographic filters with two rotating spherical lenses. In experiments, a prototype of the TBFS, was shown to be capable of spectral sampling of images in the visible range over a 200 nm spectral range with a spectral resolution of 30 nm. The figure depicts the optical layout of a prototype of the TBFS as part of a laboratory multispectral imaging system for the spectral sampling of color test images in two orthogonal polarizations. Each pair of broadband Raman reflection holographic filters is mounted at an equatorial plane between two halves of a spherical lens. The two filters in each pair are characterized by steep spectral slopes (equivalently, narrow spectral edges), no ripple or side lobes in their pass bands, and a few nanometers of non-overlapping wavelength range between their pass bands. Each spherical lens and thus the filter pair within it is rotated in order to rapidly tune its pass band. The rotations of are effected by electronically controlled, programmable, high-precision rotation stages. The rotations are coordinated by electronic circuits operating under overall supervision of a personal computer in order to obtain the desired variation of the overall pass bands with time. Embedding the filters inside the spherical lenses increases the range of the hologram incidence angles, making it possible to continuously tune the pass and stop bands of the filters over a wider wavelength range. In addition, each spherical lens also serves as part of the imaging optics: The telephoto lens focuses incoming light to a field stop that is also a focal point of each spherical lens. A correcting lens in front of the field stop compensates for the spherical aberration of the spherical lenses. The front surface of each spherical lens collimates the light coming from the field stop. After the collimated light passes through the filter in the spherical lens, the rear surface of the lens focuses the light onto a charge-coupled-device image detector.

Bailey, John W.↗
NASA NTRS2006

Tunable-Bandwidth Filter System

A tunable-bandwidth filter system (TBFS), now undergoing development, is intended to be part of a remote-sensing multispectral imaging system that will operate in the visible and near infrared spectral region (wavelengths from 400 to 900 nm). Attributes of the TBFS include rapid tunability of the pass band over a wide wavelength range and high transmission efficiency. The TBFS is based on a unique integration of two pairs of broadband Raman reflection holographic filters with two rotating spherical lenses. In experiments, a prototype of the TBFS was shown to be capable of spectral sampling of images in the visible range over a 200-nm spectral range with a spectral resolution of .30 nm. The figure depicts the optical layout of a prototype of the TBFS as part of a laboratory multispectral imaging system for the spectral sampling of color test images in two orthogonal polarizations. Each pair of broadband Raman reflection holographic filters is mounted at an equatorial plane between two halves of a spherical lens. The two filters in each pair are characterized by steep spectral slopes (equivalently, narrow spectral edges), no ripple or side lobes in their pass bands, and a few nanometers of non-overlapping wavelength range between their pass bands. Each spherical lens and thus the filter pair within it is rotated in order to rapidly tune its pass band. The rotations of the lenses are effected by electronically controlled, programmable, high-precision rotation stages. The rotations are coordinated by electronic circuits operating under overall supervision of a personal computer in order to obtain the desired variation of the overall pass bands with time. Embedding the filters inside the spherical lenses increases the range of the hologram incidence angles, making it possible to continuously tune the pass and stop bands of the filters over a wider wavelength range. In addition, each spherical lens also serves as part of the imaging optics: The telephoto lens focuses incoming light to a field stop that is also a focal point of each spherical lens. A correcting lens in front of the field stop compensates for the spherical aberration of the spherical lenses. The front surface of each spherical lens collimates the light coming from the field stop. After the collimated light passes through the filter in the spherical lens, the rear surface of the lens focuses the light onto a charge-coupled-device image detector.

Aye, Tin↗
NASA NTRSDate not supplied

Alternative Setup for Long-Duration Low-Duty-Cycle 600°C Ambient Testing of SiC Integrated Circuits

A scalable, compact oven testbed system for simultaneously evaluating a multitude of high temperature integrated circuits (ICs) for prolonged operating times of up to 600 °C has been prototyped. The new testbed system enables long-duration high temperature testing in sufficient statistical quantities consistent with standard aerospace electronics engineering standards. This setup is comprised of multiple compact ovens housing chips or packages mounted to ceramic circuit boards. Each oven is a compact 15.2 cm length by 15.2 cm width by 12.7 cm depth with a maximum 400 Watts of heating power. The custom-made silicon oxide ceramic heating block inside each oven is based on a 3D printed design adapted for the easy insertion of the IC device under test (DUT). This innovative design provides the quick insertion of ICs with or without a ceramic package into a 600 °C environment by utilizing a movable 11.43 cm long ceramic substrate with electrical traces extending from the oven hot zone to external standard plastic-based board connectors. Another key oven design feature is the minimization of the DUT exposure to electromagnetic interference (EMI) by utilizing a filtered DC power source to reduce heating element noise. Additionally, the ovens can be configured in a parallel arrangement allowing global data monitoring over a single industrial RS422 serial port. This feature is important for scaling up to test multiple ICs semi-simultaneously. A USB serial port is provided to independently control the operating parameters of each oven such as the oven target temperature and oven ramp rate. The oven temperature can reach up to 600 °C with a confirmed +/- 4 °C maximum deviation across the test zone region. The ramp rate can be programmed from 1 °C/minute up to 10 °C/minute. Furthermore, a programmable switchboard is used to interface with the DUT. This switchboard comprises a National Instruments Peripheral Component Interconnect eXtension for Instrumentation (NI PXI) system and a breakout board to send and receive power, analog or digital test signals. By using this unique oven testbed system, a variety of ICs can now be tested in parallel using the same test components configured for a diverse set of requirements.

DC Powered Oven↗
DOE OSTI2021

A Fabrication Strategy for Reconfigurable Millimeter–Scale Metamaterials

Rather than depending on material composition to primarily dictate performance metrics, metamaterials can leverage geometry to achieve specific properties of interest. For example, reconfigurable metamaterials have enabled programmable shape transformations, tunable mechanical properties, and energy absorption. While several methods exist to fabricate such structures, they often place severe restrictions on manufacturing materials, or require significant manual assembly. Moreover, these arrays are typically composed of unit cells that are either macro–scale or micro–scale in dimension. Here, the fabrication gap is bridged, and laminate manufacturing is used to develop a method for designing reconfigurable metamaterials at the millimeter–scale, that is compatible with a wide range of materials, and that requires minimal manual assembly. In addition to showing the versatility of this fabrication method, how the use of laminate manufacturing affects the behavior of these multi–component arrays is also characterized. To this end, a numerical model that captures the deformations exhibited by the structures is developed, and an analytic model that predicts the strain of the structure under compressive stress is built. Overall, this approach can be leveraged to develop millimeter–scale metamaterials for applications that require reconfigurable materials, such as in the design of tunable acoustics, photonic waveguides, and electromagnetic devices.

36 MATERIALS SCIENCE↗
NASA NTRS2012

Fault-Tolerant, Real-Time, Multi-Core Computer System

A document discusses a fault-tolerant, self-aware, low-power, multi-core computer for space missions with thousands of simple cores, achieving speed through concurrency. The proposed machine decides how to achieve concurrency in real time, rather than depending on programmers. The driving features of the system are simple hardware that is modular in the extreme, with no shared memory, and software with significant runtime reorganizing capability. The document describes a mechanism for moving ongoing computations and data that is based on a functional model of execution. Because there is no shared memory, the processor connects to its neighbors through a high-speed data link. Messages are sent to a neighbor switch, which in turn forwards that message on to its neighbor until reaching the intended destination. Except for the neighbor connections, processors are isolated and independent of each other. The processors on the periphery also connect chip-to-chip, thus building up a large processor net. There is no particular topology to the larger net, as a function at each processor allows it to forward a message in the correct direction. Some chip-to-chip connections are not necessarily nearest neighbors, providing short cuts for some of the longer physical distances. The peripheral processors also provide the connections to sensors, actuators, radios, science instruments, and other devices with which the computer system interacts.

Gostelow, Kim P.↗