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All sourcesNASA NTRSDOE OSTI
NASA NTRS2000

"Genetically Engineered" Nanoelectronics

The quantum mechanical functionality of nanoelectronic devices such as resonant tunneling diodes (RTDs), quantum well infrared-photodetectors (QWIPs), quantum well lasers, and heterostructure field effect transistors (HFETs) is enabled by material variations on an atomic scale. The design and optimization of such devices requires a fundamental understanding of electron transport in such dimensions. The Nanoelectronic Modeling Tool (NEMO) is a general-purpose quantum device design and analysis tool based on a fundamental non-equilibrium electron transport theory. NEW was combined with a parallelized genetic algorithm package (PGAPACK) to evolve structural and material parameters to match a desired set of experimental data. A numerical experiment that evolves structural variations such as layer widths and doping concentrations is performed to analyze an experimental current voltage characteristic. The genetic algorithm is found to drive the NEMO simulation parameters close to the experimentally prescribed layer thicknesses and doping profiles. With such a quantitative agreement between theory and experiment design synthesis can be performed.

Klimeck, Gerhard↗
NASA NTRS2000

Characteristics of Monolithically Integrated InGaAs Active Pixel Imager Array

Switching and amplifying characteristics of a newly developed monolithic InGaAs Active Pixel Imager Array are presented. The sensor array is fabricated from InGaAs material epitaxially deposited on an InP substrate. It consists of an InGaAs photodiode connected to InP depletion-mode junction field effect transistors (JFETs) for low leakage, low power, and fast control of circuit signal amplifying, buffering, selection, and reset. This monolithically integrated active pixel sensor configuration eliminates the need for hybridization with silicon multiplexer. In addition, the configuration allows the sensor to be front illuminated, making it sensitive to visible as well as near infrared signal radiation. Adapting the existing 1.55 micrometer fiber optical communication technology, this integration will be an ideal system of optoelectronic integration for dual band (Visible/IR) applications near room temperature, for use in atmospheric gas sensing in space, and for target identification on earth. In this paper, two different types of small 4 x 1 test arrays will be described. The effectiveness of switching and amplifying circuits will be discussed in terms of circuit effectiveness (leakage, operating frequency, and temperature) in preparation for the second phase demonstration of integrated, two-dimensional monolithic InGaAs active pixel sensor arrays for applications in transportable shipboard surveillance, night vision, and emission spectroscopy.

Kim, Q.↗
NASA NTRS1997

The Development of Si and SiGe Technologies for Microwave and Millimeter-Wave Integrated Circuits

Historically, microwave technology was developed by military and space agencies from around the world to satisfy their unique radar, communication, and science applications. Throughout this development phase, the sole goal was to improve the performance of the microwave circuits and components comprising the systems. For example, power amplifiers with output powers of several watts over broad bandwidths, low noise amplifiers with noise figures as low as 3 dB at 94 GHz, stable oscillators with low noise characteristics and high output power, and electronically steerable antennas were required. In addition, the reliability of the systems had to be increased because of the high monetary and human cost if a failure occurred. To achieve these goals, industry, academia and the government agencies supporting them chose to develop technologies with the greatest possibility of surpassing the state of the art performance. Thus, Si, which was already widely used for digital circuits but had material characteristics that were perceived to limit its high frequency performance, was bypassed for a progression of devices starting with GaAs Metal Semiconductor Field Effect Transistors (MESFETs) and ending with InP Pseudomorphic High Electron Mobility Transistors (PHEMTs). For each new material or device structure, the electron mobility increased, and therefore, the high frequency characteristics of the device were improved. In addition, ultra small geometry lithographic processes were developed to reduce the gate length to 0.1 pm which further increases the cutoff frequency. The resulting devices had excellent performance through the millimeter-wave spectrum.

Ponchak, George E.↗
NASA NTRS2000

Effects of Hydrogen on Tantalum Nitride Resistors

In this paper we report on observations of degradation of thin film Tantalum Nitride chip resistors in a hermetically sealed hybrid. The observations have been attributed to the reaction of residual Palladium with desorbed Hydrogen on the surface of the resistor film. Hydrogen gas has been observed to desorb from various sources within the sealed hybrid as a result of temperature elevation. The hydrogen gas has been reported to undergo a reaction with elements such as Platinum and Palladium causing device degradation in Gallium Arsenide Field Effect Transistors. The experimental procedures and data relating to this observation along with a discussion of available risk mitigation techniques will be presented.

Weiler, James↗
NASA NTRS2000

Infrared Emission Spectroscopy as a Reliability Tool

In this paper we report on a technique based on infrared emission spectroscopy which has been found to be useful for non-contact measurement of the temperature of a hot spot in the gate channel of a GaAs metal/semiconductor field effect transistor (MESFET). The technique was demonstrated on a powered and un-powered GaAs MESFET attaining a spatial resolution of 0.5 microns. A non-destructive submicron-size spot laser beam provided by an HeNe laser excites an extremely small local area of the gate channel of a GaAs MESFET under various operating conditions. Given the state of the experimental test system, we estimate a spatial resolution of about 0.1 microns and a spectral resolution of about 0. I Angstroms. This provides 15 - 100 times finer spatial resolution than can be obtained using the best passive IR systems available. The temperature resolution (less than 0.02 K/micron) of this technique is depend upon the spectrometer used, and that it can be improved further. The information obtained from this technique can be used to estimate device lifetimes for critical applications and for measurement of channel temperature of devices under actual operating conditions. Another potential use of the novel technique can be as a cost-effective prescreening tool for determining the "hot spot" channel temperature of devices under normal operating conditions which can further improve device design, yield enhancement, and reliable operation

Kim, Q.↗
NASA NTRS2000

Modeling of Current-Voltage Characteristics in Large Metal-Semiconducting Carbon Nanotube Systems

A model is proposed for two observed current-voltage (I-V) patterns in recent experiment with a scanning tunneling microscope tip and a carbon nanotube [Collins et al., Science 278, 100 (1997)]. We claim that there are two contact modes for a tip (metal)-nanotube (semiconductor) junction depending whether the alignment of the metal and the semiconductor band structures is (1) variable (vacuum-gap) or (2) fixed (touching) with V. With the tip grounded, the tunneling case in (1) would produce large dI/dV with V > 0, small dI/dV with V < 0, and I = 0 near V = 0 for an either n- or p-nanotube. However, the Schottky mechanism in (2) would result in forward current with V < 0 for an n-nanotube, while with V > 0 for an p-nanotube. The two observed I-V patterns are thus entirely explained by a tip-nanotube contact of the two types, where the nanotube must be n-type. We apply this model to the source-drain I-V characteristics in a long nanotube-channel field-effect-transistor with metallic electrodes at low temperature [Zhou et al., Appl. Phys. Lett. 76, 1597 (2000)], and show that two independent metal-semiconductor junctions in series are responsible for the observed behavior.

Yamada, Toshishige↗
NASA NTRS2001

Metallic Electrode: Semiconducting Nanotube Junction Model

A model is proposed for two observed current-voltage (I-V) patterns in an experiment with a scanning tunneling microscope tip and a carbon nanotube [Collins et al., Science 278, 100 ('97)]. We claim that there are two contact modes for a tip (metal) -nanotube semi conductor) junction depending whether the alignment of the metal and semiconductor band structure is (1) variable (vacuum-gap) or (2) fixed (touching) with V. With the tip grounded, the tunneling case in (1) would produce large dI/dV with V > 0, small dI/dV with V < 0, and I = 0 near V = 0 for an either n- or p-nanotube. However, the Schottky mechanism in (2) would result in forward current with V < 0 for an n-nanotube, while with V > 0 for an p-nanotube. The two observed I-V patterns are thus entirely explained by a tip-nanotube contact of the two types, where the nanotube must be n-type. We apply this picture to the source-drain I-V characteristics in a long nanotube-channel field-effect-transistor (Zhou et al., Appl. Phys. Lett. 76, 1597 ('00)], and show that two independent metal-semiconductor junctions connected in series are responsible for the observed behavior.

Yamada, Toshishige↗
NASA NTRS2001

Development of Low-Noise High Value Chromium Silicide Resistors for Cryogenic Detector Applications

Extremely high sensitivity detectors, such as silicon bolometers are required in many NASA missions for detection of photons from the x-ray to the far infrared regions. Typically, these detectors are cooled to well below the liquid helium (LHe) temperature (4.2 K) to achieve the maximum detection performance. As photoconductors, they are generally operated with a load resistor and a pre-set bias voltage, which is then coupled to the input gate of a source-follower Field Effect Transistor (FET) circuit. It is imperative that the detector system signal to noise performance be limited by the noise of the detector and not by the noise of the external components. The load resistor value is selected to optimize the detector performance. These two criteria tend to be contradictory in that these detectors require load resistors in the hundreds of megaohms, which leads to a higher Johnson noise. Additionally, the physical size of the resistor must be small for device integration as required by such missions as the NASA High Resolution Airborne Wide-Band Camera (HAWC) instrument and the Submillimeter High Angular Resolution Camera (SHARC) for the Caltech Submillimeter Observatory (CSO). We have designed, fabricated and characterized thin film resistors using a CrSi/TiW/Al metal system on optical quality quartz substrates. The resistor values range from 100 megaohms to over 650 megaohms and are Johnson noise limited at LHe temperatures. The resistor film is sputtered with a sheet resistance ranging from 300 ohms to 1600 ohms and the processing sequence developed for these devices allows for chemically fine tuning the sheet resistance in-situ. The wafer fabrication process was of sufficiently high yield (>80%) providing clusters of good resistors for integrated multiple detector channels, a very important feature in the assembly of these two instruments.

Jhabvala, Murzy↗
NASA NTRS2001

The HP 85192B EEFet3 GaAs FET Nonlinear Model Used in the High Efficiency Microwave Power Amplifier (HEMPA)

Most nonlinear circuit analysis programs that exist today were designed primarily for transient analysis. By incorporating more accurate models in simulation programs, accurate predictions of GaAs field effect transistors (FET) behavior can be accomplished. However, should the designer need to simulate GaAs FETs that operate at high DC-to-RF conversion efficiencies, a more sophisticated model is needed. A relevant and appropriate method is called harmonic-balance, as described by Quere et al.

Sims, William Herbert, III↗
NASA NTRS1998

Multi-Dimensional Quantum Effect Simulation Using a Density-Gradient Model and Script-Level Programming Techniques

A density-gradient (DG) model is used to calculate quantum-mechanical corrections to classical carrier transport in MOS (Metal Oxide Semiconductor) inversion/accumulation layers. The model is compared to measured data and to a fully self-consistent coupled Schrodinger and Poisson equation (SCSP) solver. Good agreement is demonstrated for MOS capacitors with gate oxide as thin as 21 A. It is then applied to study carrier distribution in ultra short MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) with surface roughness. This work represents the first implementation of the DG formulation on multidimensional unstructured meshes. It was enabled by a powerful scripting approach which provides an easy-to-use and flexible framework for solving the fourth-order PDEs (Partial Differential Equation) of the DG model.

Rafferty, Connor S.↗
NASA NTRS1999

Multi-Dimensional Quantum Tunneling and Transport Using the Density-Gradient Model

We show that quantum effects are likely to significantly degrade the performance of MOSFETs (metal oxide semiconductor field effect transistor) as these devices are scaled below 100 nm channel length and 2 nm oxide thickness over the next decade. A general and computationally efficient electronic device model including quantum effects would allow us to monitor and mitigate these effects. Full quantum models are too expensive in multi-dimensions. Using a general but efficient PDE solver called PROPHET, we implemented the density-gradient (DG) quantum correction to the industry-dominant classical drift-diffusion (DD) model. The DG model efficiently includes quantum carrier profile smoothing and tunneling in multi-dimensions and for any electronic device structure. We show that the DG model reduces DD model error from as much as 50% down to a few percent in comparison to thin oxide MOS capacitance measurements. We also show the first DG simulations of gate oxide tunneling and transverse current flow in ultra-scaled MOSFETs. The advantages of rapid model implementation using the PDE solver approach will be demonstrated, as well as the applicability of the DG model to any electronic device structure.

Biegel, Bryan A.↗
NASA NTRS2002

Efficient Design in a DC to DC Converter Unit

Space Flight hardware requires high power conversion efficiencies due to limited power availability and weight penalties of cooling systems. The International Space Station (ISS) Electric Power System (EPS) DC-DC Converter Unit (DDCU) power converter is no exception. This paper explores the design methods and tradeoffs that were utilized to accomplish high efficiency in the DDCU. An isolating DC to DC converter was selected for the ISS power system because of requirements for separate primary and secondary grounds and for a well-regulated secondary output voltage derived from a widely varying input voltage. A flyback-current-fed push-pull topology or improved Weinberg circuit was chosen for this converter because of its potential for high efficiency and reliability. To enhance efficiency, a non-dissipative snubber circuit for the very-low-Rds-on Field Effect Transistors (FETs) was utilized, redistributing the energy that could be wasted during the switching cycle of the power FETs. A unique, low-impedance connection system was utilized to improve contact resistance over a bolted connection. For improved consistency in performance and to lower internal wiring inductance and losses a planar bus system is employed. All of these choices contributed to the design of a 6.25 KW regulated dc to dc converter that is 95 percent efficient. The methodology used in the design of this DC to DC Converter Unit may be directly applicable to other systems that require a conservative approach to efficient power conversion and distribution.

Bruemmer, Joel E.↗
NASA NTRS2003

Design of a Ferroelectric Programmable Logic Gate Array

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

MacLeod, Todd C.↗
NASA NTRS2003

Single Event Effects Testing of the Linfinity SG1525A Pulse Width Modulator Controller

Pulse Width Modulator (PWM) Controllers are the heart of switching power supply systems in development today. The PWMs considered here have the same integration advantages as many other controllers but it also includes the interface drivers for the follow-on power Field Effect Transistors (FET). Previous work on these types of devices looked into the required test methodologies [ 11 and the impact of radiation on the soft start and shutdown circuits of typically incorporated in the technology [2]. Taking advantage of this previous work this study was undertaken to determine the single event destructive and transient susceptibility of the Linfinity SG1525A Pulse Width Modulator Controller. The device was monitored for transient interruptions in the output signals and for destructive events induced by exposing it to a heavy ion beam at the Texas A&M University Cyclotron Single Event Effects Test Facility. After exposing these devices to the beam, a new upset mode has been identified that can lead to catastrophic power supply system failure if this event would occur while drive power FETs off the two device outputs. The devices and the test methods used will be described first. This will be followed by a brief description of the data collected to date (not all data can be presented with the length constraints of the summary) and a summary of the key results.

Howard, J. W., Jr.↗
NASA NTRS2003

High Electron Mobility in SiGe/Si n-MODFET Structures on Sapphire Substrates

For the first time, SiGe/Si n-Modulation Doped Field Effect Transistors (n-MODFET) structures have been grown on sapphire substrates. Room temperature electron mobility value of 1271 square centimeters N-sec at an electron carrier density (n(sub e) = 1.33x10(exp 12) per square centimeter)) of 1.6 x 10(exp 12) per square centimeter was obtained. At 250 mK, the mobility increases to 13,313 square centimeters/V-sec (n(sub e)=1.33x10(exp 12) per square centimeter)) and Shubnikov-de Haas oscillations appear, showing excellent confinement of the two-dimensional electron gas.

Mueller, Carl H.↗
NASA NTRS2004

A Two-Dimensional, Semiconducting Bolometer Array for HAWC

The Stratospheric Observatory For Infrared Astronomy's (SOFIA's) High resolution Airborne Wideband Camera (HAWC) will use an ion-implanted silicon bolometer array developed at NASA s Goddard Space Flight Center (GSFC). The GSFC Pop-Up Detectors (PUDs) use a unique folding technique to enable a 12 x 32 element closepacked array of bolometers with a filling factor greater than 95%. The HAWC detector uses a resistive metal film on silicon to provide frequency independent, approx. 50% absorption over the 40 - 300 micron band. The silicon bolometers are manufactured in 32-element rows within silicon frames using Micro Electro Mechanical Systems (MEMS) silicon etching techniques. The frames are then cut, "folded", and glued onto a metallized, ceramic, thermal bus "bar". Optical alignment using micrometer jigs ensures their uniformity and correct placement. The rows are then stacked side-by-side to create the final 12 x 32 element array. A kinematic Kevlar suspension system isolates the 200 mK bolometer cold stage from the rest of the 4K detector housing. GSFC - developed silicon bridge chips make electrical connection to the bolometers, while maintaining thermal isolation. The Junction Field Effect Transistor (JFET) preamplifiers for all the signal channels operate at 120 K, yet they are electrically connected and located in close proximity to the bolometers. The JFET module design provides sufficient thermal isolation and heat sinking for these, so that their heat is not detected by the bolometers. Preliminary engineering results from the flight detector dark test run are expected to be available in July 2004. This paper describes the array assembly and mechanical and thermal design of the HAWC detector and the JFET module.

Voellmer, George M.↗
NASA NTRS2005

High Temperature Performance of a SiC MESFET Based Oscillator

A hybrid, UHF-Band differential oscillator based on 10 w SiC RF Power Metal Semiconductor Field Effect Transistor (MESFET) has been designed, fabricated and characterized through 475 C. Circuit is fabricated on an alumina substrate with thin film spiral inductors, chip capacitors, chip resistors, and wire bonds for all crossovers and interconnectors. The oscillator delivers 15.7 dBm at 515 MHz into a 50 Ohm load at 125 C with a DC to RF conversion efficiency of 2,8%. After tuning the load impedance, the oscillator delivers 18.8 dBm at 610 MHz at 200 C with a DC to RF conversion efficiency of 5.8%. Finally, by tuning the load and bias conditions, the oscillator delivers 4.9 dBm at 453 MHz at 475 C.

Schwartz, Zachary D.↗
NASA NTRS2001

Atomically Flat Surfaces Developed for Improved Semiconductor Devices

New wide bandgap semiconductor materials are being developed to meet the diverse high temperature, -power, and -frequency demands of the aerospace industry. Two of the most promising emerging materials are silicon carbide (SiC) for high-temperature and high power applications and gallium nitride (GaN) for high-frequency and optical (blue-light-emitting diodes and lasers) applications. This past year Glenn scientists implemented a NASA-patented crystal growth process for producing arrays of device-size mesas whose tops are atomically flat (i.e., step-free). It is expected that these mesas can be used for fabricating SiC and GaN devices with major improvements in performance and lifetime. The promising new SiC and GaN devices are fabricated in thin-crystal films (known as epi films) that are grown on commercial single-crystal SiC wafers. At this time, no commercial GaN wafers exist. Crystal defects, known as screw defects and micropipes, that are present in the commercial SiC wafers propagate into the epi films and degrade the performance and lifetime of subsequently fabricated devices. The new technology isolates the screw defects in a small percentage of small device-size mesas on the surface of commercial SiC wafers. This enables atomically flat surfaces to be grown on the remaining defect-free mesas. We believe that the atomically flat mesas can also be used to grow GaN epi films with a much lower defect density than in the GaN epi films currently being grown. Much improved devices are expected from these improved low-defect epi films. Surface-sensitive SiC devices such as Schottky diodes and field effect transistors should benefit from atomically flat substrates. Also, we believe that the atomically flat SiC surface will be an ideal surface on which to fabricate nanoscale sensors and devices. The process for achieving atomically flat surfaces is illustrated. The surface steps present on the "as-received" commercial SiC wafer is also illustrated. because of the small tilt angle between the crystal "basal" plane and the polished wafer surface. These steps are used in normal SiC epi film growth in a process known as stepflow growth to produce material for device fabrication. In the new process, the first step is to etch an array of mesas on the SiC wafer top surface. Then, epi film growth is carried out in the step flow fashion until all steps have grown themselves out of existence on each defect-free mesa. If the size of the mesas is sufficiently small (about 0.1 by 0.1 mm), then only a small percentage of the mesas will contain an undesired screw defect. Mesas with screw defects supply steps during the growth process, allowing a rough surface with unwanted hillocks to form on the mesa. The improvement in SiC epi surface morphology achievable with the new technology is shown. An atomic force microscope image of a typical SiC commercial epilayer surface is also shown. A similar image of an SiC atomically flat epi surface grown in a Glenn laboratory is given. With the current screw defect density of commercial wafers (about 5000 defects/cm2), the yield of atomically free 0.1 by 0.l mm mesas is expected to be about 90 percent. This is large enough for many types of electronic and optical devices. The implementation of this new technology was recently published in Applied Physics Letters. This work was initially carried out in-house under a Director's Discretionary Fund project and is currently being further developed under the Information Technology Base Program.

Powell, J. Anthony↗