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At least 667 records · Page 37
All sourcesNASA NTRSDOE OSTI
NASA NTRS1972

Hierarchical hybrid control of manipulators: Artificial intelligence in large scale integrated circuits

Both in practical engineering and in control of muscular systems, low level subsystems automatically provide crude approximations to the proper response. Through low level tuning of these approximations, the proper response variant can emerge from standardized high level commands. Such systems are expressly suited to emerging large scale integrated circuit technology. A computer, using symbolic descriptions of subsystem responses, can select and shape responses of low level digital or analog microcircuits. A mathematical theory that reveals significant informational units in this style of control and software for realizing such information structures are formulated.

Greene, P. H.↗
NASA NTRS1984

CYBER 200 Applications Seminar

Applications suited for the CYBER 200 digital computer are discussed. Various areas of application including meteorology, algorithms, fluid dynamics, monte carlo methods, petroleum, electronic circuit simulation, biochemistry, lattice gauge theory, economics and ray tracing are discussed.

Gary, J. P.↗
NASA NTRS1993

Delay analysis of combinations of pass transistors and classical logic gates

Combinations of pass transistors and logic gates driving nonlinear capacitive loads are analyzed for the presence of characteristics that will permit easier and more accurate digital logic simulation. Accurate time delay models are developed by studying the nature of the response of simplified circuit models to variations of input waveform rise and fall times and output loading. The nonlinear effects of the CMOS logic devices are minimized to permit easier interpretation of the influence of nonlinear capacitive loads. The performance of a CMOS inverter with a complex nonlinear load consisting of a pass transistor that separates a range of capacitances is compared to the same inverter circuit with a linear capacitive load to develop an understanding of the unique requirements of modeling a nonlinear system. Several methods of modeling the delay of CMOS circuits are reviewed, and a multi-parameter linear model is described. General guidelines for designing CMOS circuits with complex load circuits are developed, emphasizing that the circuit output rise delays and fall delays must be separately analyzed.

Gibson, Jonathan S.↗
NASA NTRS1998

A Spaceflight Magnetic Bearing Equipped Optical Chopper with Six-Axis Active Control

This paper describes the development of an ETU (Engineering Test Unit) rotary optical chopper with magnetic bearings. An ETU is required to be both flight-like, nearly identical to a flight unit without the need for material certifications, and demonstrate structural and performance integrity. A prototype breadboard design previously demonstrated the feasibility of meeting flight performance requirements using magnetic bearings. The chopper mechanism is a critical component of the High Resolution Dynamics Limb Sounder (HIRDLS) which will be flown on EOS-CHEM (Earth Observing System-Chemistry). Particularly noteworthy are the science requirements which demand high precision positioning and minimal power consumption along with full redundancy of coils and sensors in a miniature, lightweight package. The magnetic bearings are unique in their pole design to minimize parasitic losses and utilize collocated optical sensing. The motor is of an unusual disk-type ironless stator design. The ETU design has evolved from the breadboard design. A number of improvements have been incorporated into the ETU design. Active thrust control has been added along with changes to improve sensor stability, motor efficiency, and touchdown and launch survivability. It was necessary to do all this while simultaneously reducing the mechanism volume. Flight-like electronics utilize a DSP (Digital Signal Processor) and contain all sensor electronics and drivers on a single five inch by nine inch circuit board. Performance test results are reported including magnetic bearing and motor rotational losses.

Blumenstock, Kenneth A.↗
NASA NTRS1998

A Spaceflight Magnetic Bearing Equipped Optical Chopper with Six-Axis Active Control

This paper describes the development of an ETU (Engineering Test Unit) rotary optical chopper with magnetic bearings. An ETU is required to be both flight-like, nearly identical to a flight unit without the need for material certifications, and demonstrate structural and performance integrity. A prototype breadboard design previously demonstrated the feasibility of meeting flight performance requirements using magnetic bearings. The chopper mechanism is a critical component of the High Resolution Dynamics Limb Sounder (HIRDLS) which will be flown on EOS-CHEM (Earth Observing System-Chemistry). Particularly noteworthy are the science requirements which demand high precision positioning and minimal power consumption along with full redundancy of coils and sensors in a miniature, lightweight package. The magnetic bearings are unique in their pole design to minimize parasitic losses and utilize collocated optical sensing. The motor is of an unusual disk-type ironless stator design. The ETU design has evolved from the breadboard design. A number of improvements have been incorporated into the ETU design. Active thrust control has been added along with changes to improve sensor stability, motor efficiency, and touchdown and launch survivability. It was necessary to do all this while simultaneously reducing the mechanism volume. Flight-like electronics utilize a DSP (Digital Signal Processor) and contain all sensor electronics and drivers on a single five inch by nine inch circuit board. Performance test results are reported including magnetic bearing and motor rotational losses.

Blumenstock, K. A.↗
NASA NTRS1998

A Spaceflight Magnetic Bearing Equipped Optical Chopper with Six-Axis Active Control

This paper describes the development of an ETU (Engineering Test Unit) rotary optical chopper with magnetic bearings. An ETU is required to be both flight-like, nearly identical to a flight unit without the need for material certifications, and demonstrate structural and performance integrity. A prototype breadboard design previously demonstrated the feasibility of meeting flight performance requirements using magnetic bearings. The chopper mechanism is a critical component of the High Resolution Dynamics Limb Sounder (HIRDLS) which will be flown on EOS-CHEM (Earth Observing System-Chemistry). Particularly noteworthy are the science requirements which demand high precision positioning and minimal power consumption along with full redundancy of coils and sensors in a miniature, lightweight package. The magnetic bearings are unique in their pole design to minimize parasitic losses and utilize collocated optical sensing. The motor is of an unusual disk-type ironless stator design. The ETU design has evolved from the breadboard design. A number of improvements have been incorporated into the ETU design. Active thrust control has been added along with changes to improve sensor stability, motor efficiency, and touchdown and launch survivability. It was necessary to do all this while simultaneously reducing the mechanism volume. Flight-like electronics utilize a DSP (Digital Signal Processor) and contain all sensor electronics and drivers on a single five inch by nine inch circuit board. Performance test results are reported including magnetic bearing and motor rotational losses.

Blumenstock, Kenneth A.↗
NASA NTRS2000

Using Modern Design Tools for Digital Avionics Development

Using Modem Design Tools for Digital Avionics Development Shrinking development time and increased complexity of new avionics forces the designer to use modem tools and methods during hardware development. Engineers at the Marshall Space Flight Center have successfully upgraded their design flow and used it to develop a Mongoose V based radiation tolerant processor board for the International Space Station's Water Recovery System. The design flow, based on hardware description languages, simulation, synthesis, hardware models, and full functional software model libraries, allowed designers to fully simulate the processor board from reset, through initialization before any boards were built. The fidelity of a digital simulation is limited to the accuracy of the models used and how realistically the designer drives the circuit's inputs during simulation. By using the actual silicon during simulation, device modeling errors are reduced. Numerous design flaws were discovered early in the design phase when they could be easily fixed. The use of hardware models and actual MIPS software loaded into full functional memory models also provided checkout of the software development environment. This paper will describe the design flow used to develop the processor board and give examples of errors that were found using the tools. An overview of the processor board firmware will also be covered.

Hyde, David W.↗
NASA NTRS2003

Field Programmable Gate Array for Implementation of Redundant Advanced Digital Feedback Control

The goal of this effort was to develop a digital motor controller using field programmable gate arrays (FPGAs). This is a more rugged approach than a conventional microprocessor digital controller. FPGAs typically have higher radiation (rad) tolerance than both the microprocessor and memory required for a conventional digital controller. Furthermore, FPGAs can typically operate at higher speeds. (While speed is usually not an issue for motor controllers, it can be for other system controllers.) Other than motor power, only a 3.3-V digital power supply was used in the controller; no analog bias supplies were used. Since most of the circuit was implemented in the FPGA, no additional parts were needed other than the power transistors to drive the motor. The benefits that FPGAs provide over conventional designs-lower power and fewer parts-allow for smaller packaging and reduced weight and cost.

King, K. D.↗
NASA NTRS2004

Development of Electronic Load Controllers for Free-Piston Stirling Convertors Aided by Stirling Simulation Model

The free-piston Stirling convertor end-to-end modeling effort at the NASA Glenn Research Center has produced a software-based test bed in which free-piston Stirling convertors can be simulated and evaluated. The simulation model includes all the components of the convertor: the Stirling cycle engine, heat source, linear alternator, controller, and load. So far, it has been used in evaluating the performance of electronic controller designs. Three different controller design concepts were simulated using the model: 1) Controllers with parasitic direct current loading. 2) Controllers with parasitic alternating current loading. 3) Controllers that maintain a reference current. The free-piston Stirling convertor is an electromechanical device that operates at resonance. It is the function of the electronic load controller to ensure that the electrical load seen by the machine is always great enough to keep the amplitude of the piston and alternator oscillation at the rated value. This is done by regulating the load on the output bus. The controller monitors the instantaneous voltage, regulating it by switching loads called parasitic loads onto the bus whenever the bus voltage is too high and removing them whenever the voltage is too low. In the first type of controller, the monitor-ing and switching are done on the direct-current (dc) bus. In the second type, the alternating current bus is used. The model allows designers to test a controller concept before investing time in hardware. The simulation code used to develop the model also offers detailed models of digital and analog electronic components so that the resulting designs are realistic enough to translate directly into hardware circuits.

Regan, Timothy F.↗
NASA NTRS2014

A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

radiation hardened by design↗
NASA NTRS2001

Self-Timed Digital System Design

A timing and control strategy that can be used to realize synchronous systems with a level of performance that approaches that of asynchronous circuits or systems was developed in this work. This approach is based upon a single-phase synchronous circuit/system architecture with a variable period clock. The handshaking signals required for asynchronous self-timed circuits are not needed. Dynamic power supply current monitoring is used to generate the timing information, that is comparable to the completion signal found in self-timed circuits; this timing information is used to modify the circuit clock period.

Walker, Alvernon↗
NASA NTRSDate not supplied

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRSDate not supplied

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRS2023

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRS1969

Simple demodulator for telemetry phase- shift keyed subcarriers

Circuit, suitable for operation at high signal-to-noise ratio environments, recovers pulse-code modulated data from digital telemetry systems which use phase-shift keyed subcarrier techniques. This demodulator is easily constructed from microcircuit elements and may be applied where low-cost, relatively high-level signal systems are used.

Couvillon, L. A.↗
NASA NTRS1997

System-Level Integrated Circuit (SLIC) Technology Development for Phased Array Antenna Applications

This report documents the efforts and progress in developing a 'system-level' integrated circuit, or SLIC, for application in advanced phased array antenna systems. The SLIC combines radio-frequency (RF) microelectronics, digital and analog support circuitry, and photonic interfaces into a single micro-hybrid assembly. Together, these technologies provide not only the amplitude and phase control necessary for electronic beam steering in the phased array, but also add thermally-compensated automatic gain control, health and status feedback, bias regulation, and reduced interconnect complexity. All circuitry is integrated into a compact, multilayer structure configured for use as a two-by-four element phased array module, operating at 20 Gigahertz, using a Microwave High-Density Interconnect (MHDI) process. The resultant hardware is constructed without conventional wirebonds, maintains tight inter-element spacing, and leads toward low-cost mass production. The measured performances and development issues associated with both the two-by-four element module and the constituent elements are presented. Additionally, a section of the report describes alternative architectures and applications supported by the SLIC electronics. Test results show excellent yield and performance of RF circuitry and full automatic gain control for multiple, independent channels. Digital control function, while suffering from lower manufacturing yield, also proved successful.

Windyka, John A.↗
NASA NTRS2003

Low-Power Radio-Frequency SiGe Analog-to-Digital Converter

A low-power, radio-frequency analog-to-digital converter (RF-ADC) for soil moisture remote sensing was designed and fabricated. The RF-ADC is the fundamental component used in a direct-sampling digital radiometer, which is proposed to minimize the power dissipation and system complexity for synthetic thinned array radiometer. The circuit was implemented using 0.8 micron 35-GHz silicon germanium BiCMOS technology. The total power dissipation was 222 mW.

Thompson, Willie L, II↗
NASA NTRS2007

Thin, nearly wireless adaptive optical device

A thin, nearly wireless adaptive optical device capable of dynamically modulating the shape of a mirror in real time to compensate for atmospheric distortions and/or variations along an optical material is provided. The device includes an optical layer, a substrate, at least one electronic circuit layer with nearly wireless architecture, an array of actuators, power electronic switches, a reactive force element, and a digital controller. Actuators are aligned so that each axis of expansion and contraction intersects both substrate and reactive force element. Electronics layer with nearly wireless architecture, power electronic switches, and digital controller are provided within a thin-film substrate. The size and weight of the adaptive optical device is solely dominated by the size of the actuator elements rather than by the power distribution system.

Knowles, Gareth↗