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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 667 records · Page 37
All sourcesNASA NTRSDOE OSTI
DOE OSTI2021

Beamline Spectroscopy of Integrated Circuits With Hard X-Ray Transition Edge Sensors at the Advanced Photon Source

At Argonne National Laboratory, we are developing hard X-ray (2 to 20 keV) Transition Edge Sensor (TES) arrays for beamline science. The significantly improved energy resolution provided by superconducting detectors compared to semiconductor-based energy-dispersive detectors, but with better collection efficiency than wavelength-dispersive instruments, will enable greatly improved X-ray emission and absorption spectroscopic measurements. Additionally, a prototype instrument with 24 microwave-frequency multiplexed pixels is now in testing at the Advanced Photon Source (APS) 1-BM beamline. Initial measurements show an energy resolution ten times better (150 eV compared to < 15 eV) than the silicon-drift detectors currently available to APS beamline users, and in particular demonstrate the ability to resolve closely-spaced emission lines in samples containing multiple transition metal elements, such as integrated circuits. Comparing fluorescence spectra of integrated circuits measured with our TESs at the beamline to those measured with silicon detectors, we find emission lines and elements largely hidden (e.g. Hf alongside Cu) from a semiconductor-based detector but well resolved by a TES. This directly shows the strengths of TES-based instruments in fluorescence mapping.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2023

Measurements of DC SQUID Damping Effects on Superconducting Resonant Circuits

Here, we present experimental measurements of SQUID-induced damping effects on strongly coupled, lumped-element resonators in the 500kHz–1 MHz frequency range. While dc SQUIDs are commonly used for sensitive readout of electromagnetic signals such as in lumped-element axion dark matter searches, coupling a dc SQUID to a resonant circuit modifies the circuit's resonance frequency, quality factor, noise, and impedance. These parameters have a direct impact on the science reach of axion dark matter detectors, making it important to understand SQUID damping contributions. We describe a helium dip probe and two-stage SQUID readout scheme used to probe SQUID damping effects. Measurements from this setup inform the design and operation of both future test platforms as well as next-generation dark-matter experiments.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2022

Epoxy / Silicone Potting Material Removal for Greater Recovery of Circuit Boards

This report documents an exploratory research project, “Epoxy/Silicone Potting Material Removal for Greater Recovery of Circuit Boards,” that investigated micro abrasion and laser ablation as potential cost effective methods for removal of epoxy and silicone potting material from printed circuit boards (PCBs) to expose components for testing and repair. The ability to cost effectively remove such PCB potting materials will improve PCB repair, remanufacture, and reuse opportunities with potential for sizable reductions in material use, E-waste, and energy. Laser ablation was identified as a method potentially warranting further investigation, in particular for epoxy based potting materials.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
DOE OSTI2026

Fast, Controllable, and Modular Solid-State Circuit Breaker Design for Battery Management Systems

Electric power grid is experiencing a growing number of distributed and inertia-free generation resources. To facilitate the growing generation and load demands, and ensure stable operation, energy storage systems, especially behind-themeter-storage (BTMS), have emerged as a potential candidate. BTMS plays a vital role in the grid storage sector and supports high power charging for EVs. However, the potential of thermal runaway and associated safety concerns in the batteries can hamper their widespread adoption. In this work, we provide a solution for a fast and controllable discharge of a cell that was identified as a stressful/faulty, in the battery pack, and fast circuit breaking leveraging the Solid-State Circuit Breaker (SSCB) technology which provides active control over the cell connection as opposed to conventional passive solutions. Testing on the simulation platform successfully validated the concept, demonstrating its efficacy. Controlled discharge testing with 20Ah LiFePO4 Lithium Iron Phosphate (LFP) cells from 1C-10C current rate on the hardware prototype corroborated simulation results, demonstrating design feasibility and providing essential data for its performance and thermal characteristics, while also revealing limitations that inform areas for further optimization.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2021

Globally Optimizing QAOA Circuit Depth for Constrained Optimization Problems

We develop a global variable substitution method that reduces n-variable monomials in combinatorial optimization problems to equivalent instances with monomials in fewer variables. We apply this technique to 3-SAT and analyze the optimal quantum unitary circuit depth needed to solve the reduced problem using the quantum approximate optimization algorithm. For benchmark 3-SAT problems, we find that the upper bound of the unitary circuit depth is smaller when the problem is formulated as a product and uses the substitution method to decompose gates than when the problem is written in the linear formulation, which requires no decomposition.

3-SAT↗
NASA NTRS1967

Net-2 circuit analysis program

Circuit features, variational capabilities, input-output capabilities, and transient analysis of NET-2 circuit program

COMPUTER DESIGN↗
NASA NTRS1992

Toward Agent Programs with Circuit Semantics

New ideas are presented for computing and organizing actions for autonomous agents in dynamic environments-environments in which the agent's current situation cannot always be accurately discerned and in which the effects of actions cannot always be reliably predicted. The notion of 'circuit semantics' for programs based on 'teleo-reactive trees' is introduced. Program execution builds a combinational circuit which receives sensory inputs and controls actions. These formalisms embody a high degree of inherent conditionality and thus yield programs that are suitably reactive to their environments. At the same time, the actions computed by the programs are guided by the overall goals of the agent. The paper also speculates about how programs using these ideas could be automatically generated by artificial intelligence planning systems and adapted by learning methods.

ELECTRICAL CIRCUITS↗
NASA NTRS1996

Design and Analysis of Broad-Band Fixed-Tuned Submillimeter-Waveguide Multipliers using MMIC Style Circuit Topology

The design and analysis of varactor diode doubler, quadrupler and cascaded doubler circuits for 320 and 640 GHz have been completed. A new approach has been employed to produce a tunerless waveguide mount with a very flexible, frequency scaleable, MMIC style multiplier circuit. The concept, design, predicted performance and measurements on some of the constituent mount elements are presented.

varactor diode doubler MMIC style multiplier circu↗
NASA NTRS2012

Total Dose Effects on Bipolar Integrated Circuits at Low Temperature

Total dose damage in bipolar integrated circuits is investigated at low temperature, along with the temperature dependence of the electrical parameters of internal transistors. Bandgap narrowing causes the gain of npn transistors to decrease far more at low temperature compared to pnp transistors, due to the large difference in emitter doping concentration. When irradiations are done at temperatures of -140 deg C, no damage occurs until devices are warmed to temperatures above -50 deg C. After warm-up, subsequent cooling shows that damage is then present at low temperature. This can be explained by the very strong temperature dependence of dispersive transport in the continuous-time-random-walk model for hole transport. For linear integrated circuits, low temperature operation is affected by the strong temperature dependence of npn transistors along with the higher sensitivity of lateral and substrate pnp transistors to radiation damage.

linear integrated circuits↗
NASA NTRS2016

First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits

A separate submission to this conference reports that 4H-SiC Junction Field Effect Transistor (JFET) digital and analog Integrated Circuits (ICs) with two levels of metal interconnect have reproducibly demonstrated electrical operation at 500 C in excess of 1000 hours. While this progress expands the complexity and durability envelope of high temperature ICs, one important area for further technology maturation is the development of reasonably accurate and accessible computer-aided modeling and simulation tools for circuit design of these ICs. Towards this end, we report on development and verification of 25 C to 500 C SPICE simulation models of first order accuracy for this extreme-temperature durable 4H-SiC JFET IC technology. For maximum availability, the JFET IC modeling is implemented using the baseline-version SPICE NMOS LEVEL 1 model that is common to other variations of SPICE software and importantly includes the body-bias effect. The first-order accuracy of these device models is verified by direct comparison with measured experimental device characteristics.

JFET↗
NASA NTRS2018

Yearlong 500 C Operational Demonstration of Up-Scaled 4H-SiC JFET Integrated Circuits

This work describes recent progress in the design, processing, and testing of significantly up-scaled 500 C durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for over one year at 500 C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500 C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.

Silicon carbides↗
NASA NTRS1996

High Performance Low Cost Power Conditioning Subsystems Using Smart Power/ Power Integrated Circuits in Photovoltaic Power Systems

New technologies like Smart Power, and Power Integrated Circuits are the wave of the future in providing high performance low cost power conditioning subsystem (PCS)in small to large power applications. This paper discusses circuit designs using these devices that are suitable for PCS in photovoltaic and other industrial applications such as electrical appliances, instrumentation, AC motor drives, battery chargers, automobiles, telecommunications, UPS, and switch mode power supplies. It examines the cost of high volume production and current technological barriers asociated with the development of these technologies.

smart↗
NASA NTRS1999

Displacement Damage in Bipolar Linear Integrated Circuits

Although many different processes can be used to manufacture linear integrated circuits, the process that is used for most circuits is optimized for high voltage -- a total power supply voltage of about 40 V -- and low cost.

Bipolar↗
NASA NTRSDate not supplied

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗