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At least 649 records · Page 36

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NASA NTRS1986

Etching Silicon Films With Xenon Difluoride

Microscopic circuit structures prepared for probing. Xenon difluoride removes relatively large amounts of silicon from integratedcircuit or solar-cell structures while leaving SiO2, Si3N4, Al2O3, and other compounds intact. In Etching Apparatus, solid XeF2 sublimated in vacuum, then allowed to flow over sample at controlled rate and pressure. Wafer etched from back to expose SiO2 and Al layers for spectroscopic analysis of SiO2/Al interface. Using XeF2 technique, silicon wafer with oxide layer reduced in thickness from standard 300 micrometer to as little as 10 nanometer without adversely affecting oxide.

Hecht, M. H.↗

NASA NTRS1985

High purith low defect FZ silicon

The most common intrinsic defects in dislocation-free float zone (FZ) silicon crystals are the A- and B-type swirl defects. The mechanisms of their formation and annihilation have been extensively studied. Another type of defect in dislocation-free FZ crystals is referred to as a D-type defect. Concentrations of these defects can be minimized by optimizing the growth conditions, and the residual swirls can be reduced by the post-growth extrinsic gettering process. Czochralski (Cz) silicon wafers are known to exhibit higher resistance to slip and warpage due to thermal stress than do FZ wafers. The Cz crystals containing dislocations are more resistant to dislocation movement than dislocated FZ crystals because of the locking of dislocations by oxygen atoms present in the Cz crystals. Recently a transverse magnetic field was applied during the FZ growth of extrinsic silicon. Resultant flow patterns, as revealed by striation etching and spreading resistance in Ga-doped silicon crystals, indicate strong effects of the transverse magnetic field on the circulation within the melt. At fields of 5500 gauss, the fluid flow in the melt volume is so altered as to affect the morphology of the growing crystal.

Kimura, H.↗

NASA NTRS1985

Solar cell and I.C. aspects of ingot-to-slice mechanical processing

Intensive efforts have been put into the growth of silicon crystals to suit today's solar cell and integrated circuit requirements. Each step of processing the crystal must also receive concentrated attention to preserve the grown-in perfection and to provide a suitable device-ready wafer at reasonable cost. A comparison is made between solar cell and I.C. requirements on the mechanical processing of silicon from ingot to wafer. Specific defects are described that can ruin the slice or can possibly lead to device degradation. These include grinding cracks, saw exit chips, crow's-foot fractures, edge cracks, and handling scratches.

Dyer, L. D.↗

NASA NTRS1985

Reliability analysis

The objective was to search for and demonstrate approaches and concepts for fast wafer probe tests of mechanisms affecting the reliability of MOS technology and, based on these, develop and optimize test chips and test procedures. Progress is reported on four important wafer-level reliability problems: gate-oxide radiation hardness; hot-electron effects; time-dependence dielectric breakdown; and electromigration.

Source record↗

NASA NTRS1986

Lithium counterdoped silicon solar cell

The resistance to radiation damage of an n(+)p boron doped silicon solar cell is improved by lithium counterdoping. Even though lithium is an n-dopant in silicon, the lithium is introduced in small enough quantities so that the cell base remains p-type. The lithium is introduced into the solar cell wafer by implantation of lithium ions whose energy is about 50 keV. After this lithium implantation, the wafer is annealed in a nitrogen atmosphere at 375 C for two hours.

Weinberg, I.↗

NASA NTRS1986

Cross-contact chain

A system is provided for use with wafers that include multiple integrated circuits that include two conductive layers in contact at multiple interfaces. Contact chains are formed beside the integrated circuits, each contact chain formed of the same two layers as the circuits, in the form of conductive segments alternating between the upper and lower layers and with the ends of the segments connected in series through interfaces. A current source passes a current through the series-connected segments, by way of a pair of current tabs connected to opposite ends of the series of segments. While the current flows, voltage measurements are taken between each of a plurality of pairs of voltage tabs, the two tabs of each pair connected to opposite ends of an interface that lies along the series-connected segments. A plot of interface conductances on normal probability chart enables prediction of the yield of good integrated circuits from the wafer.

Lieneweg, U.↗

NASA NTRS1987

Intrusions in the active layer of channeled-substrate-planar laser diodes

Channeled-substrate-planar laser diodes from various wafers were observed to develop a node or dark spot in their near-field patterns after failure during lifetesting. 'Node' devices from each wafer were angle-lapped and stained in an attempt to uncover a physical mechanism for this common failure symptom. Optical microscopic examination of the beveled cross sections revealed that an intrusion, in the form of a spike at the tip of the zinc diffusion front, had penetrated into the active layer of these diodes. The node observed in the near-field pattern appears to be in a position correspondig to the location of the spike in the active region. In addition, cathodoluminescence measurements on other 'node' diodes revealed a dark line region approximately 2-micron-wide running parallel to and in the middle of the 5-micron contact stripe. It is believed that this dark line region is representative of an area of nonradiative recombination which occurs in the portion of the active layer containing the intrusion.

Slavin, S. E.↗

NASA NTRS1988

Micromachining Of Silicon

Etching rates of alloys and heavily-doped semiconductor materials significantly higher than lightly doped semiconductor if proper etching system used. Selectivity used to etch regions of semiconductor preferentially while not etching other unmasked regions. When selective etching used with laser-induced-diffusion techniques, possible to make structures that cannot be made at present. Possible to produce well-defined structures in and through wafer while not damaging existing structures on wafer.

Dickman, John E.↗

NASA NTRS1988

Forming n/p Junctions With An Excimer Laser

Compact equipment yields high-quality solar cells. Computer controls pulses of excimer laser and movement of silcon wafer. Mirrors direct laser beam to wafer. Lenses focus beam to small spot on surface. Process suitable for silicon made by dendritic-web-growth process.

Alexander, Paul, Jr.↗

NASA NTRS1987

Gigarad-tolerant power switches and memory elements

A new class of silicon devices operating without p-n junctions has been studied for radiation hardness. The electric field in these devices is uniform over most of the device, thus causing high-voltage breakdown to increase with electrode spacing. Deep acceptor levels are created in the silicon by diffusing gold atoms into the lattice, or by electron radiation. These acceptor levels, near the center of the band gap, trap out electrons so that the low resistivity of the n-type doped wafer can be raised to intrinsic resistivity. Switching between a high-resistivity state at low currents and a low-resistivity state at high currents occurs at a definite threshold voltage, exhibiting characteristics similar to silicon-controlled rectifiers. Compensating 0.1 ohm-meter (10 ohm-cm) silicon wafers requires electron fluxes of 10 to the 23rd electrons per square meter (10 to the 19th electrons per square centimeter). Experiments demonstrating gamma tolerance to 1 Gigarad(Si) are described. Calculations for maximum tolerable neutron fluence are shown, and a phenomenological explanation for these results is presented.

Joyner, W. T.↗

NASA NTRS1989

Roughening Surfaces Of Solar Cells

Proposed treatment involving bombardment by ions gives silicon solar cells rough surfaces and increases amount of light absorbed by cells. First step of treatment, wafer of single-crystal silicon held at temperature of 70 degree C or higher while bombarded with argon or hydrogen ions at kinetic energies between 100 and 2,000 eV. This high dose produces damaged layer on surface, consisting of outer polycrystalline sublayer and underlying sublayer containing extended defects. Bombarded wafer then etched chemically. Photovoltaic conversion efficiency increases with number of reflections at surface of silicon cell because large part of light absorbed at each reflection. Deeply textured surface provides opportunities for multiple reflections.

Singh, Ranbir↗

NASA NTRS1988

Optical Backplane Interconnect Technology (OBIT)

We describe and analyze a novel approach to implementing an Optical Backplane Interconnect Technology (OBIT) that is capable of optically connecting any row of a 32x32 backplane array to any row of a second 32x32 array. Each backplane array is formed monolithically on a wafer. The technology is based on the use of Grating Surface Emitting (GSE) waveguides formed on a wafer containing quantum-well and separate confinement waveguide layers. These layers are used for transverse guiding, gain, modulation, detection, and for the formation of wavelength tunable distributed-Bragg reflector lasers. The required surface structures are formed photolithographically. The GSE waveguides act as efficient antennae that radiate light at angles selected by tuning the wavelength of the lasers. The same waveguides may be used as the receiving antennae when the array is used in the receiving mode. Thus, wavelength tuning is used to direct each row of the transmitting array to the desired row of the receiving array. In summary: The optical backplane array will have the following characteristics: Any row of a 32x32 GSE array may be optically connected to any row of a second 32x32 array. Only one switch decision is required to switch 32 parallel connections to any one of 32 positions. Each monolithic array can be used as both transmitter and receiver by switching the bias on the quantum-well switch-detectors. Separate transmitting and receiving structures could be provided for duplex operation. For a bit error rate of 10 sup 9 at 100-MHz data rate, a required laser power of 12 mW is calculated based on an estimated total optical loss of 40 dB.

Hammer, J. M.↗

NASA NTRS1989

External electro-optic probing of millimeter-wave integrated circuits

An external, noncontact electro-optic measurement system, designed to operate at the wafer level with conventional wafer probing equipment and without any special circuit preparation, has been developed. Measurements have demonstrated the system's ability to probe continuous and pulsed signals on microwave integrated circuits on arbitrary substrates with excellent spatial resolution. Experimental measurements on a variety of digital and analog circuits, including a GaAs selectively-doped heterostructure transistor prescaler, an NMOS silicon multiplexer, and a GaAs power amplifier MMIC are reported.

Whitaker, J. F.↗

NASA NTRS1989

Solid state photomultiplier for astronomy, phase 2

Epitaxial layers with varying donor concentration profiles were grown on silicon substrate wafers using chemical vapor deposition (CVD) techniques, and solid state photomultiplier (SSPM) devices were fabricated from the wafers. Representative detectors were tested in a low background photon flux, low temperature environment to determine the device characteristics for comparison to NASA goals for astronomical applications. The SSPM temperatures varied between 6 and 11 K with background fluxes in the range from less than 5 x 10 to the 6th power to 10 to the 13th power photons/square cm per second at wavelengths of 3.2 and 20 cm. Measured parameters included quantum efficiency, dark count rate and bias current. Temperature for optimal performance is 10 K, the highest ever obtained for SSPMs. The devices exhibit a combination of the lowest dark current and highest quantum efficiency yet achieved. Experimental data were reduced, analyzed and used to generate recommendations for future studies. The background and present status of the microscopic theory of SSPM operation were reviewed and summarized. Present emphasis is on modeling of the avalanche process which is the basis for SSPM operation. Approaches to the solution of the Boltzmann transport equation are described and the treatment of electron scattering mechanisms is presented. The microscopic single-electron transport theory is ready to be implemented for large-scale computations.

Besser, P. J.↗

NASA NTRS1988

Integrated circuit reliability testing

A technique is described for use in determining the reliability of microscopic conductors deposited on an uneven surface of an integrated circuit device. A wafer containing integrated circuit chips is formed with a test area having regions of different heights. At the time the conductors are formed on the chip areas of the wafer, an elongated serpentine assay conductor is deposited on the test area so the assay conductor extends over multiple steps between regions of different heights. Also, a first test conductor is deposited in the test area upon a uniform region of first height, and a second test conductor is deposited in the test area upon a uniform region of second height. The occurrence of high resistances at the steps between regions of different height is indicated by deriving the measured length of the serpentine conductor using the resistance measured between the ends of the serpentine conductor, and comparing that to the design length of the serpentine conductor. The percentage by which the measured length exceeds the design length, at which the integrated circuit will be discarded, depends on the required reliability of the integrated circuit.

Buehler, Martin G.↗

NASA NTRS1989

Fabrication of n(+)/p InP solar cells on silicon substrates

InP films were grown by MOCVD on Si GaAs substrates (as well as on InP substrates, included as controls), and were used to fabricate solar cells, using the Spitzer et al. (1987) technique. Contact to the substrate was made with Al-Ti-Pd-Ag to the Si wafers and with Au-Zn alloy to the GaAs wafers, while contract to the front was made with Cr-Au-Ag. Air mass zero efficiencies were found to be 7.1 percent for Si-substrate cells and 9.4 percent for GaAs-substrate cells.

Keavney, C. J.↗

NASA NTRS1989

External electro-optic probing of millimeter-wave integrated circuits

Whitaker, J. F.↗

NASA NTRS1990

Integrated Grating Spectrometer

Proposed integrated grating spectrometer made in waveguide layer on silicon wafer. Occupies area of about 2 centimeters to 2nd power on wafer 0.4 mm thick. Operates in visible spectrum (wavelengths of 400 to 700 nm) and blazed to diffract in first order. Array of integrated grating spectrometers performs spectral analysis of picture elements along line. Optical fiber couples light from each picture element into separate integrated spectrometer. Technique enables continous independent variation, along grating, of pitch, curvature, and blaze angle. Grating designed to have large numerical aperture, zero aberration at two selected wavelengths, and very low aberration at intermediate wavelengths.

Lang, Robert J.↗