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Shift register time-shared in proposed error-correcting code for tape-storage systems. Error-correcting code logic for blocks of 256-bit data words implemented by 14-stage-time-shared shift register, two 4,096bit RAM's and logic gates. Encoding and decoding logic implement generator polynomial that defines error-correcting code, and error correction based on algorithm also implemented by logic.
Improved method of rounding off (truncation of least-significant bits) in integer processing of data devised. Provides for reduction, to extremely low value, of numerical bias otherwise generated by accumulation of truncation errors from many arithmetic operations. Devised for use in integer signal processing, in which rescaling and truncation usually performed to reduce number of bits, which typically builds up in sequence of operations. Essence of method to alternate direction of roundoff (plus, then minus) on alternate occurrences of truncated values contributing to bias.
Large-scale integrated circuit generates and checks parity of four eight-bit registers. In addition, circuit will indicate by output signal whether parity error exists. Circuit can also generate or check parity of words up to 32 bits. This is done by making appropriate internal wiring connections on the large-scale integrated chip.
The desire to assess the reliability of emerging scaled microelectronics technologies through faster reliability trials and more accurate acceleration models is the precursor for further research and experimentation in this relevant field. The effect of semiconductor scaling on microelectronics product reliability is an important aspect to the high reliability application user. From the perspective of a customer or user, who in many cases must deal with very limited, if any, manufacturer's reliability data to assess the product for a highly-reliable application, product-level testing is critical in the characterization and reliability assessment of advanced nanometer semiconductor scaling effects on microelectronics reliability. A methodology on how to accomplish this and techniques for deriving the expected product-level reliability on commercial memory products are provided.Competing mechanism theory and the multiple failure mechanism model are applied to the experimental results of scaled SDRAM products. Accelerated stress testing at multiple conditions is applied at the product level of several scaled memory products to assess the performance degradation and product reliability. Acceleration models are derived for each case. For several scaled SDRAM products, retention time degradation is studied and two distinct soft error populations are observed with each technology generation: early breakdown, characterized by randomly distributed weak bits with Weibull slope (beta)=1, and a main population breakdown with an increasing failure rate. Retention time soft error rates are calculated and a multiple failure mechanism acceleration model with parameters is derived for each technology. Defect densities are calculated and reflect a decreasing trend in the percentage of random defective bits for each successive product generation. A normalized soft error failure rate of the memory data retention time in FIT/Gb and FIT/cm2 for several scaled SDRAM generations is presented revealing a power relationship. General models describing the soft error rates across scaled product generations are presented. The analysis methodology may be applied to other scaled microelectronic products and their key parameters.
A technique was developed to provide a reconfigurable high-precision micro - wave electrical phase delay for resonators and phase shifters. The invention employs multiple branches of transmission lines with open-ended or ground-ended terminations as configurable bits or digits. This technique minimizes the errors due to limited precision of switching devices. In addition, the proposed linear analytical approach significantly produces a much simpler design than that of other prior inventions at the time of this reporting. Microwave components such as filters, phase delay elements, or resonators require a method that can accurately adjust their frequency responses. Most tuning techniques offer very wide frequency tuning range; however, it is often difficult and expensive to tune their response in a very narrow operating frequency, especially when the tuning element reaches its minimum discrete step due to fabrication tolerances. The problem becomes worse as the operating frequency is in mm-wave frequency range (>26 GHz). The electrical tuning sensitivity of a microwave line is dependent on the position of the tuning element with respect to the reference termination. By placing this tuning element away from this reference with the main transmission line connecting the two elements together the sensitivity of the tuning element can change significantly. This concept can be used in the system that requires multiple tuning sensitivities. In this case, multiple tuning branches are superimposed in the main transmission line. The proposed invention allows the transmission-line electrical length to be accurately programmed using switching elements that have limited accuracy. The invention consists of multiple branches of transmission lines connected to discrete switching devices with open-ended terminations. They are used as discrete tuning elements. These elements are connected to the main microwave transmission line and are separated by a well-defined electrical degree spacing. Each branch is programmed to have different electrical degree sensitivity, such as a combination of discrete steps in each branch, which results in a reflective line with a unique effective phase response. To reduce the number of switching devices, it is desirable to program the devices in binary configuration where each branch represents one bit in the base-2 number system. This invention allows the transmission line electrical length to be tuned precisely with customizable sensitivity based on the known sensitivity of the base tuning circuit. The tuning resolution is dependent on the distance among tuning branches.
Conventional memory technologies currently employed in aerospace applications contribute at least fifty percent to system unreliability (where the system includes CPU, I/O and memory). A fault tolerant memory performs both error correction and memory replacement at the bit plane level. To determine the effects of system design of using a fault tolerant memory in space applications, analysis was performed to determine tradeable hardware configurations that meet the reliability goals of each program. The candidate configurations, which included redundant elements of the computer system with both conventional and fault tolerant memories, were then traded in terms of selection criteria of cost, weight, volume, and power. These trade studies demonstrated that a fault tolerant memory provided significant advantages in terms of cost, weight, and volume. The memory selected for this analysis was a recently developed five fault tolerant memory.
Arithmetic technique facilitates high-speed rounding of 2's complement binary data. Conventional rounding of 2's complement numbers presents problems in high-speed digital circuits. Proposed technique consists of truncating K + 1 bits then attaching bit in least significant position. Mean output error is zero, eliminating introducing voltage offset at input.
The next era of space exploration will generate extraordinary volumes of image data, and management of this image data is beyond current technical capabilities. We propose a strategy for coding visual information that exploits the known properties of early human vision. This Perceptual Components Architecture codes images and image sequences in terms of discrete samples from limited bands of color, spatial frequency, orientation, and temporal frequency. This spatiotemporal pyramid offers efficiency (low bit rate), variable resolution, device independence, error-tolerance, and extensibility.
TESS data release 30 (DR30) provides reprocessed data products of Sector 14 to 19. The updated data products were generated using version 4.0 of the science processing pipeline and conform to the final set of data anomaly flags defined over the last two years of TESS data analysis and pipeline development. Data release 33 (DR33) corresponds to a multisector search for transiting planets in the same reprocessed data. A detailed description of the changes in the data products in DR30 and DR33 is discussed in§2, and a brief list of changes is summarized here: The timestamps for 2 minute cadence and FFI data are more accurate. The differences between reprocessed data and previous data releases are less than 2.0 seconds in all cases. Photometric apertures were increased in size for targets with T mag<11. Three new Data Anomaly Flags were added to mitigate the effects of scattered light:–Cadences with strong scattered light signals or saturation effects that corrupt the calibration data are flagged and removed from analysis (bit 15, value 16384, “Bad Calibration Exclude”).–Scattered light data anomaly flags are customized for each target, and flagged automatically based on the local background level (bit 13, value 4096, ”Scattered light flag”).–Cadences with insufficient targets to derive cotrending basis vectors are flagged and the PDCSAP FLUX light curves are set to NULL at these times (bit 16, value 32768, “Insufficient Targets for Error Correction Exclude”). The planet search of the reprocessed light curves produced a different set of TCEs from the original processed data. Although there is a high degree of overlap between the original and reprocessed data (∼83% of targets produced TCEs in common), new TCEs were produced in DR30 and not every TCE from previous data releases was recovered. The same is true of the multisector search results from DR33 compared to DR28
A single-burst-error correction system is described for data stored in the UNICON laser memory. In the proposed system, a long fire code with code length n greater than 16,768 bits was used as an outer code to augment an existing inner shorter fire code for burst error corrections. The inner fire code is a (80,64) code shortened from the (630,614) code, and it is used to correct a single-burst-error on a per-word basis with burst length b less than or equal to 6. The outer code, with b less than or equal to 12, would be used to correct a single-burst-error on a per-page basis, where a page consists of 512 32-bit words. In the proposed system, the encoding and error detection processes are implemented by hardware. A minicomputer, currently used as a UNICON memory management processor, is used on a time-demanding basis for error correction. Based upon existing error statistics, this combination of an inner code and an outer code would enable the UNICON system to obtain a very low error rate in spite of flaws affecting the recorded data.
A method has been developed of computing bounds on the performance of a code comprised of two linear binary codes generated by two encoders serially concatenated through an interleaver. Originally intended for use in evaluating the performances of some codes proposed for deep-space communication links, the method can also be used in evaluating the performances of short-block-length codes in other applications. The method applies, more specifically, to a communication system in which following processes take place: At the transmitter, the original binary information that one seeks to transmit is first processed by an encoder into an outer code (Co) characterized by, among other things, a pair of numbers (n,k), where n (n > k)is the total number of code bits associated with k information bits and n k bits are used for correcting or at least detecting errors. Next, the outer code is processed through either a block or a convolutional interleaver. In the block interleaver, the words of the outer code are processed in blocks of I words. In the convolutional interleaver, the interleaving operation is performed bit-wise in N rows with delays that are multiples of B bits. The output of the interleaver is processed through a second encoder to obtain an inner code (Ci) characterized by (ni,ki). The output of the inner code is transmitted over an additive-white-Gaussian- noise channel characterized by a symbol signal-to-noise ratio (SNR) Es/No and a bit SNR Eb/No. At the receiver, an inner decoder generates estimates of bits. Depending on whether a block or a convolutional interleaver is used at the transmitter, the sequence of estimated bits is processed through a block or a convolutional de-interleaver, respectively, to obtain estimates of code words. Then the estimates of the code words are processed through an outer decoder, which generates estimates of the original information along with flags indicating which estimates are presumed to be correct and which are found to be erroneous. From the perspective of the present method, the topic of major interest is the performance of the communication system as quantified in the word-error rate and the undetected-error rate as functions of the SNRs and the total latency of the interleaver and inner code. The method is embodied in equations that describe bounds on these functions. Throughout the derivation of the equations that embody the method, it is assumed that the decoder for the outer code corrects any error pattern of t or fewer errors, detects any error pattern of s or fewer errors, may detect some error patterns of more than s errors, and does not correct any patterns of more than t errors. Because a mathematically complete description of the equations that embody the method and of the derivation of the equations would greatly exceed the space available for this article, it must suffice to summarize by reporting that the derivation includes consideration of several complex issues, including relationships between latency and memory requirements for block and convolutional codes, burst error statistics, enumeration of error-event intersections, and effects of different interleaving depths. In a demonstration, the method was used to calculate bounds on the performances of several communication systems, each based on serial concatenation of a (63,56) expurgated Hamming code with a convolutional inner code through a convolutional interleaver. The bounds calculated by use of the method were compared with results of numerical simulations of performances of the systems to show the regions where the bounds are tight (see figure).
A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. For example, some 256K-bit dynamic random access memories are organized as 32K x 8 bit-bytes. Byte-oriented codes such as Reed Solomon (RS) codes provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. Some special high speed decoding techniques for extended single and double error correcting RS codes. These techniques are designed to find the error locations and the error values directly from the syndrome without having to form the error locator polynomial and solve for its roots.
Encoding algorithms generate a 32 x 64-bit matrix Reed-Muller code from a 6-bit orthogonal code-word. This increases error-free reception by a high rate telemetry channel under adverse signal noise with minimal use of additional hardware.
The design and operation of a quad redundant data terminal and a multiplexer/demultiplexer (MDU) is described. The most unique feature is the design of the quad redundant data terminal. This is one of the few designs where the unit is fail/op, fail/op, fail/safe. Laboratory tests confirm that the unit will operate satisfactorily with the failure of three out of four channels. Although the design utilizes state-of-the-art technology, the waveform error checks, the voting techniques, and the parity bit checks are believed to be used in unique configurations. Correct word selection routines are also novel. The MDU design, while not redundant, utilizes, the latest state-of-the-art advantages of light coupler and interested amplifiers. Much of the technology employed was an evolution of prior NASA contracts related to the Addressable Time Division Data System. A good example of the earlier technology development was the development of a low level analog multiplexer, a high level analog multiplexer, and a digital multiplexer. A list of all drawings is included for reference and all schematic, block and timing diagrams are incorporated.
The design and operation of a quad redundant data terminal and a multiplexer/demultiplexer (MDU) design are described. The most unique feature is the design of the quad redundant data terminal. This is one of the few designs where the unit is fail/op, fail/op, fail/safe. Laboratory tests confirm that the unit will operate satisfactorily with the failure of three out of four channels. Although the design utilizes state-of-the-art technology. The waveform error checks, the voting techniques, and the parity bit checks are believed to be used in unique configurations. Correct word selection routines are also novel, if not unique. The MDU design, while not redundant, utilizes, the latest state-of-the-art advantages of light couplers and integrated circuit amplifiers.
A computer program is described for the calculation of the zeroes of the associated Legendre functions, Pnm, and their derivatives, for the calculation of the extrema of Pnm and also the integral between pairs of successive zeroes. The program has been run for all n,m from (0,0) to (20,20) and selected cases beyond that for n up to 40. Up to (20,20), the program (written in double precision) retains nearly full accuracy, and indications are that up to (40,40) there is still sufficient precision (4-5 decimal digits for a 54-bit mantissa) for estimation of various bounds and errors involved in geopotential modelling, the purpose for which the program was written.
The encoding of video signals using the Song Adaptive Delta Modulator (Song ADM) is discussed. The video signals are characterized as a sequence of pulses having arbitrary height and width. Although the ADM is suited to tracking signals having fast rise times, it was found that the DM algorithm (which permits an exponential rise for estimating an input step) results in a large overshoot and an underdamped response to the step. An overshoot suppression algorithm which significantly reduces the ringing while not affecting the rise time is presented along with formuli for the rise time and the settling time. Channel errors and their effect on the DM encoded bit stream were investigated.
'Second-order quantizers' are introduced which can be used for implementing recursive digital filters with practically no roundoff errors or limit-cycle oscillations. Based on the idea of changing the transfer function used to compute roundoff errors, these quantizers save the low-order bits to correct the product at future iterations. For several pole locations, this can be done with a minimal amount of extra hardware.