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At least 649 records · Page 36

Low-voltage and hysteresis-free organic thin-film transistors employing solution-processed hybrid bilayer gate dielectrics

This study presents a promising approach to realize low-voltage (<3 V) organic thin-film transistors (OTFTs) exhibiting improved electrical and optical stability. Such device performance results from the use of solution-processed hybrid bilayer gate dielectrics consisting of zirconium dioxide (high-k dielectric) and amorphous fluoropolymer, CYTOP{sup ®} (low-k dielectric). Employing a very thin amorphous fluoropolymer film reduces interfacial defect-states by repelling water molecules and other aqueous chemicals from an organic semiconductor active layer due to the hydrophobic surface-property. The chemically clean interface, stemming from decrease in density of trap states improves all the key device properties such as field-effect mobility, threshold voltage, and sub-threshold swing. Furthermore, degradation by electrical bias-stress and photo-induced hysteresis were suppressed in OTFTs employing hybrid bilayer gate dielectrics.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Impact ionization in N-polar AlGaN/GaN high electron mobility transistors

The existence of impact ionization as one of the open questions for GaN device reliability was studied in N-polar AlGaN/GaN high electron mobility transistors. Electroluminescence (EL) imaging and spectroscopy from underneath the device gate contact revealed the presence of hot electrons in excess of the GaN bandgap energy even at moderate on-state bias conditions, enabling impact ionization with hole currents up to several hundreds of pA/mm. The detection of high energy luminescence from hot electrons demonstrates that EL analysis is a highly sensitive tool to study degradation mechanisms in GaN devices.

36 MATERIALS SCIENCE↗

Fabrication and characterization of junctionless carbon nanotube field effect transistor for cholesterol detection

We have reported fabrication and characterization of polyaniline (PANI)/zinc oxide (ZnO) membrane-based junctionless carbon nanotube field effect transistor deposited on indium tin oxide glass plate for the detection of cholesterol (0.5–22.2 mM). Cholesterol oxidase (ChOx) has been immobilized on the PANI/ZnO membrane by physical adsorption technique. Electrical response has been recorded using digital multimeter (Agilent 3458A) in the presence of phosphate buffer saline of 50 mM, pH 7.0, and 0.9% NaCl contained in a glass pot. The results of response studies for cholesterol reveal linearity as 0.5–16.6 mM and improved sensitivity of 60 mV/decade in good agreement with Nernstian limit ∼59.2 mV/decade. The life time of this sensor has been found up to 5 months and response time of 1 s. The limit of detection with regression coefficient (r) ∼ 0.998 and Michaelis-Menten constant (K{sub m}) were found to be ∼0.25 and 1.4 mM, respectively, indicating high affinity of ChOx to cholesterol. The results obtained in this work show negligible interference with glucose and urea.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Reduced thermal resistance in AlGaN/GaN multi-mesa-channel high electron mobility transistors

Dramatic reduction of thermal resistance was achieved in AlGaN/GaN Multi-Mesa-Channel (MMC) high electron mobility transistors (HEMTs) on sapphire substrates. Compared with the conventional planar device, the MMC HEMT exhibits much less negative slope of the I{sub D}-V{sub DS} curves at high V{sub DS} regime, indicating less self-heating. Using a method proposed by Menozzi and co-workers, we obtained a thermal resistance of 4.8 K-mm/W at ambient temperature of ∼350 K and power dissipation of ∼9 W/mm. This value compares well to 4.1 K-mm/W, which is the thermal resistance of AlGaN/GaN HEMTs on expensive single crystal diamond substrates and the lowest reported value in literature.

36 MATERIALS SCIENCE↗

High-performance chemical-bath deposited CdS thin-film transistors with ZrO{sub 2} gate dielectric

We demonstrate high performance chemical bath deposited CdS thin-film transistors (TFTs) using atomic layer deposited ZrO{sub 2} based high-k gate dielectric material. Our unique way of isolation of the CdS-based TFTs devices yielded significantly low leakage current as well as remarkable lower operating voltages (<5 V) which is four times smaller than the devices reported on CdS-based TFTs using SiO{sub 2} gate dielectric. Upon thermal annealing, the devices demonstrate even higher performance, including μ{sub FE} exceeding 4 ± 0.2 cm{sup 2} V{sup −1}S{sup −1}, threshold voltage V{sub T} of 3.8 V, and I{sub on-off} of 10{sup 4}–10{sup 5}, which hold much promise for applications in future electronic and optical devices.

36 MATERIALS SCIENCE↗

Influence of anharmonic phonon decay on self-heating in Si nanowire transistors

Anharmonic phonon-phonon scattering is incorporated into an electro-thermal quantum transport approach based on the nonequilibrium Green's function formalism. Electron-phonon and phonon-phonon interactions are taken into account through scattering self-energies solved in the self-consistent Born approximation. While studying self-heating effects in ultra-scaled Si nanowire transistors, it is found that the phonon decay process softens the artificial accumulation of high energy phonons caused by electron relaxations close to the drain region. This leads to an increase of the device current in the ON-state and a reduction of the effective lattice temperature.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Proposal for a phase-coherent thermoelectric transistor

Identifying materials and devices which offer efficient thermoelectric effects at low temperature is a major obstacle for the development of thermal management strategies for low-temperature electronic systems. Superconductors cannot offer a solution since their near perfect electron-hole symmetry leads to a negligible thermoelectric response; however, here we demonstrate theoretically a superconducting thermoelectric transistor which offers unparalleled figures of merit of up to ∼45 and Seebeck coefficients as large as a few mV/K at sub-Kelvin temperatures. The device is also phase-tunable meaning its thermoelectric response for power generation can be precisely controlled with a small magnetic field. Our concept is based on a superconductor-normal metal-superconductor interferometer in which the normal metal weak-link is tunnel coupled to a ferromagnetic insulator and a Zeeman split superconductor. Upon application of an external magnetic flux, the interferometer enables phase-coherent manipulation of thermoelectric properties whilst offering efficiencies which approach the Carnot limit.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Investigation of trap properties in high-k/metal gate p-type metal-oxide-semiconductor field-effect-transistors with aluminum ion implantation using random telegraph noise analysis

In this study, the impact of aluminum ion implantation (Al I/I) on random telegraph noise (RTN) in high-k/metal gate (HK/MG) p-type metal-oxide-semiconductor field-effect-transistors (pMOSFETs) was investigated. The trap parameters of HK/MG pMOSFETs with Al I/I, such as trap energy level, capture time and emission time, activation energies for capture and emission, and trap location in the gate dielectric, were determined. The configuration coordinate diagram was also established. It was observed that the implanted Al could fill defects and form a thin Al{sub 2}O{sub 3} layer and thus increase the tunneling barrier height for holes. It was also observed that the trap position in the Al I/I samples was lower due to the Al I/I-induced dipole at the HfO{sub 2}/SiO{sub 2} interface.

36 MATERIALS SCIENCE↗

Effects of threading dislocations on drain current dispersion and slow transients in unpassivated AlGaN/GaN/Si heterostructure field-effect transistors

Current transient analysis combined with response to pulsed bias drives have been used to explore the possibilities of threading dislocations affecting the current dispersion characteristics of AlGaN/GaN heterostructure field-effect transistors (HFETs). A growth strategy is developed to modulate the dislocation density among the heterostructures grown on silicon by plasma-assisted molecular-beam epitaxy. Slow pulsed I-V measurements show severe compressions and appear to be significantly dependent on the threading dislocation density. By analyzing the corresponding slow detrapping process, a deep-level trap with emission time constant in the order of seconds was identified as the cause. Among the specimens, both in the epilayers and at the surface, the number of dislocations was found to have a notable influence on the spatial distribution of deep-level trap density. The observations confirm that the commonly observed degraded frequency performance among AlGaN/GaN HFETs in the form of DC-radio frequency dispersions can at least partly be correlated with threading dislocation density.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Probing channel temperature profiles in Al{sub x}Ga{sub 1−x}N/GaN high electron mobility transistors on 200 mm diameter Si(111) by optical spectroscopy

Using micro-Raman and photoluminescence (PL) techniques, the channel temperature profile is probed in Al{sub x}Ga{sub 1-x}N/GaN high electron mobility transistors (HEMTs) fabricated on a 200 mm diameter Si(111) substrate. In particular, RuO{sub x}-based gate is used due to the semitransparent nature to the optical excitation wavelengths, thus allowing much accurate thermal investigations underneath the gate. To determine the channel temperature profile in devices subjected to different electrical bias voltages, the GaN band-edge PL peak shift calibration with respect to temperature is used. PL analyses show a maximum channel temperature up to 435 K underneath the gate edge between gate and drain, where the estimated thermal resistance in such a HEMT structure is about 13.7 KmmW{sup −1} at a power dissipation of ∼10 W/mm. The temperature profiles from micro-Raman measurements are also addressed from the E{sub 2}-high optical phonon peak shift of GaN, and this method also probes the temperature-induced peak shifts of optical phonon from Si thus showing the nature of thermal characteristics at the AlN/Si substrate interface.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Advantages of flattened electrode in bottom contact single-walled carbon nanotube field-effect transistor

We fabricated single-walled carbon nanotube (SWNT) field-effect transistor (FET) devices on flattened electrodes, in which there are no height difference between metal electrodes and the substrate. SWNT-FET fabricated using bottom contact technique have some advantages, such that the SWNTs are free from electron irradiation, have direct contact with the desired metal electrodes, and can be functionalized before or after deposition. However, the SWNTs can be bent at the contact point with the metal electrodes leading to a different electrical characteristic of the devices. The number of SWNT direct junctions in short channel length devices is drastically increased by the use of flattened electrodes due to strong attractive interaction between SWNT and the substrate. The flattened electrodes show a better balance between their hole and electron mobility compared to that of the non-flattened electrodes, that is, ambipolar FET characteristic. It is considered that bending of the SWNTs in the non-flattened electrode devices results in a higher Schottky barrier for the electrons.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

Strain characterization of fin-shaped field effect transistors with SiGe stressors using nanobeam electron diffraction

This study undertook strain analysis on fin-shaped field effect transistor structures with epitaxial Si{sub 1−x}Ge{sub x} stressors, using nano-beam electron diffraction and finite elements method. Combining the two methods disclosed dynamic strain distribution in the source/drain and channel region of the fin structure, and the effects of dimensional factors such as the stressor thickness and fin width, offering valuable information for device design.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Large area graphene ion sensitive field effect transistors with tantalum pentoxide sensing layers for pH measurement at the Nernstian limit

We have fabricated and characterized large area graphene ion sensitive field effect transistors (ISFETs) with tantalum pentoxide sensing layers and demonstrated pH sensitivities approaching the Nernstian limit. Low temperature atomic layer deposition was used to deposit tantalum pentoxide atop large area graphene ISFETs. The charge neutrality point of graphene, inferred from quantum capacitance or channel conductance, was used to monitor surface potential in the presence of an electrolyte with varying pH. Bare graphene ISFETs exhibit negligible response, while graphene ISFETs with tantalum pentoxide sensing layers show increased sensitivity reaching up to 55 mV/pH over pH 3 through pH 8. Applying the Bergveld model, which accounts for site binding and a Guoy-Chapman-Stern picture of the surface-electrolyte interface, the increased pH sensitivity can be attributed to an increased buffer capacity reaching up to 10{sup 14} sites/cm{sup 2}. ISFET response was found to be stable to better than 0.05 pH units over the course of two weeks.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Assessment of field-induced quantum confinement in heterogate germanium electron–hole bilayer tunnel field-effect transistor

The analysis of quantum mechanical confinement in recent germanium electron–hole bilayer tunnel field-effect transistors has been shown to substantially affect the band-to-band tunneling (BTBT) mechanism between electron and hole inversion layers that constitutes the operating principle of these devices. The vertical electric field that appears across the intrinsic semiconductor to give rise to the bilayer configuration makes the formerly continuous conduction and valence bands become a discrete set of energy subbands, therefore increasing the effective bandgap close to the gates and reducing the BTBT probabilities. In this letter, we present a simulation approach that shows how the inclusion of quantum confinement and the subsequent modification of the band profile results in the appearance of lateral tunneling to the underlap regions that greatly degrades the subthreshold swing of these devices. To overcome this drawback imposed by confinement, we propose an heterogate configuration that proves to suppress this parasitic tunneling and enhances the device performance.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Effects of rapid thermal annealing on the electrical properties of the AlGaN/AlN/GaN heterostructure field-effect transistors with Ti/Al/Ni/Au gate electrodes

In this study, we investigated the electrical properties of the AlGaN/AlN/GaN heterostructure field-effect transistors (HFETs) with Ti/Al/Ni/Au gate electrodes using the measured capacitance-voltage, current-voltage characteristics, and micro-Raman spectroscopy. We found that the uneven distribution of the strain caused by the Schottky metals was a major factor that generates the polarization Coulomb field scattering in AlGaN/AlN/GaN HFETs, and after appropriate rapid thermal annealing (RTA) processes, the polarization Coulomb field scattering was greatly weakened and the two-dimensional electron gas electron mobility was improved. We also found that the Schottky barrier height and the DC characteristics of the devices became better after appropriate RTA. Of course, the electrical performances mentioned above became deteriorated after excessive annealing.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Contact research strategy for emerging molybdenum disulfide and other two-dimensional field-effect transistors

Layered two-dimensional (2D) semiconducting transition metal dichalcogenides (TMDs) have been widely isolated, synthesized, and characterized recently. Numerous 2D materials are identified as the potential candidates as channel materials for future thin film technology due to their high mobility and the exhibiting bandgaps. While many TMD filed-effect transistors (FETs) have been widely demonstrated along with a significant progress to clearly understand the device physics, large contact resistance at metal/semiconductor interface still remain a challenge. From 2D device research point of view, how to minimize the Schottky barrier effects on contacts thus reduce the contact resistance of metals on 2D materials is very critical for the further development of the field. Here, we present a review of contact research on molybdenum disulfide and other TMD FETs from the fundamental understanding of metal-semiconductor interfaces on 2D materials. A clear contact research strategy on 2D semiconducting materials is developed for future high-performance 2D FETs with aggressively scaled dimensions.

36 MATERIALS SCIENCE↗

MoS{sub 2} nanotube field effect transistors

We report on electric field effects on electron transport in multi-walled MoS{sub 2} nanotubes (NTs), fabricated using a two-step synthesis method from Mo{sub 6}S{sub x}I{sub 9-x} nanowire bundle precursors. Transport properties were measured on 20 single nanotube field effect transistor (FET) devices, and compared with MoS{sub 2} layered crystal devices prepared using identical fabrication techniques. The NTs exhibited mobilities of up to 0.014 cm{sup 2}V{sup −1}s{sup −1} and an on/off ratio of up to 60. As such they are comparable with previously reported WS{sub 2} nanotube FETs, but materials defects and imperfections apparently limit their performance compared with multilayer MoS{sub 2} FETs with similar number of layers.

36 MATERIALS SCIENCE↗

Low-voltage organic field-effect transistors based on novel high-κ organometallic lanthanide complex for gate insulating materials

A novel high-κ organometallic lanthanide complex, Eu(tta){sub 3}L (tta=2-thenoyltrifluoroacetonate, L = 4,5-pinene bipyridine), is used as gate insulating material to fabricate low-voltage pentacene field-effect transistors (FETs). The optimized gate insulator exhibits the excellent properties such as low leakage current density, low surface roughness, and high dielectric constant. When operated under a low voltage of −5 V, the pentacene FET devices show the attractive electrical performance, e.g. carrier mobility (μ{sub FET}) of 0.17 cm{sup 2} V{sup −1} s{sup −1}, threshold voltage (V{sub th}) of −0.9 V, on/off current ratio of 5 × 10{sup 3}, and subthreshold slope (SS) of 1.0 V dec{sup −1}, which is much better than that of devices obtained on conventional 300 nm SiO{sub 2} substrate (0.13 cm{sup 2} V{sup −1} s{sup −1}, −7.3 V and 3.1 V dec{sup −1} for μ{sub FET}, V{sub th} and SS value when operated at −30 V). These results indicate that this kind of high-κ organometallic lanthanide complex becomes a promising candidate as gate insulator for low-voltage organic FETs.

36 MATERIALS SCIENCE↗