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At least 649 records · Page 36

All sources NASA NTRS DOE OSTI

NASA NTRSDate not supplied

Developmental Hardware Testing Results and Forward Plans for Spacecraft Water Impurity Monitor (SWIM) Organic Water Module (OWM)

We present testing results for developmental hardware of the Spacecraft Water Impurity Monitor (SWIM) Organic Water Module (OWM). SWIM-OWM will monitor spacecraft potable water and system water for trace organic contaminants. The system will detect and identify the specific organic chemical that makes up a given total organic carbon reading. We have built a first development unit (1DU) for SWIM-OWM, which directly injects aqueous water samples and detects chemicals with both a thermal conductivity detector and mass spectrometer sensor. The gas chromatography mass spectrometer (GCMS) system that comprises SWIM-OWM draws on the success of ISS-proven mass spectrometer hardware, and the demonstration of GCMS detection of trace organic contaminants in ISS cabin air. SWIM-OWM benefits from the excellent sensitivity and specificity afforded by GCMS. We have demonstrated detection of a set of chemicals relevant to both crew health and performance as well as system monitoring; these target chemicals range from light, volatile organics such as acetone and ethanol, to heavier, very non-volatile compounds such as dimethyl sulfone and o-phthalaldehyde. Direct aqueous injection was chosen for the general applicability of the technique to clean water sampling and to preclude sample pre-processing, which facilitates an on-line implementation of the SWIM-OWM when deployed in a spacecraft or habitation module. A specific advantage of direct aqueous injection when coupled with appropriate methods is that both the light, volatile organics and heavier non-volatiles can be detected from a single injection, in a single chromatogram. Results from 1DU testing will be discussed, and forward plans will be outlined for continued maturation of SWIM-OWM with the goal of implementing a technology demonstration for the purposes of maturing the engineering design and operations in an environment relevant to NASA’s future goals of exploring and setting up habitation on the Moon and Mars.

Water Monitoring↗

NASA NTRSDate not supplied

Hardware Systems and EDU Demonstration of the Tall Lunar Tower Project

The Tall Lunar Tower (TLT) project developed a robotic tower assembly system (RTAS) and TLT Truss engineering development units (EDUs) to perform a ground demonstration of supervised semi-autonomous robotic assembly of a truss-based tall tower. Truss structures provide exceptional strength-to-weight ratios for payload capabilities supporting large masses. On the lunar surface, tall towers are a critical structural system that will enable significant solar power generation by supporting vertical solar arrays and beyond-the-horizon communications at the lunar south pole, supporting the Artemis mission architecture, as well as a lunar economy. Tall towers, greater than 30-meters-tall, provide the elevation needed for more consistent solar power generation due to low inclination sunlight and deep shadowing from surface features on the lunar surface at the poles. The robotic structural assembly technologies developed for truss-based tall towers will also enable other large-scale functional lunar structures to be built, including launch plume deflectors, lunar safe havens for astronauts and assets, surface transportation for cargo, and other critical infrastructure. Robotic assembly of truss structures for lunar surface infrastructure is near-term enabling for future Artemis mission campaign and Moon to Mars Objectives needs for power and communication. The project team designed, fabricated, tested, and demonstrated the RTAS EDU by assembling a TLT Truss EDU in a laboratory environment. The hardware systems and the supervised semi-autonomous assembly process for a TLT assembled EDU design, along with descriptions of a hardware demonstration are presented.

In-space Assembly↗

NASA NTRSDate not supplied

Yeast Strain Development and Hardware Testing in Preparation of a Lunar BioSensor

With Artemis missions underway, it is clear we are going back to the Moon to stay. Before sending Astronauts for long-duration missions, it is crucial to understand the technological and biomedical countermeasures needed to protect them before they get there. We can use knowledge gained from biological CubeSats to guide the next generation of experiments to support human habitation on the Moon. Lunar Explorer Instrument for space biology Applications (LEIA) is NASA’s latest BioSensor, adapted BioSentinel, the only CubeSat to travel Beyond Low Earth Orbit. BioSentinel launched on Artemis I and is currently >50 million kilometers from Earth (as of July 2024). LEIA aims to identify biological responses to the Lunar environment, which unprotected against would pose a threat to astronauts (cancer, cardiovascular disease, neurological impairment). The suite of instruments within LEIA detects Lunar radiation using two on-board radiation sensors (ARES charged particle detector, Mini-Fast Neutron Detector), then monitors real-time biological responses to the Lunar environment via an autonomous microfluidic system, fit with 3-LED emitter and detector boards and the alamarBlue metabolic indicator dye. LEIA will use a genetic approach in addition to synthetic biology to test counter-measure production in space, with the goal to inform and protect astronauts for future Moon missions. We have conducted preliminary tests in preparation for launch to the anticipated South Pole of the Moon, optimizing the biology (strain down-selection, desiccation tolerance, radiation sensitivity) and improving the hardware (including a blue LED to detect the beta-carotene countermeasure product). Our team will discuss these findings in several parts – an overview of the LEIA mission (Mark Settles), adapting flexible CubeSat platforms for deep-space applications (Sergio Santa Maria, Kira Rienecker), developing new technologies to support LEIA ground studies (Chinmayee Govinda Raj), and yeast strain development and hardware testing in preparation for LEIA (presented here).

synthetic biology↗

NASA NTRSDate not supplied

Hardware Systems and EDU Demonstration of the Tall Lunar Tower Project

Lunar Infrastructure↗

NASA NTRS2025

Orion Hardware In The Loop OIMU Stimulation Latency Effect on Navigation State Estimation

Because Hardware In The Loop (HITL) testing involves the integration of flight software and flight hardware on the ground, non-flight-like effects may arise. One of these non-flight-like effects includes Inertial Measurement Unit (IMU) stimulation latency that affects the time in which the measurement is received by the Extended Kalman Filter (EKF). This paper seeks to present the extent to which this stimulation latency affects the navigational state estimate from the Orion navigation system for all phases of flight for Artemis II.

Christopher A Ertl↗

NASA NTRSDate not supplied

Orion Hardware In The Loop OIMU Stimulation Latency Effect on Navigation State Estimation

Christopher A Ertl↗

DOE OSTI2011

A hardware overview of the RHIC LLRF platform

The RHIC Low Level RF (LLRF) platform is a flexible, modular system designed around a carrier board with six XMC daughter sites. The carrier board features a Xilinx FPGA with an embedded, hard core Power PC that is remotely reconfigurable. It serves as a front end computer (FEC) that interfaces with the RHIC control system. The carrier provides high speed serial data paths to each daughter site and between daughter sites as well as four generic external fiber optic links. It also distributes low noise clocks and serial data links to all daughter sites and monitors temperature, voltage and current. To date, two XMC cards have been designed: a four channel high speed ADC and a four channel high speed DAC. The new LLRF hardware was used to replace the old RHIC LLRF system for the 2009 run. For the 2010 run, the RHIC RF system operation was dramatically changed with the introduction of accelerating both beams in a new, common cavity instead of each ring having independent cavities. The flexibility of the new system was beneficial in allowing the low level system to be adapted to support this new configuration. This hardware was also used in 2009 to provide LLRF for the newly commissioned Electron Beam Ion Source.

43 PARTICLE ACCELERATORS↗

DOE OSTI2010

Computer hardware fault administration

Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.

Archer, Charles J↗

DOE OSTI2012

Hardware Architectures for Data-Intensive Computing Problems: A Case Study for String Matching

DNA analysis is an emerging application of high performance bioinformatic. Modern sequencing machinery are able to provide, in few hours, large input streams of data, which needs to be matched against exponentially growing databases of known fragments. The ability to recognize these patterns effectively and fastly may allow extending the scale and the reach of the investigations performed by biology scientists. Aho-Corasick is an exact, multiple pattern matching algorithm often at the base of this application. High performance systems are a promising platform to accelerate this algorithm, which is computationally intensive but also inherently parallel. Nowadays, high performance systems also include heterogeneous processing elements, such as Graphic Processing Units (GPUs), to further accelerate parallel algorithms. Unfortunately, the Aho-Corasick algorithm exhibits large performance variability, depending on the size of the input streams, on the number of patterns to search and on the number of matches, and poses significant challenges on current high performance software and hardware implementations. An adequate mapping of the algorithm on the target architecture, coping with the limit of the underlining hardware, is required to reach the desired high throughputs. In this paper, we discuss the implementation of the Aho-Corasick algorithm for GPU-accelerated high performance systems. We present an optimized implementation of Aho-Corasick for GPUs and discuss its tradeoffs on the Tesla T10 and he new Tesla T20 (codename Fermi) GPUs. We then integrate the optimized GPU code, respectively, in a MPI-based and in a pthreads-based load balancer to enable execution of the algorithm on clusters and large sharedmemory multiprocessors (SMPs) accelerated with multiple GPUs.

Tumeo, Antonino↗

DOE OSTI2013

Hardware packet pacing using a DMA in a parallel computer

Method and system for hardware packet pacing using a direct memory access controller in a parallel computer which, in one aspect, keeps track of a total number of bytes put on the network as a result of a remote get operation, using a hardware token counter.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2014

Deterrence of device counterfeiting, cloning, and subversion by substitution using hardware fingerprinting

Deterrence of device subversion by substitution may be achieved by including a cryptographic fingerprint unit within a computing device for authenticating a hardware platform of the computing device. The cryptographic fingerprint unit includes a physically unclonable function ("PUF") circuit disposed in or on the hardware platform. The PUF circuit is used to generate a PUF value. A key generator is coupled to generate a private key and a public key based on the PUF value while a decryptor is coupled to receive an authentication challenge posed to the computing device and encrypted with the public key and coupled to output a response to the authentication challenge decrypted with the private key.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2015

Scaling Retro-Commissioning to Small Commercial Buildings: A Turnkey Automated Hardware-Software Solution

In the United States, small commercial buildings represent 51% of total floor space of all commercial buildings and consume nearly 3 quadrillion Btu (3.2 quintillion joule) of site energy annually, presenting an enormous opportunity for energy savings. Retro-commissioning (RCx), the process through which professional energy service providers identify and correct operational problems, has proven to be a cost-effective means to achieve median energy savings of 16%. However, retro-commissioning is not typically conducted at scale throughout the commercial stock. Very few small commercial buildings are retro-commissioned because utility expenses are relatively modest, margins are tighter, and capital for improvements is limited. In addition, small buildings do not have in-house staff with the expertise to identify improvement opportunities. In response, a turnkey hardware-software solution was developed to enable cost-effective, monitoring-based RCx of small commercial buildings. This highly tailored solution enables non-commissioning providers to identify energy and comfort problems, as well as associated cost impacts and remedies. It also facilitates scale by offering energy service providers the means to streamline their existing processes and reduce costs by more than half. The turnkey RCx sensor suitcase consists of two primary components: a suitcase of sensors for short-term building data collection that guides users through the process of deploying and retrieving their data and a software application that automates analysis of sensor data, identifies problems and generates recommendations. This paper presents the design and testing of prototype models, including descriptions of the hardware design, analysis algorithms, performance testing, and plans for dissemination.

Lin, Guanjing↗

DOE OSTI2014

Exploring Infiniband Hardware Virtualization in OpenNebula towards Efficient High-Performance Computing

has been widely accepted that software virtualization has a big negative impact on high-performance computing (HPC) application performance. This work explores the potential use of Infiniband hardware virtualization in an OpenNebula cloud towards the efficient support of MPI-based workloads. We have implemented, deployed, and tested an Infiniband network on the FermiCloud private Infrastructure-as-a-Service (IaaS) cloud. To avoid software virtualization towards minimizing the virtualization overhead, we employed a technique called Single Root Input/Output Virtualization (SRIOV). Our solution spanned modifications to the Linux’s Hypervisor as well as the OpenNebula manager. We evaluated the performance of the hardware virtualization on up to 56 virtual machines connected by up to 8 DDR Infiniband network links, with micro-benchmarks (latency and bandwidth) as well as w a MPI-intensive application (the HPL Linpack benchmark).

Pais Pitta de Lacerda Ruivo, Tiago↗

DOE OSTI2017

Multi-Megawatt-Scale Power-Hardware-in-the-Loop Interface for Testing Ancillary Grid Services by Converter-Coupled Generation: Preprint

Power-hardware-in-the-loop (PHIL) is a simulation tool that can support electrical systems engineers in the development and experimental validation of novel, advanced control schemes that ensure the robustness and resiliency of electrical grids that have high penetrations of low-inertia variable renewable resources. With PHIL, the impact of the device under test on a generation or distribution system can be analyzed using a real-time simulator (RTS). PHIL allows for the interconnection of the RTS with a 7 megavolt ampere (MVA) power amplifier to test multi-megawatt renewable assets available at the National Wind Technology Center (NWTC). This paper addresses issues related to the development of a PHIL interface that allows testing hardware devices at actual scale. In particular, the novel PHIL interface algorithm and high-speed digital interface, which minimize the critical loop delay, are discussed.

17 WIND ENERGY↗

DOE OSTI2017

Real-Time Digital Simulation of Inertial Response with Hardware-in-the-Loop Implementation on the CART3 Wind Turbine at the National Wind Technology Center

With increasing penetrations of wind power on electric grids, the stability and reliability of interconnected power systems may be impacted. In some countries that have developed renewable energy sources and systems, grid codes have been revised to require wind power plants (WPPs) to provide ancillary services to support the power system frequency in case of severe grid events. To do this, wind turbine generators (WTGs) should be deloaded to reserve a certain amount of active power for primary frequency response; however, deloading curtails annual energy production, and the market for this type of service needs to be further developed. In this report, we focus on the temporary frequency support provided by WTGs through inertial response. WTGs have potential to provide inertial response, but appropriate control methods should be implemented. With the implemented inertial control methods, wind turbines are capable of increasing their active power output by releasing some of their stored kinetic energy when a frequency excursion occurs. Active power can be temporarily boosted above the maximum power points, after which the rotor speed decelerates, and subsequently an active power output reduction restores the kinetic energy. In this report, we develop two types of models for wind power systems: the first is common, based on the wind power aerodynamic equation, and the power coefficient can be regressed using nonlinear functions; the second is much more complicated, wherein the wind turbine system is modeled using the Fatigue, Aerodynamics, Structures, and Turbulence Modeling (FAST) tool with several degrees of freedoms. A nine-bus test power system is built in Simulink and the Real-Time Digital Simulator, respectively, which are used to evaluate the frequency support performance of the WPPs. We implement two distinct types of inertial control methods in the modeled wind turbines: frequency-based inertial control (FBIC) and stepwise inertial control (SIC). We compare the performances of the two methods in terms of their frequency nadirs, rates of change of frequency, and recovery times. We conclude the results under various wind speeds and penetration cases, which provide insight into designing the inertial response of WTGs. Further, we discuss the impact of the parameters on the performance of the inertial control methods. We evaluate both the scaling factors for the FBIC method and the slope values for the TLIC methods. The simulation work shows the characteristics of different inertial responses compared to conventional synchronous generators. Based on the simulation results, we modify, improve, and test the inertial control methods under a more realistic wind turbine model based on FAST. We then validate the inertial responses under highly turbulent wind conditions generated by TurbSim, and we examine their influences on the turbine mechanical components. The extensive simulation proves the effectiveness of the proposed inertial control methods as well as the nine-bus test power system. We then reconsider the parameters. We rebuild the same test power system using Real time Simulator Computer Aided Design (RSCAD), and we implement the inertial control methods in the real Controls Advanced Research Turbine (CART3), which is prepared for the hardware-in-the-loop field-test simulation. After the setups for the hardware and software hybrid simulation platform are complete, the inertial response is further tested on a real wind turbine for the first time, in which CART3 release the controlled inertial response against the emulated frequency excursion, provided by the real-time simulated power system test bed in RTDS.

17 WIND ENERGY↗

DOE OSTI2018

Hardware accuracy counters for application precision and quality feedback

Methods, devices, and systems for capturing an accuracy of an instruction executing on a processor. An instruction may be executed on the processor, and the accuracy of the instruction may be captured using a hardware counter circuit. The accuracy of the instruction may be captured by analyzing bits of at least one value of the instruction to determine a minimum or maximum precision datatype for representing the field, and determining whether to adjust a value of the hardware counter circuit accordingly. The representation may be output to a debugger or logfile for use by a developer, or may be output to a runtime or virtual machine to automatically adjust instruction precision or gating of portions of the processor datapath.

47 OTHER INSTRUMENTATION↗

DOE OSTI2018

Hardware Design of a 1.7 kV SiC MOSFET Based MMC for Medium Voltage Motor Drives

Abstract—This paper presents the hardware design of a 7 kV dc bus,1 MVA, 0-1,000 Hz, 1.7 kV SiC MOSFET based medium voltage variable speed drive (MVVSD)1. The system is based on a 7-level three-phase modular multilevel converter (MMC). The full in-depth design, development, and testing of this prototype are provided, including MMC submodule development, arm inductor design, control hardware realization, system integration and thermal analysis. Finally, experimental results demonstrate the excellent performance of the 1.7 kV SiC MOSFET based submodule and the 1 MW, 7 kV MVVSD as a unity in various operation modes

SiC MOSFET, Modular Multilevel Converter, Medium V↗

DOE OSTI2020

SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators

Next generation systems, such as edge devices, will have to provide efficient processing of machine learning (ML) algorithms along several metrics, including energy, performance, area, and latency. However, the quickly evolving field of ML makes it extremely difficult to generate accelerators able to support a wide variety of algorithms. At the same time, designing accelerators in hardware description languages (HDLs) by hand is hard and time consuming, and does not allow quick exploration of the design space. This paper discusses the SODA synthesizer, an automated open source high-level ML framework-to-Verilog compiler targeting ML Application-Specific Integrated Circuits (ASICs) chiplets based on the LLVM infrastructure. The SODA synthesizers will allow implementing optimal designs by combining templated and fully tunable IPs and macros, and fully custom components generated through high-level synthesis. All these components will be provided through an extendable resource library, characterized with both commercial and open source logic design flows. Through a closed loop design space exploration engine, developers will be able to quickly explore their hardware designs along different dimension

Minutoli, Marco↗