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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 631 records · Page 35
All sourcesNASA NTRSDOE OSTI
NASA NTRS1979

Trends in reliability modeling technology for fault tolerant systems

Developments in reliability modeling for large fault tolerant avionic computing systems are presented. Issues of state size and complexity, fault coverage, and practical computation are addressed. A two-fold developmental effort is described based on the structural and fault coverage modeling approaches. A technique which was successfully applied to an 865 state pure death stationary Markov model is presented. Of particular interest is a short computer program which executes very quickly to produce reliability results of a large state space model. This model also incorporates fault coverage states for processor, memory, and bus line replaceable units. A second structural reliability modeling scheme is aimed at solving nonstationary Markov models. This technique provides the tool required for studying the reliability of systems with nonconstant failure rates and includes intermittent/transient faults, electronic hardware which exhibits decreasing failure rates, and hydromechanical devices which typically have wearout failure mechanisms. Several aspects of fault coverage, including modeling and data measurement of intermittent/transient faults and latent faults, are elucidated and illustrated. The CARE II (computer-aided reliability estimation) coverage is presented and shortcomings to be eliminated are discussed.

Bavuso, S. J.↗
NASA NTRS1983

Data flow methods for dynamic system simulation - A CSSL-IV microcomputer network interface

A major problem in employing networks of microcomputers for the real-time simulation of complex systems is to allocate computational tasks to the various microcomputers in such a way that idle time and time lost in interprocess communication is minimized. The research reported in this paper is directed to the development of a software interface between a higher-level simulation language and a network of microcomputers. A CSSL-IV source program is translated to a data flow graph. This graph is then analyzed automatically so as to allocate computing tasks to the various processors.

Makoui, A.↗
NASA NTRS1989

Implementing nested conditional statements in SIMD machines

Single instruction, multiple data (SIMD) computers consist of a very large number of processors executing a common sequence of instructions. Maintaining the full speedup potential of such machines is most sensitive to conditional execution in their programs, regions of code where some processing elements (PEs) perform no useful work. Techniques are presented for efficiently implementing nested conditional statements, specifically if and case statements, in SIMD machines, while adding minimal specialized hardware.

Middleton, David↗
NASA NTRS1990

Sequence invariant state machines

A synthesis method and new VLSI architecture are introduced to realize sequential circuits that have the ability to implement any state machine having N states and m inputs, regardless of the actual sequence specified in the flow table. A design method is proposed that utilizes BTS logic to implement regular and dense circuits. A given state sequence can be programmed with power supply connections or dynamically reallocated if stored in a register. Arbitrary flow table sequences can be modified or programmed to dynamically alter the function of the machine. This allows VLSI controllers to be designed with the programmability of a general purpose processor but with the compact size and performance of dedicated logic.

Whitaker, S.↗
NASA NTRS1993

Mongoose: Creation of a Rad-Hard MIPS R3000

This paper describes the development of a 32 Bit, full MIPS R3000 code-compatible Rad-Hard CPU, code named Mongoose. Mongoose progressed from contract award, through the design cycle, to operational silicon in 12 months to meet a space mission for NASA. The goal was the creation of a fully static device capable of operation to the maximum Mil-883 derated speed, worst-case post-rad exposure with full operational integrity. This included consideration of features for functional enhancements relating to mission compatibility and removal of commercial practices not supported by Rad-Hard technology. 'Mongoose' developed from an evolution of LSI Logic's MIPS-I embedded processor, LR33000, code named Cobra, to its Rad-Hard 'equivalent', Mongoose. The term 'equivalent' is used to infer that the core of the processor is functionally identical, allowing the same use and optimizations of the MIPS-I Instruction Set software tool suite for compilation, software program trace, etc. This activity was started in September of 1991 under a contract from NASA-Goddard Space Flight Center (GSFC)-Flight Data Systems. The approach affected a teaming of NASA-GSFC for program development, LSI Logic for system and ASIC design coupled with the Rad-Hard process technology, and Harris (GASD) for Rad-Hard microprocessor design expertise. The program culminated with the generation of Rad-Hard Mongoose prototypes one year later.

Lincoln, Dan↗
NASA NTRS1994

Hardware and software reliability estimation using simulations

The simulation technique is used to explore the validation of both hardware and software. It was concluded that simulation is a viable means for validating both hardware and software and associating a reliability number with each. This is useful in determining the overall probability of system failure of an embedded processor unit, and improving both the code and the hardware where necessary to meet reliability requirements. The methodologies were proved using some simple programs, and simple hardware models.

Swern, Frederic L.↗
NASA NTRS1994

Recycle Requirements for NASA's 30 cm Xenon Ion Thruster

Electrical breakdowns have been observed during ion thruster operation. These breakdowns, or arcs, can be caused by several conditions. In flight systems, the power processing unit must be designed to handle these faults autonomously. This has a strong impact on power processor requirements and must be understood fully for the power processing unit being designed for the NASA Solar Electric Propulsion Technology Application Readiness program. In this study, fault conditions were investigated using a NASA 30 cm ion thruster and a power console. Power processing unit output specifications were defined based on the breakdown phenomena identified and characterized.

Pinero, Luis R.↗
NASA NTRS2017

Towards a Qualification Data Set: Expanded SEE Data on the P2020 Processor

Earlier P2020 SEE data are compared and expanded to a recent die revision, significantly increasing samples tested by protons by five devices, and by heavy ions by five devices. Earlier tested SEE types are found to be fairly similar in register, L1 cache, L2 cache, and CPU crashes. New test methods give SEE performance for the flash memory controller, watchdog circuit, and a built-in Ethernet port on the P2020 processor. Results from heavy ion and proton tests are presented, with data separated over a large number of specific error types and test programs.

Vartanian, Sargeh↗
DOE OSTI2022

Controlling prediction functional blocks used by a branch predictor in a processor

An electronic device includes a processor, a branch predictor in the processor, and a predictor controller in the processor. The branch predictor includes multiple prediction functional blocks, each prediction functional block configured for generating predictions for control transfer instructions (CTIs) in program code based on respective prediction information, the branch predictor configured to select, from among predictions generated by the prediction functional blocks for each CTI, a selected prediction to be used for that CTI. The predictor controller keeps a record of prediction functional blocks from which the branch predictor previously selected predictions for CTIs. The predictor controller uses information from the record for controlling which prediction functional blocks are used by the branch predictor for generating predictions for CTIs.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Modbus RTU for Embedded Cyber Secure Inverter Controller

The Modbus communication protocol is a widely adopted communication standard in industrial control systems. This communication protocol is known for being reliable and straightforward to implement while being versatile in terms of its operating parameters while supporting multiple formats over various hardware infrastructures and architectures. Many intelligent devices such as Programmable Logic Controllers (PLCs), Human-Machine Interfaces (HMIs), Internet-of-Things (IoT), and various Operational Technologies (OT) utilize Modbus for their communication systems. These types of systems must communicate with each other through a standardized and central communication process. To support the integration of these modular systems, a Field-Programmable Gate Array (FPGA) can act as an embedded central routing fabric for this communication to take place. Embedded systems are versatile enough to interface with various devices and systems to accomplish various goals. Additionally, embedded systems require relatively small physical designs to minimize the required resources to facilitate the intended application by providing low-level system access. This minimization of system resources goes hand in hand with reducing the financial cost of a proposed solution or system. As remotely collaborating researchers often use FPGAs to prototype designs that are required to have a method for data transmission among systems, it is imperative to provide a baseline standard for communications among devices and systems. A typical method of implementing the Modbus RTU communication protocol in an embedded environment is using integrated logic architectures within the FPGA called “Intellectual Property (IP) cores.” IP cores can be designed using integrated logic or circuit designs to function as an embedded processor. These IP cores can then perform the required computational actions to support the Modbus RTU communication protocol by utilizing high-level programming languages such as the C programming language. The hardware description language of Very High-Speed Integrated Circuit Hardware Description Language (VHDL) allows for the control of real hardware at the logic gate and signal level. These logic gates and signals can be designed and controlled to perform desired actions based on the system design. Programming an FPGA using VHDL allows an individual to access the lowest abstraction level of the system during FPGA development. This level of abstraction is referred to as the register-transfer level (RTL), which gives access to manipulating values and variables at the register level. This register-level manipulation provides precision over creating the logical circuit within the FPGA, thus minimizing the required code to perform desired operations. The Modbus RTU communication protocol can be implemented within an FPGA using VHDL programming to establish a standardized and embedded serial communication pathway. This implementation provides a standardized communication protocol to streamline research efforts among researchers, thus increasing the efficiency of research efforts. Additionally, this Modbus RTU implementation requires fewer resources when compared to typical communication protocol implementations that utilize an IP core, reducing the hardware requirement for effective research efforts.

communication↗
NASA NTRS1994

Compute Server Performance Results

Parallel-vector supercomputers have been the workhorses of high performance computing. As expectations of future computing needs have risen faster than projected vector supercomputer performance, much work has been done investigating the feasibility of using Massively Parallel Processor systems as supercomputers. An even more recent development is the availability of high performance workstations which have the potential, when clustered together, to replace parallel-vector systems. We present a systematic comparison of floating point performance and price-performance for various compute server systems. A suite of highly vectorized programs was run on systems including traditional vector systems such as the Cray C90, and RISC workstations such as the IBM RS/6000 590 and the SGI R8000. The C90 system delivers 460 million floating point operations per second (FLOPS), the highest single processor rate of any vendor. However, if the price-performance ration (PPR) is considered to be most important, then the IBM and SGI processors are superior to the C90 processors. Even without code tuning, the IBM and SGI PPR's of 260 and 220 FLOPS per dollar exceed the C90 PPR of 160 FLOPS per dollar when running our highly vectorized suite,

Stockdale, I. E.↗
NASA NTRS2017

13kW Advanced Electric Propulsion Flight System Development and Qualification

The next phase of robotic and human deep space exploration missions is enhanced by high performance, high power solar electric propulsion systems for large-scale science missions and cargo transportation. Aerojet Rocketdynes Advanced Electric Propulsion System (AEPS) program is completing development, qualification and delivery of five flight 13.3kW EP systems to NASA. The flight AEPS includes a magnetically-shielded, long-life Hall thruster, power processing unit (PPU), xenon flow controller (XFC), and intrasystem harnesses. The Hall thruster, originally developed and demonstrated by NASAs Glenn Research Center and the Jet Propulsion Laboratory, operates at input powers up to 12.5kW while providing a specific impulse over 2600s at an input voltage of 600V. The power processor is designed to accommodate an input voltage range of 95 to 140V, consistent with operation beyond the orbit of Mars. The integrated system is continuously throttleable between 3 and 13.3kW. The program has completed the system requirement review; the system, thruster, PPU and XFC preliminary design reviews; development of engineering models, and initial system integration testing. This paper will present the high power AEPS capabilities, overall program and design status and the latest test results for the 13.3kW flight system development and qualification program.

Jackson, Jerry↗
NASA NTRS2013

NASA Tech Briefs, September 2013

Topics include: ISS Ammonia Leak Detection Through X-Ray Fluorescence; A System for Measuring the Sway of the Vehicle Assembly Building; Fast, High-Precision Readout Circuit for Detector Arrays; Victim Simulator for Victim Detection Radar; Hydrometeor Size Distribution Measurements by Imaging the Attenuation of a Laser Spot; Quasi-Linear Circuit; High-Speed, High-Resolution Time-to-Digital Conversion; Li-Ion Battery and Supercapacitor Hybrid Design for Long Extravehicular Activities; Ultrasonic Low-Friction Containment Plate for Thermal and Ultrasonic Stir Weld Processes; High-Powered, Ultrasonically Assisted Thermal Stir Welding; Next-Generation MKIII Lightweight HUT/Hatch Assembly; Centrifugal Sieve for Gravity-Level-Independent Size; Segregation of Granular Materials; Ion Exchange Technology Development in Support of the Urine Processor Assembly; Nickel-Graphite Composite Compliant Interface and/or Hot Shoe Material; UltraSail CubeSat Solar Sail Flight Experiment; Mechanism for Deploying a Long, Thin-Film Antenna From a Rover; Counterflow Regolith Heat Exchanger; Acquisition and Retaining Granular Samples via a Rotating Coring Bit; Very-Low-Cost, Rugged Vacuum System; Medicine Delivery Device With Integrated Sterilization and Detection; FRET-Aptamer Assays for Bone Marker Assessment, C-Telopeptide, Creatinine, and Vitamin D; Multimode Directional Coupler for Utilization of Harmonic Frequencies from TWTAs; Dual-Polarization, Multi-Frequency Antenna Array for use with Hurricane Imaging Radiometer; Complementary Barrier Infrared Detector (CBIRD) Contact Methods; Autonomous Control of Space Nuclear Reactors; High-Power, High-Speed Electro-Optic Pockels Cell Modulator; Covariance Analysis Tool (G-CAT) for Computing Ascent, Descent, and Landing Errors; Enigma Version 12; Micrometeoroid and Orbital Debris (MMOD) Shield Ballistic Limit Analysis Program; Spitzer Telemetry Processing System; Planetary Protection Bioburden Analysis Program; Wing Leading Edge RCC Rapid Response Damage Prediction Tool (IMPACT2); ISSM: Ice Sheet System Model; Automated Loads Analysis System (ATLAS); Integrated Main Propulsion System Performance Reconstruction Process/Models. Phoenix Telemetry Processor; Contact Graph Routing Enhancements Developed in ION for DTN; GFEChutes Lo-Fi; Advanced Strategic and Tactical Relay Request Management for the Mars Relay Operations Service; Software for Generating Troposphere Corrections for InSAR Using GPS and Weather Model Data; Ionospheric Specifications for SAR Interferometry (ISSI); Implementation of a Wavefront-Sensing Algorithm; Sally Ride EarthKAM - Automated Image Geo-Referencing Using Google Earth Web Plug-In; Trade Space Specification Tool (TSST) for Rapid Mission Architecture (Version 1.2); Acoustic Emission Analysis Applet (AEAA) Software; Memory-Efficient Onboard Rock Segmentation; Advanced Multimission Operations System (ATMO); Robot Sequencing and Visualization Program (RSVP); Automating Hyperspectral Data for Rapid Response in Volcanic Emergencies; Raster-Based Approach to Solar Pressure Modeling; Space Images for NASA JPL Android Version; Kinect Engineering with Learning (KEWL); Spacecraft 3D Augmented Reality Mobile App; MPST Software: grl_pef_check; Real-Time Multimission Event Notification System for Mars Relay; SIM_EXPLORE: Software for Directed Exploration of Complex Systems; Mobile Timekeeping Application Built on Reverse-Engineered JPL Infrastructure; Advanced Query and Data Mining Capabilities for MaROS; Jettison Engineering Trajectory Tool; MPST Software: grl_suppdoc; PredGuid+A: Orion Entry Guidance Modified for Aerocapture; Planning Coverage Campaigns for Mission Design and Analysis: CLASP for DESDynl; and Space Place Prime.

Source record↗
NASA NTRS1986

Symbolic generation of elastic rotor blade equations using a FORTRAN processor and numerical study on dynamic inflow effects on the stability of helicopter rotors

The process of performing an automated stability analysis for an elastic-bladed helicopter rotor is discussed. A symbolic manipulation program, written in FORTRAN, is used to aid in the derivation of the governing equations of motion for the rotor. The blades undergo coupled bending and torsional deformations. Two-dimensional quasi-steady aerodynamics below stall are used. Although reversed flow effects are neglected, unsteady effects, modeled as dynamic inflow are included. Using a Lagrangian approach, the governing equations are derived in generalized coordinates using the symbolic program. The program generates the steady and perturbed equations and writes into subroutines to be called by numerical routines. The symbolic program can operate on both expressions and matrices. For the case of hovering flight, the blade and dynamic inflow equations are converted to equations in a multiblade coordinate system by rearranging the coefficients of the equations. For the case of forward flight, the multiblade equations are obtained through the symbolic program. The final multiblade equations are capable of accommodating any number of elastic blade modes. The computer implementation of this procedure consists of three stages: (1) the symbolic derivation of equations; (2) the coding of the equations into subroutines; and (3) the numerical study after identifying mass, damping, and stiffness coefficients. Damping results are presented in hover and in forward flight with and without dynamic inflow effects for various rotor blade models, including rigid blade lag-flap, elastic flap-lag, flap-lag-torsion, and quasi-static torsion. Results from dynamic inflow effects which are obtained from a lift deficiency function for a quasi-static inflow model in hover are also presented.

Reddy, T. S. R.↗
NASA NTRS1993

Computer program for analysis of high speed, single row, angular contact, spherical roller bearing, SASHBEAN. Volume 1: User's guide

The computer program SASHBEAN (Sikorsky Aircraft Spherical Roller High Speed Bearing Analysis) analyzes and predicts the operating characteristics of a Single Row, Angular Contact, Spherical Roller Bearing (SRACSRB). The program runs on an IBM or IBM compatible personal computer, and for a given set of input data analyzes the bearing design for it's ring deflections (axial and radial), roller deflections, contact areas and stresses, induced axial thrust, rolling element and cage rotation speeds, lubrication parameters, fatigue lives, and amount of heat generated in the bearing. The dynamic loading of rollers due to centrifugal forces and gyroscopic moments, which becomes quite significant at high speeds, is fully considered in this analysis. For a known application and it's parameters, the program is also capable of performing steady-state and time-transient thermal analyses of the bearing system. The steady-state analysis capability allows the user to estimate the expected steady-state temperature map in and around the bearing under normal operating conditions. On the other hand, the transient analysis feature provides the user a means to simulate the 'lost lubricant' condition and predict a time-temperature history of various critical points in the system. The bearing's 'time-to-failure' estimate may also be made from this (transient) analysis by considering the bearing as failed when a certain temperature limit is reached in the bearing components. The program is fully interactive and allows the user to get started and access most of its features with a minimal of training. For the most part, the program is menu driven, and adequate help messages were provided to guide a new user through various menu options and data input screens. All input data, both for mechanical and thermal analyses, are read through graphical input screens, thereby eliminating any need of a separate text editor/word processor to edit/create data files. Provision is also available to select and view the contents of output files on the monitor screen if no paper printouts are required. A separate volume (Volume-2) of this documentation describes, in detail, the underlying mathematical formulations, assumptions, and solution algorithms of this program.

Aggarwal, Arun K.↗
NASA NTRS1973

Development of a uninterrupted power system: ac and dc to dc converter

This program covered the design, fabrication and testing of an advanced development model uninterrupted power system. The input and output requirements imposed on the power processor were specified such that the unit is electrically interchangeable with existing power systems used by the Federal Aviation Administration in installations which have a history of failure due to electrical transient conditions. Input power is from either of two single-phase ac power sources or batteries with electronic selection and transfer between power sources. Battery reconditioning is automatic when either ac source is present. The output power is rated at 84OW; the nominal output is 24V at 35A. Within the 84OW limit, the regulated output voltage is adjustable from 22V to 30Vdc. Protection against continuous overloading or short circuit is provided. The unit is packaged in a standard 19-inch rack mount configuration with 7-inch panel height. Controls are on the front panel with power input and output through connectors on the rear surface. Cooling is by free convection from fin areas located on the side and rear panels. The packaged unit weighs 52.8 lbs., which can be reduced significantly if a three-phase ac power source is used.

Cronin, D. L.↗
NASA NTRS1976

Formulation of a methodology for power circuit design optimization

A methodology for optimizing power-processor designs is described which achieves optimization with respect to some power-processor characteristic deemed particularly desirable by the designer, such as weight or efficiency. Optimization theory based on Lagrange multipliers is reviewed together with nonlinear programming techniques employing penalty functions. The methodology, the task of which is to minimize an objective function subject to design constraints, is demonstrated with the aid of four examples: optimum-weight core selection for an inductor with a predetermined winding size, optimum-weight inductor design with a given loss constraint, optimum-loss inductor design with a given weight constraint, and a comparison of optimum-weight single- and two-stage input-filter designs with identical loss and other requirement constraints. Closed-form solutions for the first three examples are obtained by applying the Lagrange-multiplier method, but solutions for the last example are found numerically through the use of the sequential unconstrained minimization technique.

Yu, Y.↗
NASA NTRS1982

Implementation of the DAST ARW II control laws using an 8086 microprocessor and an 8087 floating-point coprocessor

A 5 MHZ single-board microprocessor system which incorporates an 8086 CPU and an 8087 Numeric Data Processor is used to implement the control laws for the NASA Drones for Aerodynamic and Structural Testing, Aeroelastic Research Wing II. The control laws program was executed in 7.02 msec, with initialization consuming 2.65 msec and the control law loop 4.38 msec. The software emulator execution times for these two tasks were 36.67 and 61.18, respectively, for a total of 97.68 msec. The space, weight and cost reductions achieved in the present, aircraft control application of this combination of a 16-bit microprocessor with an 80-bit floating point coprocessor may be obtainable in other real time control applications.

Kelly, G. L.↗