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At least 631 records · Page 35
All sourcesNASA NTRSDOE OSTI
NASA NTRS2001

Ultrasonic Data Display and Analysis System Developed (Including Fuzzy Logic Analysis) for the Windows-Based PC

Post-Scan Interactive Data Display (PSIDD) III is a user-oriented Windows-based system that facilitates the display and comparison of ultrasonic contact measurement data obtained at NASA Glenn Research Center's Ultrasonic Nondestructive Evaluation measurement facility. The system is optimized to compare ultrasonic measurements made at different locations within a material or at different stages of material degradation. PSIDD III provides complete analysis of the primary waveforms in the time and frequency domains along with the calculation of several frequency-dependent properties including phase velocity and attenuation coefficient and several frequency-independent properties, like the cross correlation velocity. The system allows image generation on all the frequency-dependent properties at any available frequency (limited by the bandwidth used in the scans) and on any of the frequency-independent properties. From ultrasonic contact scans, areas of interest on an image can be studied with regard to underlying raw waveforms and derived ultrasonic properties by simply selecting the point on the image. The system offers various modes of indepth comparison between scan points. Up to five scan points can be selected for comparative analysis at once. The system was developed with Borland Delphi software (Visual Pascal) and is based on an SQL data base. It is ideal for the classification of material properties or the location of microstructure variations in materials. Along with the ultrasonic contact measurement software that it is partnered with, this system is technology ready and can be transferred to users worldwide.

Lovelace, Jeffrey J.↗
NASA NTRS2006

Recent Results on SEU Hardening of SiGe HBT Logic Circuits

A viewgraph presentation on SEU tolerant SiGe HBT technology is shown. The topics include: 1) Introduction; 2) TID and SEU in SiGe Technology; 3) RHBD Techniques; 4) Experiment; 5) Heavy-Ion Data and Analysis; and 6) Summary.

Krithivasan, Ramkumar↗
NASA NTRS2004

Digital logic optimization using selection operators

According to the invention, a digital design method for manipulating a digital circuit netlist is disclosed. In one step, a first netlist is loaded. The first netlist is comprised of first basic cells that are comprised of first kernel cells. The first netlist is manipulated to create a second netlist. The second netlist is comprised of second basic cells that are comprised of second kernel cells. A percentage of the first and second kernel cells are selection circuits. There is less chip area consumed in the second basic cells than in the first basic cells. The second netlist is stored. In various embodiments, the percentage could be 2% or more, 5% or more, 10% or more, 20% or more, 30% or more, or 40% or more.

Whitaker, Sterling R.↗
NASA NTRS2004

Digital circuits using universal logic gates

According to the invention, a digital circuit design embodied in at least one of a structural netlist, a behavioral netlist, a hardware description language netlist, a full-custom ASIC, a semi-custom ASIC, an IP core, an integrated circuit, a hybrid of chips, one or more masks, a FPGA, and a circuit card assembly is disclosed. The digital circuit design includes first and second sub-circuits. The first sub-circuits comprise a first percentage of the digital circuit design and the second sub-circuits comprise a second percentage of the digital circuit design. Each of the second sub-circuits is substantially comprised of one or more kernel circuits. The kernel circuits are comprised of selection circuits. The second percentage is at least 5%. In various embodiments, the second percentage could be at least 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or 95%.

Whitaker, Sterling R.↗
NASA NTRS2010

Precise delay measurement through combinatorial logic

A high resolution circuit and method for facilitating precise measurement of on-chip delays for FPGAs for reliability studies. The circuit embeds a pulse generator on an FPGA chip having one or more groups of LUTS (the "LUT delay chain"), also on-chip. The circuit also embeds a pulse width measurement circuit on-chip, and measures the duration of the generated pulse through the delay chain. The pulse width of the output pulse represents the delay through the delay chain without any I/O delay. The pulse width measurement circuit uses an additional asynchronous clock autonomous from the main clock and the FPGA propagation delay can be displayed on a hex display continuously for testing purposes.

Burke, Gary R.↗
NASA NTRS2010

A Generalized Logical Format for Inter-Calibrated Brightness Temperatures for the Global Precipitation Measurement Mission

An important aspect of the GPM mission is the merging of precipitation data from multiple radiometers on different satellites. This requires that each radiometer be consistently calibrated and that each be intercalibrated with a mission reference standard. For GPM the reference standard is to be the core satellite carrying a dual frequency precipitation radar and a well calibrated conically scanning radiometer. This paper describes a common format for representing these intercalibrated brightness temperatures which will be used for all radiometer products from GPM partner satellites. The use of common formats ensures that users obtain all the required information and also facilitates the rain retrieval algorithm code preparation as it can always except to have the data that it needs for the retrieval.

Stocker, Erich Franz↗
NASA NTRS2005

Multifunctional Logic Gate Controlled by Temperature

A complementary metal oxide/semiconductor (CMOS) electronic circuit has been designed to function as a NAND gate at a temperature between 0 and 80 deg C and as a NOR gate at temperatures from 120 to 200 C. In the intermediate temperature range of 80 to 120 C, this circuit is expected to perform a function intermediate between NAND and NOR with degraded noise margin. The process of designing the circuit and the planned fabrication and testing of the circuit are parts of demonstration of polymorphic electronics a technological discipline that emphasizes designing the same circuit to perform different analog and/or digital functions under different conditions. In this case, the different conditions are different temperatures.

Stoica, Adrian↗
NASA NTRS2005

Multifunctional Logic Gate Controlled by Supply Voltage

A complementary metal oxide/semiconductor (CMOS) electronic circuit functions as a NAND gate at a power-supply potential (V(sub dd)) of 3.3 V and as NOR gate for V(sub dd) = 1.8 V. In the intermediate V(sub dd) range of 1.8 to 3.3 V, this circuit performs a function intermediate between NAND and NOR with degraded noise margin. Like the circuit of the immediately preceding article, this circuit serves as a demonstration of the evolutionary approach to design of polymorphic electronics -- a technological discipline that emphasizes evolution of the design of a circuit to perform different analog and/or digital functions under different conditions. In this instance, the different conditions are different values of V(sub dd).

Stoica, Adrian↗
NASA NTRS2011

Optimal Terminal Descent Guidance Logic to Achieve a Soft Lunar Touchdown

Altair Lunar Lander is the linchpin in the Constellation Program for human return to the Moon. In the 2010design reference mission, Altair is to be delivered to low Earth orbit by the Ares V heavy lift launch vehicle, and after subsequent docking with Orion in LEO, the Altair/Orion stack is delivered through trans-lunar injection (TLI). The Altair/Orion stack separates from the Ares V Earth departure stage shortly after TLI and continues the flight to the Moon as a single stack. Fig. 1 depicts one version of the Altair lunar lander.

Landing↗
NASA NTRS2012

System and method for embedding emotion in logic systems

A system, method, and computer readable-media for creating a stable synthetic neural system. The method includes training an intellectual choice-driven synthetic neural system (SNS), training an emotional rule-driven SNS by generating emotions from rules, incorporating the rule-driven SNS into the choice-driven SNS through an evolvable interface, and balancing the emotional SNS and the intellectual SNS to achieve stability in a nontrivial autonomous environment with a Stability Algorithm for Neural Entities (SANE). Generating emotions from rules can include coding the rules into the rule-driven SNS in a self-consistent way. Training the emotional rule-driven SNS can occur during a training stage in parallel with training the choice-driven SNS. The training stage can include a self assessment loop which measures performance characteristics of the rule-driven SNS against core genetic code. The method uses a stability threshold to measure stability of the incorporated rule-driven SNS and choice-driven SNS using SANE.

Curtis, Steven A.↗
NASA NTRS2013

N Channel JFET Based Digital Logic Gate Structure

An apparatus is provided that includes a first field effect transistor with a source tied to zero volts and a drain tied to voltage drain drain (Vdd) through a first resistor. The apparatus also includes a first node configured to tie a second resistor to a third resistor and connect to an input of a gate of the first field effect transistor in order for the first field effect transistor to receive a signal. The apparatus also includes a second field effect transistor configured as a unity gain buffer having a drain tied to Vdd and an uncommitted source.

Krasowski, Michael J↗
NASA NTRS2014

Lunar Station: The Next Logical Step in Space Development

The International Space Station (ISS) is the product of the efforts of sixteen nations over the course of several decades. It is now complete, operational, and has been continuously occupied since November of 20001. Since then the ISS has been carrying out a wide variety of research and technology development experiments, and starting to produce some pleasantly startling results. The ISS has a mass of 420 metric tons, supports a crew of six with a yearly resupply requirement of around 30 metric tons, within a pressurized volume of 916 cubic meters, and a habitable volume of 388 cubic meters. Its solar arrays produce up to 84 kilowatts of power. In the course of developing the ISS, many lessons were learned and much valuable expertise was gained. Where do we go from here? The ISS offers an existence proof of the feasibility of sustained human occupation and operations in space over decades. It also demonstrates the ability of many countries to work collaboratively on a very complex and expensive project in space over an extended period of time to achieve a common goal. By harvesting best practices and lessons learned, the ISS can also serve as a useful model for exploring architectures for beyond low-­‐ earth-­‐orbit (LEO) space development. This paper will explore the concept and feasibility for a Lunar Station. The Station concept can be implemented by either putting the equivalent capability of the ISS down on the surface of the Moon, or by developing the required capabilities through a combination of delivered materials and equipment and in situ resource utilization (ISRU). Scenarios that leverage existing technologies and capabilities as well as capabilities that are under development and are expected to be available within the next 3-­5 years, will be examined. This paper will explore how best practices and expertise gained from developing and operating the ISS and other relevant programs can be applied to effectively developing Lunar Station.

Lunar↗
NASA NTRS2016

Predictive Lateral Logic for Numerical Entry Guidance Algorithms

Recent entry guidance algorithm development123 has tended to focus on numerical integration of trajectories onboard in order to evaluate candidate bank profiles. Such methods enjoy benefits such as flexibility to varying mission profiles and improved robustness to large dispersions. A common element across many of these modern entry guidance algorithms is a reliance upon the concept of Apollo heritage lateral error (or azimuth error) deadbands in which the number of bank reversals to be performed is non-deterministic. This paper presents a closed-loop bank reversal method that operates with a fixed number of bank reversals defined prior to flight. However, this number of bank reversals can be modified at any point, including in flight, based on contingencies such as fuel leaks where propellant usage must be minimized.

Smith, Kelly M.↗