Resistive contribution in electrical-switching experiments with antiferromagnets
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A new modulation scheme is proposed for current source inverters (CSIs) that reduces the variation and peak junction temperature in the CSIs' power devices. The distributed loss pulse-width modulation (DLM) concept is introduced and applied to traditional space vector modulation methods to develop modified modulation schemes that reduce the thermal stress on power devices. The device junction temperatures resulting from conventional and DLM schemes are compared. Simulation and experimental results confirm that the proposed DLM concept reduces thermal stress on the devices while maintaining the same high output current waveform quality compared to traditional CSI modulation schemes. The CSI power device lifetime (i.e., the number of cycles to failure) are estimated using the simulation and experimental results. The proposed DLM significantly increases the device lifetime (by 5 to 6 times) by reducing the junction temperature variation compared to the conventional modulations.
This paper presents the design and optimization of the high-frequency transformer for an isolated single-stage threephase AC/DC converter enabled by the 4H-SiC BiDirectional Field Effect Transistor (BiDFET). Non-dominated Sorting Genetic Algorithm II (NSGA-II) is used to perform a multiobjective optimization to minimize loss, weight, and volume. A 20 kW, 50 kHz hardware prototype based on the selected optimal point is characterized by a power amplifier. The finite element analysis simulation results are also presented to validate the core magnetic flux density and winding electric field strength. The experimental prototype was tested at 800 Vdc/480 Vrms at 10 kW rated power.
Many recent efforts in developing hardware-accelerated spiking neural networks (SNNs) are characterized by deep co-design between algorithms, architectures, and devices. Architectural advances overcome device constraints by coupling together many small resistive-RAM (ReRAM) crossbars via a network-on-chip (NoC) for neuromorphic component operation. Concurrently, improved SNN training methods increase accuracy and structural sparsity in networks despite growing problem sizes. Finally, compilers leverage these attributes to minimize area and inter-crossbar communication while mapping large SNNs to sophisticated architectures. However, for compiler-driven co-design to realize increasingly complex and profitable optimizations, a compile-time view of power consumption is critical. We present PowerMappeR to express and optimize over mapping-, architecture-, and device-specific power consumption information. By modeling the dynamic power of well-established components, we develop an integer linear programming (ILP)-based, encoding-agnostic, parametric power estimation model. Using this model, we demonstrate practical improvements in area and inter-crossbar communication by 0%–9.5% and 1.4%–5.1%, respectively. We also limit hotspot formation during optimization, achieving comparable or better results in targeted metrics with up to 96.4%–97.1% restriction of hotspot magnitude. Finally, we introduce profile-guided formulations to reduce worst-case and expected-case hotspot magnitude by 40.7%–69.5% and 40.6%–56.3%, respectively. Optimizing worst-case hotspot magnitude incidentally improves expected-case magnitude by 10.85%–33.45%. Reciprocally, optimizing expected-case magnitude incidentally improves worst-case magnitude by 4.33%–39.87%. Validation against hardware simulators confirms that PowerMappeR can decrease dynamic power consumption by 12.6%–27.3%.
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With the emergence of programmable network devices that match the performance of fixed function devices, several recent projects have explored in-network computing, where the processing that is traditionally done outside the network is offloaded to the network devices. In-network computing has typically been applied to network functions (e.g., load balancing, NAT, and DNS), caching, data reduction/aggregation, and coordination/consensus functions. In some cases it has been used to accelerate stream-processing tasks that involve small payloads and simple operations. In this work we focus on leveraging in-network computing for stream processing of scientific datasets with large payloads that require complex operations such as floating-point computations and logarithmic functions. We demonstrate in-network computing for a real-world scientific application performing streaming normalization of a 2-D image from a light source experiment. We discuss the challenges we encountered and potential approaches to address them.